def test_reg_set_get(self): c = ARMv8Core() i = 0 while i < 31: c.reg["X{}".format(i)].set(i + 1) i = i + 1 j = 0 while j < 31: a = c.reg["X{}".format(j)].get(hexa=True) b = c.reg["X{}".format(j)].get(binary=True) self.assertEqual(a, hex(j + 1)) self.assertNotEqual(a, hex(0)) self.assertEqual(b, "{0:b}".format(j + 1)) self.assertNotEqual(b, "{0:b}".format(0)) j = j + 1 self.assertEqual(i, j)
def test_reg_aliases(self): c = ARMv8Core() c.reg["IP0"].set(10) self.assertEqual(c.reg["IP0"].get(), c.reg["X16"].get()) self.assertEqual(c.reg["IP0"], c.reg["X16"])
def test_orr(self): c = ARMv8Core() c.reg["X0"].set(10) c.reg["X1"].set(25) armv8_isa.ORR.execute(c, "X0", 0, "X1", "X2") self.assertEqual(c.reg["X2"].get(), 27)
def test_eor(self): c = ARMv8Core() c.reg["X0"].set(10) c.reg["X1"].set(5) armv8_isa.EOR.execute(c, "X0", 0, "X1", "X2") self.assertEqual(c.reg["X2"].get(), 15)
def test_lsr(self): c = ARMv8Core() c.reg["X0"].set(2) c.reg["X1"].set(40) armv8_isa.LSR.execute(c, "X0", 0, "X1", "X2") self.assertEqual(c.reg["X2"].get(), 10)
def test_umulh(self): c = ARMv8Core() c.reg["X0"].set(10) c.reg["X1"].set(5) armv8_isa.UMULH.execute(c, "X0", 0, "X1", "X2") self.assertEqual(c.reg["X2"].get(), 50)
def test_sdiv(self): c = ARMv8Core() c.reg["X0"].set(5) c.reg["X1"].set(10) armv8_isa.SDIV.execute(c, "X0", 0x02, "X1", "X2") self.assertEqual(c.reg["X2"].get(), 2)
def test_subs(self): c = ARMv8Core() c.reg["X0"].set(1) armv8_isa.SUBS.execute(c, "X0", 0, "X0", "X0") self.assertEqual(c.flag_zero, True)
def test_mul(self): c = ARMv8Core() c.reg["X0"].set(10) c.reg["X1"].set(5) armv8_isa.MUL.execute(c, "X0", 0x1F, "X1", "X2") self.assertEqual(c.reg["X2"].get(), 50)
def test_adds(self): c = ARMv8Core() c.reg["X0"].set(0) armv8_isa.ADDS.execute(c, "X0", 0, "X0", "X0") self.assertEqual(c.flag_zero, True)
def test_sub(self): c = ARMv8Core() c.reg["X0"].set(3) c.reg["X1"].set(4) armv8_isa.SUB.execute(c, "X0", 0, "X1", "X2") self.assertEqual(c.reg["X2"].get(), 1)
def test_add(self): c = ARMv8Core() c.reg["X0"].set(1) c.reg["X1"].set(1) armv8_isa.ADD.execute(c, "X0", 0, "X1", "X2") self.assertEqual(c.reg["X2"].get(), 2)
def test_addi(self): c = ARMv8Core() c.reg["X0"].set(1) armv8_isa.ADDI.execute(c, 1, "X0", "X1") # immediate = 1 self.assertEqual(c.reg["X1"].get(), 2)
def test_orri(self): c = ARMv8Core() c.reg["X0"].set(25) armv8_isa.ORRI.execute(c, 10, "X0", "X1") # immediate = 1 self.assertEqual(c.reg["X1"].get(), 27)
def test_andi(self): c = ARMv8Core() c.reg["X0"].set(20) armv8_isa.ANDI.execute(c, 5, "X0", "X1") # immediate = 1 self.assertEqual(c.reg["X1"].get(), 4)
def test_subis(self): c = ARMv8Core() c.reg["X1"].set(1) armv8_isa.SUBIS.execute(c, 1, "X1", "X1") self.assertEqual(c.flag_zero, True)