def on_activate(self, e):
""" Connect and configure the access to the FPGA.
@param object e: Event class object from Fysom.
An object created by the state machine module Fysom,
which is connected to a specific event (have a look in
the Base Class). This object contains the passed event
the state before the event happens and the destination
of the state which should be reached after the event
has happen.
"""
config = self.getConfiguration()
if 'fpgacounter_serial' in config.keys():
self._fpgacounter_serial = config['fpgacounter_serial']
else:
self.log.warning('No serial number defined for fpga counter')
if 'fpgacounter_channel_apd_0' in config.keys():
self._channel_apd_0 = config['fpgacounter_channel_apd_0']
else:
self.log.warning('No apd0 channel defined for fpga counter')
if 'fpgacounter_channel_apd_1' in config.keys():
self._channel_apd_1 = config['fpgacounter_channel_apd_1']
else:
self.log.warning('No apd1 channel defined for fpga counter')
if 'fpgacounter_channel_detect' in config.keys():
self._channel_detect = config['fpgacounter_channel_detect']
else:
self.log.warning('No no detect channel defined for fpga counter')
if 'fpgacounter_channel_sequence' in config.keys():
self._channel_sequence = config['fpgacounter_channel_sequence']
else:
self.log.warning('No sequence channel defined for fpga counter')
tt._Tagger_setSerial(self._fpgacounter_serial)
thirdpartypath = os.path.join(self.get_main_dir(), 'thirdparty')
bitfilepath = os.path.join(thirdpartypath, 'stuttgart_counter',
'TimeTaggerController.bit')
tt._Tagger_setBitfilePath(bitfilepath)
del bitfilepath, thirdpartypath
self._number_of_gates = int(100)
self._bin_width = 1
self._record_length = int(4000)
self.configure(self._bin_width * 1e-9, self._record_length * 1e-9,
self._number_of_gates)
self.statusvar = 0
def configure(self, bin_width_s, record_length_s, number_of_gates=0):
""" Configuration of the fast counter.
@param float bin_width_s: Length of a single time bin in the time trace
histogram in seconds.
@param float record_length_s: Total length of the timetrace/each single
gate in seconds.
@param int number_of_gates: optional, number of gates in the pulse
sequence. Ignore for not gated counter.
@return tuple(binwidth_s, gate_length_s, number_of_gates):
binwidth_s: float the actual set binwidth in seconds
gate_length_s: the actual set gate length in seconds
number_of_gates: the number of gated, which are accepted
"""
self._number_of_gates = number_of_gates
self._bin_width = bin_width_s * 1e9
self._record_length = int(record_length_s / bin_width_s)
self.statusvar = 1
self.pulsed = tt.Pulsed(self._record_length,
int(np.round(self._bin_width * 1000)),
self._number_of_gates, self._channel_apd_0,
self._channel_detect, self._channel_sequence)
return (bin_width_s, record_length_s, number_of_gates)
def on_activate(self):
""" Connect and configure the access to the FPGA.
"""
config = self.getConfiguration()
if 'fpgacounter_serial' in config.keys():
self._fpgacounter_serial = config['fpgacounter_serial']
else:
self.log.warning('No serial number defined for fpga counter')
if 'fpgacounter_channel_apd_0' in config.keys():
self._channel_apd_0 = config['fpgacounter_channel_apd_0']
else:
self.log.warning('No apd0 channel defined for fpga counter')
if 'fpgacounter_channel_apd_1' in config.keys():
self._channel_apd_1 = config['fpgacounter_channel_apd_1']
else:
self.log.warning('No apd1 channel defined for fpga counter')
if 'fpgacounter_channel_detect' in config.keys():
self._channel_detect = config['fpgacounter_channel_detect']
else:
self.log.warning('No no detect channel defined for fpga counter')
if 'fpgacounter_channel_sequence' in config.keys():
self._channel_sequence = config['fpgacounter_channel_sequence']
else:
self.log.warning('No sequence channel defined for fpga counter')
tt._Tagger_setSerial(self._fpgacounter_serial)
thirdpartypath = os.path.join(self.get_main_dir(), 'thirdparty')
bitfilepath = os.path.join(thirdpartypath, 'stuttgart_counter',
'TimeTaggerController.bit')
tt._Tagger_setBitfilePath(bitfilepath)
del bitfilepath, thirdpartypath
self._number_of_gates = int(100)
self._bin_width = 1
self._record_length = int(4000)
self.configure(self._bin_width * 1e-9, self._record_length * 1e-9,
self._number_of_gates)
self.statusvar = 0
def on_activate(self):
""" Connect and configure the access to the FPGA.
"""
tt._Tagger_setSerial(self._fpgacounter_serial)
thirdpartypath = os.path.join(get_main_dir(), 'thirdparty')
bitfilepath = os.path.join(thirdpartypath, 'stuttgart_counter',
'TimeTaggerController.bit')
tt._Tagger_setBitfilePath(bitfilepath)
del bitfilepath, thirdpartypath
self._number_of_gates = int(100)
self._bin_width = 1
self._record_length = int(4000)
self.configure(self._bin_width * 1e-9, self._record_length * 1e-9,
self._number_of_gates)
self.statusvar = 0
def on_activate(self):
""" Connect and configure the access to the FPGA.
"""
tt._Tagger_setSerial(self._fpgacounter_serial)
thirdpartypath = os.path.join(get_main_dir(), 'thirdparty')
bitfilepath = os.path.join(thirdpartypath, 'stuttgart_counter', 'TimeTaggerController.bit')
tt._Tagger_setBitfilePath(bitfilepath)
del bitfilepath, thirdpartypath
self._number_of_gates = int(100)
self._bin_width = 1
self._record_length = int(4000)
self.configure(
self._bin_width * 1e-9,
self._record_length * 1e-9,
self._number_of_gates)
self.statusvar = 0
def on_activate(self):
""" Connect and configure the access to the FPGA.
"""
config = self.getConfiguration()
if 'fpgacounter_serial' in config.keys():
self._fpgacounter_serial=config['fpgacounter_serial']
else:
self.log.warning('No serial number defined for fpga counter')
if 'fpgacounter_channel_apd_0' in config.keys():
self._channel_apd_0 = config['fpgacounter_channel_apd_0']
else:
self.log.warning('No apd0 channel defined for fpga counter')
if 'fpgacounter_channel_apd_1' in config.keys():
self._channel_apd_1 = config['fpgacounter_channel_apd_1']
else:
self.log.warning('No apd1 channel defined for fpga counter')
if 'fpgacounter_channel_detect' in config.keys():
self._channel_detect = config['fpgacounter_channel_detect']
else:
self.log.warning('No no detect channel defined for fpga counter')
if 'fpgacounter_channel_sequence' in config.keys():
self._channel_sequence = config['fpgacounter_channel_sequence']
else:
self.log.warning('No sequence channel defined for fpga counter')
tt._Tagger_setSerial(self._fpgacounter_serial)
thirdpartypath = os.path.join(self.get_main_dir(), 'thirdparty')
bitfilepath = os.path.join(thirdpartypath, 'stuttgart_counter', 'TimeTaggerController.bit')
tt._Tagger_setBitfilePath(bitfilepath)
del bitfilepath, thirdpartypath
self._number_of_gates = int(100)
self._bin_width = 1
self._record_length = int(4000)
self.configure(self._bin_width*1e-9,self._record_length*1e-9,self._number_of_gates)
self.statusvar = 0