# Processor Configuration Register: contains informations on the processor
# configuration (num reg win, etc.)
PCR = trap.Register('PCR', 32)
PCR.setDefaultValue(0x02700300)
processor.addRegister(PCR)
# Ancillary State Registers
# in the LEON2 processor some of them have a special meaning:
# 24-31 are used for hardware breakpoints
# 17 is the processor configuration register
asrRegs = trap.RegisterBank('ASR', 32, 32)
processor.addRegBank(asrRegs)
# Now I set the alias: they can (and will) be used by the instructions
# to access the registers more easily. Note that, in general, it is
# responsibility of the programmer keeping the aliases updated
regs = trap.AliasRegBank('REGS', 32, ('GLOBAL[0-7]', 'WINREGS[0-23]'))
regs.setFixed([0, 1, 2, 3, 4, 5, 6, 7])
regs.setCheckGroup()
processor.addAliasRegBank(regs)
FP = trap.AliasRegister('FP', 'REGS[30]')
FP.setFixed()
processor.addAliasReg(FP)
LR = trap.AliasRegister('LR', 'REGS[31]')
LR.setFixed()
processor.addAliasReg(LR)
SP = trap.AliasRegister('SP', 'REGS[14]')
SP.setFixed()
processor.addAliasReg(SP)
# Now I add the registers which I want to see printed in the instruction trace
# COMMENT FOR COMPARISON
'F': (6, 6),
'mode': (0, 3)
}
cpsr = trap.Register('CPSR', 32, cpsrBitMask)
cpsr.setDefaultValue(0x000000D3)
processor.addRegister(cpsr)
# Fake register (not presented in the architecture) indicating
# the processor ID: it is necessary in a multi-processor
# system
mp_id = trap.Register('MP_ID', 32)
mp_id.setDefaultValue('MPROC_ID')
processor.addRegister(mp_id)
# Now I set the alias: they can (and will) be used by the instructions
# to access the registers more easily. Note that, in general, it is
# responsibility of the programmer keeping the alias updated
regs = trap.AliasRegBank('REGS', 16, 'RB[0-15]')
regs.setOffset(15, 4)
processor.addAliasRegBank(regs)
FP = trap.AliasRegister('FP', 'REGS[11]')
processor.addAliasReg(FP)
SP = trap.AliasRegister('SPTR', 'REGS[13]')
processor.addAliasReg(SP)
LR = trap.AliasRegister('LINKR', 'REGS[14]')
processor.addAliasReg(LR)
SP_SVC = trap.AliasRegister('SP_SVC', 'RB[15]')
processor.addAliasReg(SP_SVC)
LR_SVC = trap.AliasRegister('LR_SVC', 'RB[16]')
processor.addAliasReg(LR_SVC)
SP_ABT = trap.AliasRegister('SP_ABT', 'RB[17]')
processor.addAliasReg(SP_ABT)