def __init__(self, slot_idx, **kwargs):
DboardManagerBase.__init__(self, slot_idx, **kwargs)
self.log = get_logger("Rhodium-{}".format(slot_idx))
self.log.trace("Initializing Rhodium daughterboard, slot index %d",
self.slot_idx)
self.rev = int(self.device_info['rev'])
self.log.trace("This is a rev: {}".format(chr(65 + self.rev)))
# This is a default ref clock freq, it must be updated before init() is
# called!
self.ref_clock_freq = None
# These will get updated during init()
self.master_clock_rate = None
self.sampling_clock_rate = None
self.current_jesd_rate = None
# Predeclare some attributes to make linter happy:
self.lmk = None
self._port_expander = None
self._lo_dist = None
self.cpld = None
# If _init_args is None, it means that init() hasn't yet been called.
self._init_args = None
# Now initialize all peripherals. If that doesn't work, put this class
# into a non-functional state (but don't crash, or we can't talk to it
# any more):
try:
self._init_periphs()
self._periphs_initialized = True
except Exception as ex:
self.log.error("Failed to initialize peripherals: %s",
str(ex))
self._periphs_initialized = False
def __init__(self, slot_idx, **kwargs):
DboardManagerBase.__init__(self, slot_idx, **kwargs)
self.log = get_logger("ZBX-{}".format(slot_idx))
self.log.trace("Initializing ZBX daughterboard, slot index %d",
self.slot_idx)
# local variable to track if PLL ref clock is enabled for the CPLD logic
self._clock_enabled = False
# Interface with MB HW
if 'db_iface' not in kwargs:
self.log.error("Required DB Iface was not provided!")
raise RuntimeError("Required DB Iface was not provided!")
self.db_iface = kwargs['db_iface']
self.eeprom_symbol = f"db{slot_idx}_eeprom"
eeprom = self._get_eeprom()
self._assert_rev_compatibility(eeprom["rev_compat"])
# Initialize daughterboard CPLD control
self.poke_cpld = self.db_iface.poke_db_cpld
self.peek_cpld = self.db_iface.peek_db_cpld
self.regs = zbx_cpld_regs_t()
self._spi_addr = self.regs.SPI_READY_addr
self._enable_base_power()
# Check register map compatibility
self._check_compat_version()
self.log.debug("ZBX CPLD build git hash: %s",
self._get_cpld_git_hash())
# Power up the DB
self._enable_power()
# enable PLL reference clock
self.reset_clock(False)
self._cpld_set_safe_defaults()
def __init__(self, slot_idx, **kwargs):
DboardManagerBase.__init__(self, slot_idx, **kwargs)
self.log = get_logger("X4xxDebugDboard-{}".format(slot_idx))
self.log.trace("Initializing X4xxDebug daughterboard, slot index %d",
self.slot_idx)
# Interface with MB HW
if 'db_iface' not in kwargs:
self.log.error("Required DB Iface was not provided!")
raise RuntimeError("Required DB Iface was not provided!")
self.db_iface = kwargs['db_iface']
# Power on the card
self.db_iface.enable_daughterboard(enable=True)
if not self.db_iface.check_enable_daughterboard():
self.db_iface.enable_daughterboard(enable=False)
self.log.error('Debug dboard {} power up failed'.format(self.slot_idx))
raise RuntimeError('Debug dboard {} power up failed'.format(self.slot_idx))
self._paths = {
"a": DebugDboardSignalPath(
slot_idx,
"A",
{
"adc0": 1,
"adc2": 0,
},
{
"dac0": 1,
"dac2": 0,
},
1 # TRXA_CTRL=1 enables loopback
),
"b": DebugDboardSignalPath(
slot_idx,
"B",
{
"adc3": 1,
"adc1": 0,
},
{
"dac3": 1,
"dac1": 0,
},
0 # TRXB_CTRL=0 enables loopback
),
}
def __init__(self, slot_idx, **kwargs):
DboardManagerBase.__init__(self, slot_idx, **kwargs)
self.log = get_logger("EmptyDB-{}".format(slot_idx))
self.log.trace("Initializing Empty dboard, slot index %d",
self.slot_idx)
def __init__(self, slot_idx, **kwargs):
DboardManagerBase.__init__(self, slot_idx, **kwargs)
self.log = get_logger("X4xxIfTestCCA-{}".format(slot_idx))
self.log.trace("Initializing X4xxIfTestCCA, slot index %d",
self.slot_idx)
# Interface with MB HW
if 'db_iface' not in kwargs:
self.log.error("Required DB Iface was not provided!")
raise RuntimeError("Required DB Iface was not provided!")
self.db_iface = kwargs['db_iface']
# Power on the card
self.db_iface.enable_daughterboard(enable=True)
if not self.db_iface.check_enable_daughterboard():
self.db_iface.enable_daughterboard(enable=False)
self.log.error('IF Test CCA {} power up failed'.format(self.slot_idx))
raise RuntimeError('IF Test CCA {} power up failed'.format(self.slot_idx))
# [boolean for stage 1 mux , boolean for stage 2 mux]
self._adc_mux_settings = {
"adc0" : [0, 0],
"adc1" : [1, 1],
"adc2" : [1, 0],
"adc3" : [0, 1],
}
self._dac_mux_settings = {
"dac0" : [1, 0],
"dac1" : [1, 1],
"dac2" : [0, 0],
"dac3" : [0, 1],
}
# There are 4 possible Tx (DAC) streams that are available to choose
# to export to the SMA TX port using a 2-stage hardware mux.
# Choose between 0 and 2 OR 1 and 3
self.tx_0_2_1_3_mux_ctrl = Gpio("DB{}_TX0_2p_1_3n".format(slot_idx), Gpio.OUTPUT, 0)
# Choose between 0 OR 2
self.tx_0_2_mux_ctrl = Gpio("DB{}_TX_MUX_0p_2n".format(slot_idx), Gpio.OUTPUT, 0)
# Choose between 1 OR 3
self.tx_1_3_mux_ctrl = Gpio("DB{}_TX_MUX_1p_3n".format(slot_idx), Gpio.OUTPUT, 0)
# The signal from the SMA RX port can be directed to one of the 4
# available Rx (ADC) streams using a 2-stage hardware mux.
# Choose between 0 and 2 OR 1 and 3
self.rx_0_2_1_3_mux_ctrl = Gpio("DB{}_RX0_2p_1_3n".format(slot_idx), Gpio.OUTPUT, 0)
# Choose between 0 OR 2
self.rx_0_2_mux_ctrl = Gpio("DB{}_RX_MUX_0p_2n".format(slot_idx), Gpio.OUTPUT, 0)
# Choose between 1 OR 3
self.rx_1_3_mux_ctrl = Gpio("DB{}_RX_MUX_1p_3n".format(slot_idx), Gpio.OUTPUT, 0)
self._tx_path = ""
self._rx_path = ""
# Controls to load the power supplies on the daughterboard. Enabling
# these will increase the power draw of the daughterboard.
self.enable_1v8_load = Gpio("DB{}_1V8_LOAD".format(slot_idx), Gpio.OUTPUT, 0)
self.enable_2v5_load = Gpio("DB{}_2V5_LOAD".format(slot_idx), Gpio.OUTPUT, 0)
self.enable_3v3_load = Gpio("DB{}_3V3_LOAD".format(slot_idx), Gpio.OUTPUT, 0)
self.enable_3v3_mcu_load = Gpio("DB{}_3V3_MCU_LOAD".format(slot_idx), Gpio.OUTPUT, 0)
self.enable_3v7_load = Gpio("DB{}_3V7_LOAD".format(slot_idx), Gpio.OUTPUT, 0)
self.enable_12v_load = Gpio("DB{}_12V_LOAD".format(slot_idx), Gpio.OUTPUT, 0)
# Control to choose between DAC output or MB VCM signals as the VCM
# signal to use on board.
self.disable_vcm_dac = Gpio("DB{}_VCM_MB_nDAC".format(slot_idx), Gpio.OUTPUT, 0)
# Control to choose which MB clock to output to the SMA Clock port.
# Choices are BaseRefClk and PllRefClk
self.disable_vcm_dac = Gpio("DB{}_REF_CLK_SEL_USR".format(slot_idx), Gpio.OUTPUT, 0)