def test_cmp_2():
name = f'ckt_{get_test_id()}'
netlist = circuits.comparator(name)
setup = textwrap.dedent("""\
POWER = vccx
GND = vssx
""")
constraints = [
{"constraint": "GroupBlocks", "instances": ["mn1", "mn2"], "name": "dp"},
{"constraint": "GroupBlocks", "instances": ["mn3", "mn4"], "name": "ccn"},
{"constraint": "GroupBlocks", "instances": ["mp5", "mp6"], "name": "ccp"},
{"constraint": "GroupBlocks", "instances": ["mn11", "mp13"], "name": "invp"},
{"constraint": "GroupBlocks", "instances": ["mn12", "mp14"], "name": "invn"},
{"constraint": "SameTemplate", "instances": ["mp7", "mp8"]},
{"constraint": "SameTemplate", "instances": ["mp9", "mp10"]},
{"constraint": "SameTemplate", "instances": ["invn", "invp"]},
{"constraint": "SymmetricBlocks", "direction": "V",
"pairs": [["ccp"], ["ccn"], ["dp"], ["mn0"], ["invn", "invp"], ["mp7", "mp8"], ["mp9", "mp10"]]},
{"constraint": "Order", "direction": "top_to_bottom", "instances": ["invn", "ccp", "ccn", "dp", "mn0"]},
{"constraint": "Order", "direction": "top_to_bottom", "instances": ["invn", "mp9", "mp7", "mn0"]},
{"constraint": "MultiConnection", "nets": ["vcom"], "multiplier": 6},
{"constraint": "AspectRatio", "subcircuit": name, "ratio_low": 0.5, "ratio_high": 1.5}
]
example = build_example(name, netlist, setup, constraints)
run_example(example, cleanup=cleanup, area=5e9)
def test_tia():
name = f'ckt_{get_test_id()}'
netlist = circuits.tia(name)
setup = ""
constraints = []
example = build_example(name, netlist, setup, constraints)
run_example(example, cleanup=cleanup)
def test_do_not_identify():
name = f'ckt_{get_test_id()}'
netlist = circuits.ota_five(name)
constraints = [{
"constraint": "AlignInOrder",
"line": "left",
"instances": ["mp1", "mn1"]
}]
example = build_example(name, netlist, constraints)
run_example(example)
def test_boundary_max_height():
name = f'ckt_{get_test_id()}'
netlist = circuits.cascode_amplifier(name)
constraints = [{
"constraint": "Boundary",
"subcircuit": "example_boundary_max_height",
"max_height": 1.3
}]
example = build_example(name, netlist, constraints)
run_example(example)
def test_aspect_ratio_high():
name = f'ckt_{get_test_id()}'
netlist = circuits.cascode_amplifier(name)
constraints = [{
"constraint": "AspectRatio",
"subcircuit": "example_aspect_ratio_max",
"ratio_high": 1
}]
example = build_example(name, netlist, constraints)
run_example(example)
def test_cmp_pg():
name = f'ckt_{get_test_id()}'
netlist = circuits.comparator(name)
setup = textwrap.dedent("""\
POWER = vccx
GND = vssx
""")
constraints = []
example = build_example(name, netlist, setup, constraints)
run_example(example, cleanup=cleanup)
def test_ldo_amp():
name = f'ckt_{get_test_id()}'
netlist = circuits.ldo_amp(name)
setup = textwrap.dedent("""\
POWER = vccx
GND = vssx
DONT_USE_CELLS = CASCODED_CMC_NMOS CMB_PMOS_2 LSB_PMOS_2 LSB_NMOS_2
""")
constraints = []
example = build_example(name, netlist, setup, constraints)
run_example(example, cleanup=cleanup)
def test_ota_six():
name = f'ckt_{get_test_id()}'
netlist = circuits.ota_six(name)
setup = textwrap.dedent(f"""\
DONT_CONST = {name}
""")
constraints = [
{"constraint": "GroupBlocks", "instances": ["mn1", "mn2"], "name": "g1"},
{"constraint": "GroupBlocks", "instances": ["mn3", "mn4"], "name": "g2"},
{"constraint": "GroupBlocks", "instances": ["mp5", "mp6"], "name": "g3"},
{"constraint": "AspectRatio", "subcircuit": name, "ratio_low": 0.01, "ratio_high": 100}]
example = build_example(name, netlist, setup, constraints)
run_example(example, cleanup=cleanup, log_level='DEBUG')
def test_cs_grid():
name = f'ckt_{get_test_id()}'
netlist = circuits.common_source_mini(name)
setup = textwrap.dedent("""\
POWER = vccx
GND = vssx
""")
constraints = [{
"constraint": "AlignInOrder",
"line": "left",
"instances": ["mp0", "mn0"]
}]
example = build_example(name, netlist, setup, constraints)
run_example(example, cleanup=cleanup)
def test_cmp_0():
name = f'ckt_{get_test_id()}'
netlist = circuits.comparator(name)
setup = ""
constraints = []
example = build_example(name, netlist, setup, constraints)
ckt_dir, run_dir = run_example(example, cleanup=cleanup)
def test_ro_1():
name = f'ckt_{get_test_id()}'
setup = textwrap.dedent("""\
DONT_CONST = {name}
""")
netlist = textwrap.dedent(f"""\
.subckt ro_stage vi vo vccx vssx
mp0 vo vi vccx vccx p w=360e-9 m=1 nf=2
mn0 vo vi vssx vssx n w=360e-9 m=1 nf=2
.ends
.subckt {name} vo vccx vssx
xi0 vo v1 vccx vssx ro_stage
xi1 v1 v2 vccx vssx ro_stage
xi2 v2 v3 vccx vssx ro_stage
xi3 v3 v4 vccx vssx ro_stage
xi4 v4 vo vccx vssx ro_stage
.ends {name}
""")
constraints = {
'ro_stage': [
{"constraint": "Order", "direction": "left_to_right", "instances": ["mn0", "mp0"]},
],
name: [
{"constraint": "Order", "direction": "left_to_right", "instances": [f'xi{k}' for k in range(5)]},
]
}
example = build_example(name, netlist, setup, constraints)
ckt_dir, run_dir = run_example(example, cleanup=cleanup)
with (run_dir / '3_pnr' / 'inputs' / 'RO_STAGE.pnr.const.json').open('rt') as fp:
d = json.load(fp)
assert len(d['constraints']) > 0, 'Where is the order constraint???'
def test_align_center():
name = f'ckt_{get_test_id()}'
netlist = textwrap.dedent(f"""\
.subckt {name} vin vop vcc vss nbs pbs
mp1 vop pbs vcc vcc p w=720e-9 nf=4 m=8
mn1 vop nbs vmd vss n w=720e-9 nf=4 m=6
mn0 vmd vin vss vss n w=720e-9 nf=4 m=16
.ends {name}
""")
constraints = [{
"constraint": "AlignInOrder",
"direction": "vertical",
"line": "center",
"instances": ["mn0", "mn1", "mp1"]
}]
example = build_example(name, netlist, constraints)
run_example(example)
def test_cmp_3():
name = f'ckt_{get_test_id()}'
netlist = circuits.comparator(name)
setup = textwrap.dedent("""\
POWER = vccx
GND = vssx
CLOCK = clk
""")
constraints = [
{"constraint": "GroupBlocks", "instances": ["mn1", "mn2"], "name": "dp"},
{"constraint": "GroupBlocks", "instances": ["mn3", "mn4"], "name": "ccn"},
{"constraint": "GroupBlocks", "instances": ["mp5", "mp6"], "name": "ccp"},
{"constraint": "SymmetricBlocks", "direction": "V", "pairs": [["mn0"], ["dp"]]},
{"constraint": "SymmetricBlocks", "direction": "V", "pairs": [["ccp"], ["ccn"]]},
{"constraint": "Order", "direction": "top_to_bottom", "instances": ["mn0", "dp"]},
{"constraint": "Order", "direction": "top_to_bottom", "instances": ["ccp", "ccn"]},
{"constraint": "AlignInOrder", "line": "bottom", "instances": ["dp", "ccn"]}
]
example = build_example(name, netlist, setup, constraints)
run_example(example, cleanup=cleanup, area=3.5e9)
def test_dig_1():
name = f'ckt_{get_test_id()}'
setup = textwrap.dedent(f"""\
DONT_CONST = {name}
""")
netlist = textwrap.dedent(f"""\
.subckt dig22inv a o vccx vssx
mp0 o a vccx vccx p w=45e-9 m=1 nf=1
mn0 o a vssx vssx n w=45e-9 m=1 nf=1
.ends
.subckt {name} vi vo vccx vssx
xi0 vi v1 vccx vssx dig22inv
xi1 v1 v2 vccx vssx dig22inv
xi2 v2 vo vccx vssx dig22inv
.ends {name}
.END
""")
constraints = [{
"constraint": "AlignInOrder",
"line": "bottom",
"instances": ["xi0", "xi1", "xi2"]
}]
example = build_example(name, netlist, setup, constraints)
run_example(example, cleanup=cleanup)
def test_donotroute():
name = f'ckt_{get_test_id()}'
netlist = textwrap.dedent(f"""\
.subckt inv vi vo vccx vssx
mp0 vo vi vccx vccx p w=360e-9 m=1 nf=2
mn0 vo vi vssx vssx n w=360e-9 m=1 nf=2
.ends
.subckt {name} vi vo vccx vssx
xi0 vi v1 vccx vssx inv
xi1 v1 vo vccx vssx inv
.ends
""")
constraints = [{
"constraint": "AutoConstraint",
"isTrue": False
}, {
"constraint": "PowerPorts",
"ports": ["vccx"]
}, {
"constraint": "GroundPorts",
"ports": ["vssx"]
}, {
"constraint": "DoNotRoute",
"nets": ["v1", "vccx", "vssx"]
}]
example = build_example(name, netlist, constraints)
_, run_dir = run_example(example, cleanup=False)
# There should be opens in the generated layout
with (run_dir / '3_pnr' / f'{name.upper()}_0.json').open('rt') as fp:
d = json.load(fp)
cv = CanvasPDK()
cv.terminals = d['terminals']
cv.removeDuplicates()
assert len(cv.rd.opens) > 0, 'Layout should have opens'
# The generated and loaded files should be identical
input_dir = run_dir / '3_pnr' / 'inputs'
verilog_d = VerilogJsonTop.parse_file(input_dir /
f'{name.upper()}.verilog.json')
constraint_files_l, pnr_const_ds_l = load_constraint_files(input_dir)
constraint_files_g, pnr_const_ds_g = gen_constraint_files(
verilog_d, input_dir)
assert constraint_files_l == constraint_files_g
assert pnr_const_ds_l == pnr_const_ds_g
def test_dependencies():
name = f'ckt_{get_test_id()}'
netlist = circuits.tia(name)
setup = ""
constraints = []
example = build_example(name, netlist, setup, constraints)
ckt_dir, run_dir = run_example(example, cleanup=False)
with (run_dir / '2_primitives' / '__primitives__.json').open('rt') as fp:
primitives = json.load(fp)
assert 'metadata' in primitives[
'TFR_PRIM_L_1E06_W_1E06'], 'Metadata not found'
with (run_dir / '3_pnr' / 'Results' /
f'{name.upper()}_0.placement_verilog.json').open('rt') as fp:
placement = json.load(fp)
assert 'modules' in placement, 'modules not in placement'
shutil.rmtree(run_dir)
shutil.rmtree(ckt_dir)
def test_cmp_order():
""" mp7 and mp8 should not be identified as a primitive """
name = f'ckt_{get_test_id()}'
netlist = circuits.comparator(name)
setup = ""
constraints = [{"constraint": "Order", "direction": "left_to_right", "instances": ["mp7", "mp8"]}]
name = f'ckt_{get_test_id()}'
example = build_example(name, netlist, setup, constraints)
ckt_dir, run_dir = run_example(example, cleanup=False)
with (run_dir / '1_topology' / f'{name.upper()}.verilog.json').open('rt') as fp:
verilog_json = json.load(fp)
module_found = False
for module in verilog_json['modules']:
if module['name'] == name.upper():
module_found = True
instances = set([k['instance_name'] for k in module['instances']])
assert 'MP7' in instances and 'MP8' in instances, f'MP7 or MP8 not found in {instances}'
assert module_found, f'Module {name.upper()} not found in {name.upper()}verilog.json'
if cleanup:
shutil.rmtree(run_dir)
shutil.rmtree(ckt_dir)
def test_1():
name = f'ckt_{get_test_id()}'
netlist = textwrap.dedent(f"""\
.subckt {name} vbias2 vccx
mp29 v4 vbias2 v2 vccx p w=2.16e-6 m=1 nf=12
mp33 vbias2 vbias2 vbias1 vccx p w=1.44e-6 m=1 nf=8
.ends {name}
""")
setup = textwrap.dedent("""\
POWER = vccx
GND =
""")
constraints = []
example = build_example(name, netlist, setup, constraints)
ckt_dir, run_dir = run_example(example, cleanup=False)
with (run_dir / '1_topology' / '__primitives__.json').open('rt') as fp:
primitives = json.load(fp)
for key, _ in primitives.items():
assert key.startswith('PMOS') or key.startswith(
'DCL'), f"Incorrect subcircuit identification {key}"
shutil.rmtree(run_dir)
shutil.rmtree(ckt_dir)
def test_cmp_noconst():
name = f'ckt_{get_test_id()}'
netlist = circuits.comparator(name)
setup = textwrap.dedent(f"""\
POWER = vccx
GND = vssx
DONT_CONST = {name}
""")
constraints = []
example = build_example(name, netlist, setup, constraints)
ckt_dir, run_dir = run_example(example, cleanup=False)
with (run_dir / '1_topology' / f'{name.upper()}.verilog.json').open('rt') as fp:
verilog_json = json.load(fp)
module_found = False
for module in verilog_json['modules']:
if module['name'] == name.upper():
module_found = True
assert len(module['constraints']) == 0, "Constraints generated despise DONT_CONST"
assert module_found, f'Module {name.upper()} not found in {name.upper()}verilog.json'
if cleanup:
shutil.rmtree(run_dir)
shutil.rmtree(ckt_dir)
def test_cmp():
name = f'ckt_{get_test_id()}'
netlist = circuits.comparator(name)
setup = ""
constraints = []
example = build_example(name, netlist, setup, constraints)
ckt_dir, run_dir = run_example(example, cleanup=False, area=4.5e9)
# TODO: Generalize this test to all primitives based on m value
with (run_dir / '1_topology' / '__primitives__.json').open('rt') as fp:
primitives = json.load(fp)
counter = 0
for m in primitives.keys():
if m.startswith('DP_NMOS'):
counter += 1
assert counter == 6, f'Diff pair in comparator should have 6 variants. Found {counter}.'
if cleanup:
shutil.rmtree(run_dir)
shutil.rmtree(ckt_dir)
if cleanup:
shutil.rmtree(run_dir)
shutil.rmtree(ckt_dir)
def test_order_abut():
name = f'ckt_{get_test_id()}'
netlist = circuits.comparator(name)
constraints = [{
"constraint": "PowerPorts",
"ports": ["VCCX"]
}, {
"constraint": "GroundPorts",
"ports": ["VSSX"]
}, {
"constraint": "GroupBlocks",
"instances": ["mn1", "mn2"],
"name": "dp"
}, {
"constraint": "GroupBlocks",
"instances": ["mn3", "mn4"],
"name": "ccn"
}, {
"constraint": "GroupBlocks",
"instances": ["mp5", "mp6"],
"name": "ccp"
}, {
"constraint": "GroupBlocks",
"instances": ["mn11", "mp13"],
"name": "invp"
}, {
"constraint": "GroupBlocks",
"instances": ["mn12", "mp14"],
"name": "invn"
}, {
"constraint":
"SymmetricBlocks",
"direction":
"V",
"pairs": [["ccp"], ["ccn"], ["dp"], ["mn0"], ["invn", "invp"],
["mp7", "mp8"], ["mp9", "mp10"]]
}, {
"constraint": "Order",
"direction": "top_to_bottom",
"instances": ["invn", "ccp", "ccn", "dp", "mn0"]
}, {
"constraint": "Order",
"direction": "top_to_bottom",
"instances": ["invn", "mp9", "mp7", "mn0"]
}, {
"constraint": "MultiConnection",
"nets": ["vcom"],
"multiplier": 6
}, {
"constraint": "AspectRatio",
"subcircuit": "comparator",
"ratio_low": 0.5,
"ratio_high": 1.5
}, {
"constraint": "Order",
"abut": True,
"direction": "left_to_right",
"instances": ["invn", "invp"]
}]
example = build_example(name, netlist, constraints)
run_example(example)
def test_place_cmp_2():
""" comparator with modified hierarchy """
name = f'ckt_{get_test_id()}'
netlist = textwrap.dedent(f"""\
.subckt dptail clk vin vip vin_d vip_d vssx
mn0 vcom clk vssx vssx n w=2.88e-6 m=1 nf=16
mn1 vin_d vin vcom vssx n w=360e-9 m=18 nf=2
mn2 vip_d vip vcom vssx n w=360e-9 m=18 nf=2
.ends dptail
.subckt {name} clk vccx vin vip von vop vssx
x0 clk vin vip vin_d vip_d vssx dptail
mn3 vin_o vip_o vin_d vssx n w=360e-9 m=8 nf=2
mn4 vip_o vin_o vip_d vssx n w=360e-9 m=8 nf=2
mp5 vin_o vip_o vccx vccx p w=360e-9 m=6 nf=2
mp6 vip_o vin_o vccx vccx p w=360e-9 m=6 nf=2
mp7 vin_d clk vccx vccx p w=360e-9 m=1 nf=2
mp8 vip_d clk vccx vccx p w=360e-9 m=1 nf=2
mp9 vin_o clk vccx vccx p w=360e-9 m=2 nf=2
mp10 vip_o clk vccx vccx p w=360e-9 m=2 nf=2
mn11 von vin_o vssx vssx n w=360e-9 m=1 nf=2
mn12 vop vip_o vssx vssx n w=360e-9 m=1 nf=2
mp13 von vin_o vccx vccx p w=360e-9 m=1 nf=2
mp14 vop vip_o vccx vccx p w=360e-9 m=1 nf=2
.ends {name}
""")
setup = textwrap.dedent(f"""\
POWER = vccx
GND = vssx
DONT_CONST = {name}
""")
constraints = [{
"constraint": "GroupBlocks",
"instances": ["mn3", "mn4"],
"name": "ccn"
}, {
"constraint": "GroupBlocks",
"instances": ["mp5", "mp6"],
"name": "ccp"
}, {
"constraint": "GroupBlocks",
"instances": ["mn11", "mp13"],
"name": "invp"
}, {
"constraint": "GroupBlocks",
"instances": ["mn12", "mp14"],
"name": "invn"
}, {
"constraint": "SameTemplate",
"instances": ["mp7", "mp8"]
}, {
"constraint": "SameTemplate",
"instances": ["mp9", "mp10"]
}, {
"constraint": "SameTemplate",
"instances": ["invn", "invp"]
}, {
"constraint":
"SymmetricBlocks",
"direction":
"V",
"pairs": [["ccp"], ["ccn"], ["invn", "invp"], ["mp9", "mp10"],
["mp7", "mp8"]]
}, {
"constraint": "AlignInOrder",
"line": "bottom",
"instances": ["x0", "ccn"]
}, {
"constraint": "AspectRatio",
"subcircuit": name,
"ratio_low": 1,
"ratio_high": 2
}]
example = build_example(name, netlist, setup, constraints)
# TODO: Separate below to a separate PR to debug: Constraints for the subhierarchy not respected..
# setup = textwrap.dedent("""\
# GND = vssx
# DONT_CONST = dptail
# """)
# with open(example / 'dptail.setup', 'w') as fp:
# fp.write(setup)
# constraints = [
# {"constraint": "GroupBlocks", "instances": ["mn1", "mn2"], "name": "dp"},
# {"constraint": "SymmetricBlocks", "direction": "V", "pairs": [["mn0"], ["dp"]]},
# {"constraint": "Order", "direction": "top_to_bottom", "instances": ["mn0", "dp"]}
# ]
# with open(example / 'dptail.const.json', 'w') as fp:
# fp.write(json.dumps(constraints, indent=2))
ckt_dir, run_dir = run_example(example, cleanup=cleanup, area=4e10)
cn = f'{name.upper()}_0'
with (run_dir / '3_pnr' / 'Results' /
f'{cn}.placement_verilog.json').open('rt') as fp:
placement = json.load(fp)
assert standalone_overlap_checker(placement, cn)
nets = gen_netlist(placement, cn)
hpwl_new = calculate_HPWL_from_placement_verilog_d(placement, cn, nets)
x0, y0, x1, y1 = placement['modules'][0]['bbox']
area_new = (x1 - x0) * (y1 - y0)
print(f'hpwl_new={hpwl_new} area_new={area_new}')
if cleanup:
shutil.rmtree(run_dir)
shutil.rmtree(ckt_dir)
def test_place_cmp_1():
""" original comparator. Run this test with -v and -s"""
name = f'ckt_{get_test_id()}'
netlist = circuits.comparator(name)
setup = textwrap.dedent(f"""\
POWER = vccx
GND = vssx
DONT_CONST = {name}
""")
constraints = [{
"constraint": "GroupBlocks",
"instances": ["mn1", "mn2"],
"name": "dp"
}, {
"constraint": "GroupBlocks",
"instances": ["mn3", "mn4"],
"name": "ccn"
}, {
"constraint": "GroupBlocks",
"instances": ["mp5", "mp6"],
"name": "ccp"
}, {
"constraint": "GroupBlocks",
"instances": ["mn11", "mp13"],
"name": "invp"
}, {
"constraint": "GroupBlocks",
"instances": ["mn12", "mp14"],
"name": "invn"
}, {
"constraint": "SameTemplate",
"instances": ["mp7", "mp8"]
}, {
"constraint": "SameTemplate",
"instances": ["mp9", "mp10"]
}, {
"constraint": "SameTemplate",
"instances": ["invn", "invp"]
}, {
"constraint": "SymmetricBlocks",
"direction": "V",
"pairs": [["mn0"], ["dp"]]
}, {
"constraint":
"SymmetricBlocks",
"direction":
"V",
"pairs": [["ccp"], ["ccn"], ["invn", "invp"], ["mp9", "mp10"],
["mp7", "mp8"]]
}, {
"constraint": "Order",
"direction": "top_to_bottom",
"instances": ["mn0", "dp"]
}, {
"constraint": "AlignInOrder",
"line": "bottom",
"instances": ["dp", "ccn"]
}, {
"constraint": "MultiConnection",
"nets": ["vcom"],
"multiplier": 6
}, {
"constraint": "AspectRatio",
"subcircuit": name,
"ratio_low": 1,
"ratio_high": 2
}]
example = build_example(name, netlist, setup, constraints)
ckt_dir, run_dir = run_example(example,
cleanup=cleanup,
log_level='DEBUG',
additional_args=[
'-e', '4', '--flow_stop', '3_pnr:route',
'--router_mode', 'no_op'
])
print(f'run_dir: {run_dir}')
cn = f'{name.upper()}_0'
with (run_dir / '3_pnr' / 'Results' /
f'{cn}.placement_verilog.json').open('rt') as fp:
placement = json.load(fp)
assert standalone_overlap_checker(placement, cn)
nets = gen_netlist(placement, cn)
hpwl_new = calculate_HPWL_from_placement_verilog_d(placement, cn, nets)
x0, y0, x1, y1 = placement['modules'][0]['bbox']
area_new = (x1 - x0) * (y1 - y0)
print(f'hpwl_new={hpwl_new} area_new={area_new}')
with (run_dir / '..' / f'_{cn}.placement_verilog.json').open('rt') as fp:
placement = json.load(fp)
assert standalone_overlap_checker(placement, cn)
nets = gen_netlist(placement, cn)
hpwl_best = calculate_HPWL_from_placement_verilog_d(
placement, cn, nets)
x0, y0, x1, y1 = placement['modules'][0]['bbox']
area_best = (x1 - x0) * (y1 - y0)
print(f'hpwl_best={hpwl_best} area_best={area_best}')
hpwl_pct = round(100 * ((hpwl_new / hpwl_best) - 1))
area_pct = round(100 * ((area_new / area_best) - 1))
print(
f'Generated layout is {hpwl_pct}% worse in HPWL and {area_pct}% worse in AREA'
)
if cleanup:
shutil.rmtree(run_dir)
shutil.rmtree(ckt_dir)
def test_place_cmp_seed(seed):
""" original comparator. Run this test with -v and -s"""
name = f'ckt_{get_test_id()}'
netlist = circuits.comparator(name)
setup = textwrap.dedent(f"""\
POWER = vccx
GND = vssx
DONT_CONST = {name}
""")
constraints = [{
"constraint": "GroupBlocks",
"instances": ["mn1", "mn2"],
"name": "dp"
}, {
"constraint": "GroupBlocks",
"instances": ["mn3", "mn4"],
"name": "ccn"
}, {
"constraint": "GroupBlocks",
"instances": ["mp5", "mp6"],
"name": "ccp"
}, {
"constraint": "GroupBlocks",
"instances": ["mn11", "mp13"],
"name": "invp"
}, {
"constraint": "GroupBlocks",
"instances": ["mn12", "mp14"],
"name": "invn"
}, {
"constraint": "SameTemplate",
"instances": ["mp7", "mp8"]
}, {
"constraint": "SameTemplate",
"instances": ["mp9", "mp10"]
}, {
"constraint": "SameTemplate",
"instances": ["invn", "invp"]
}, {
"constraint": "SymmetricBlocks",
"direction": "V",
"pairs": [["mn0"], ["dp"]]
}, {
"constraint":
"SymmetricBlocks",
"direction":
"V",
"pairs": [["ccp"], ["ccn"], ["invn", "invp"], ["mp9", "mp10"],
["mp7", "mp8"]]
}, {
"constraint": "Order",
"direction": "top_to_bottom",
"instances": ["mn0", "dp"]
}, {
"constraint": "AlignInOrder",
"line": "bottom",
"instances": ["dp", "ccn"]
}, {
"constraint": "MultiConnection",
"nets": ["vcom"],
"multiplier": 6
}, {
"constraint": "AspectRatio",
"subcircuit": name,
"ratio_low": 0.01,
"ratio_high": 100
}]
example = build_example(name, netlist, setup, constraints)
ckt_dir, run_dir = run_example(example,
cleanup=cleanup,
log_level='DEBUG',
additional_args=[
'-e', '1', '--flow_stop', '3_pnr:route',
'--router_mode', 'no_op', '--seed',
str(seed)
])
cn = f'{name.upper()}_0'
with (run_dir / '3_pnr' / 'Results' /
f'{cn}.placement_verilog.json').open('rt') as fp:
placement = json.load(fp)
assert standalone_overlap_checker(placement, cn)
nets = gen_netlist(placement, cn)
hpwl_new = calculate_HPWL_from_placement_verilog_d(placement, cn, nets)
x0, y0, x1, y1 = placement['modules'][0]['bbox']
area_new = (x1 - x0) * (y1 - y0)
cn = 'CKT_PLACE_CMP_1_0'
with (run_dir / '..' / f'_{cn}.placement_verilog.json').open('rt') as fp:
placement = json.load(fp)
assert standalone_overlap_checker(placement, cn)
nets = gen_netlist(placement, cn)
hpwl_best = calculate_HPWL_from_placement_verilog_d(
placement, cn, nets)
x0, y0, x1, y1 = placement['modules'][0]['bbox']
area_best = (x1 - x0) * (y1 - y0)
hpwl_pct = round(100 * ((hpwl_new / hpwl_best) - 1))
area_pct = round(100 * ((area_new / area_best) - 1))
pct = (area_new * hpwl_new) / (area_best * hpwl_best)
pct = round(100 * (pct - 1))
print(
f'seed={seed} hpwl={hpwl_new} area={area_new} area*hpwl={area_new*hpwl_new} This placement is {hpwl_pct}% in hpwl, {area_pct}% in area, {pct}% in area*hpwl worse than the best known solution'
)
plot_sa_cost(name.upper())
plot_sa_seq(name.upper())
import sys
sys.path.append("../docs/guide/writing-filters")
sys.path.append("../docs/guide/writing-filters/ex3")
from StringIO import StringIO
import json
import nose
import utils
script_output = {}
utils.run_example("ex3", script_output)
loader = nose.loader.TestLoader()
test = loader.loadTestsFromDir("../docs/guide/writing-filters/ex3")
config = nose.config.Config()
s = StringIO()
config.stream = s
result = nose.core.run(suite = test, config=config)
script_output['test-out'] = s.getvalue()
script_output['test-results'] = result
with open("dexy--script-output-ex3.json", "w") as f:
json.dump(script_output, f, sort_keys=True, indent=4)
