def create_reg(name, nbits=32, num_fields=1):
reg = UVMReg(name, nbits)
lsb_pos = 0
nbits_per_fields = int(nbits / num_fields)
msb_pos = nbits_per_fields - 1
for i in range(num_fields):
field = UVMRegField.type_id.create(name, None, reg.get_full_name())
field.configure(reg, msb_pos, lsb_pos, "RW", 0, 0x00, 1, 1, 1)
lsb_pos += nbits_per_fields
msb_pos += nbits_per_fields
return reg
def test_add_reg(self):
rb = UVMRegBlock("rb_blk")
rb.create_map("", 0, 1, UVM_BIG_ENDIAN)
reg1 = UVMReg("xx", 32, rb.get_full_name())
reg1.configure(rb, None, "acp")
# reg1.build()
rb.default_map.add_reg(reg1, 0x0000, "RW")
print("len is now " + str(len(rb.regs)))
rr = rb.get_reg_by_name('xx')
self.assertEqual(rr.get_name(), 'xx')
r_none = rb.get_reg_by_name('y_reg')
self.assertEqual(r_none, None)
def test_add_field(self):
UVMRegField.define_access('RW')
reg = UVMReg('my_reg', 32, False)
f1 = UVMRegField('my_field_1')
f1.configure(reg,
16,
0,
'RW',
volatile=False,
reset=0,
has_reset=True,
is_rand=False,
individually_accessible=True)
arr = []
reg.get_fields(arr)
print(str(reg.m_fields))
self.assertEqual(len(arr), 1)
def create_reg(self, name='reg', nbits=32):
reg = UVMReg(name, nbits, False)
for i in range(0, nbits):
f1 = UVMRegField('my_field_' + str(i))
f1.configure(reg,
1,
i,
'RW',
volatile=False,
reset=i % 2,
has_reset=True,
is_rand=False,
individually_accessible=True)
return reg
def test_XupdateX(self):
reg = UVMReg('update_reg', 16, False)
field = self.create_field('field2', reg)
field.set_access("RW")
field.set(0x2345)
value = field.XupdateX()
self.assertEqual(value, 0x2345)
# Clear on write
field.set_access("WC")
field.set(0x5555)
value = field.XupdateX()
self.assertEqual(value, 0x0)
# Set on Write
field.set_access("WS")
field.set(0x5555)
value = field.XupdateX()
self.assertEqual(value, 0xFFFF)
def test_set_get(self):
for mode in NO_RAND_SET:
reg = UVMReg('my_reg', 16, False)
field = self.create_field('field_' + mode, reg, acc=mode)
field.reset()
access = field.get_access()
field.set(0x1234)
val = field.get()
msg = 'Access ' + access + ' OK'
predict_msg = 'Predict for ' + access + ' OK'
if access in ['RW', 'WRS', 'WRC']:
self.assertEqual(val, 0x1234, msg)
self.assertTrue(field.predict(0x1234, -1, UVM_PREDICT_WRITE), predict_msg)
elif access in ['RO', 'RC', 'RS']:
self.assertEqual(val, field.get_reset(), msg)
self.assertTrue(field.predict(field.get_reset(), -1, UVM_PREDICT_READ), predict_msg)
else:
self.assertTrue(field.predict(0x12), predict_msg)
val = field.get()
self.assertEqual(val, 0x12, 'Val OK after predict with ' + access)
def test_string_conv(self):
reg = UVMReg('r0_test', 16, False)
field = self.create_field('f1', reg)
ss = field.convert2string()
self.assertRegex(ss, r'\[15:0\]={}'.format(16))
def test_configure(self):
reg = UVMReg('my_reg', 16, False)
field = self.create_field('f1', reg)
self.assertEqual(field.get_reset(), 0xABCD)