def prologue(self): # hush debug messages to database self.mdb.filter_fn = lambda cb_id, level, filename: level < message.INFORMATION duv.mem[0] = 69 duv.mem[69] = 666 totin = 0 message.note('begin initialize') for r in duv.mem: r.set_value(verilog.vpiInt(r.index)) totin += r.index message.note('end initialize at %(idx)d, sum is %(tot)d', idx=r.index, tot=totin) message.note('begin read') totout = reduce(lambda a, b: int(a) + int(b), duv.mem) message.note('end read, sum is %(tot)d', tot=totout) duv.mem[666] = 69 message.note('size of [%(lhs)d:%(rhs)d] is %(size)d', lhs=duv.mem.lhs, rhs=duv.mem.rhs, size=duv.mem.size) message.note('size of mem[0] [%(lhs)d:%(rhs)d] is %(size)d', lhs=duv.mem[0].lhs, rhs=duv.mem[0].rhs, size=duv.mem[0].size)
def prologue(self) : # hush debug messages to database self.mdb.filter_fn = lambda cb_id, level, filename : level < message.INFORMATION duv.mem[0] = 69 duv.mem[69] = 666 totin = 0 message.note('begin initialize') for r in duv.mem : r.set_value(verilog.vpiInt(r.index)) totin += r.index message.note('end initialize at %(idx)d, sum is %(tot)d', idx=r.index, tot=totin) message.note('begin read') totout = reduce(lambda a,b : int(a)+int(b), duv.mem) message.note('end read, sum is %(tot)d', tot=totout) duv.mem[666] = 69 message.note('size of [%(lhs)d:%(rhs)d] is %(size)d', lhs=duv.mem.lhs, rhs=duv.mem.rhs, size=duv.mem.size) message.note('size of mem[0] [%(lhs)d:%(rhs)d] is %(size)d', lhs=duv.mem[0].lhs, rhs=duv.mem[0].rhs, size=duv.mem[0].size)
# Copyright (c) 2012, 2013 Rich Porter - see LICENSE for further details import atexit import message import test import verilog def root() : return 'example' simctrl = verilog.scope(root() + '.simctrl_0_u') if test.plusargs().timeout : simctrl.direct.sim_ctrl_timeout_i = verilog.vpiInt(test.plusargs().timeout) # use verilog vpi cbEndOfSimulation callback class cbEndOfSimulation(verilog.callback) : def __init__(self) : verilog.callback.__init__(self, name='PLI end of simulation callback', reason=verilog.callback.cbEndOfSimulation, func=self.execute) def execute(self) : message.note('vpi cbEndOfSimulation') end = cbEndOfSimulation() # show when python interpreter is closed down def finalize() : message.note('finalize') atexit.register(finalize)