def __init__(self):
self.chksz = vsc.rand_uint8_t()
self.totsz = vsc.rand_uint16_t()
self.inc_src = vsc.rand_bit_t(i=1)
self.inc_dst = vsc.rand_bit_t(i=1)
self.src_addr = 0
self.dst_addr = 0
def __init__(self):
super().__init__()
self.a = vsc.rand_bit_t(8)
self.b = vsc.rand_bit_t(8)
self.c = vsc.rand_bit_t(8)
self.d = vsc.rand_bit_t(8)
def __init__(self):
super().__init__()
self.a = vsc.rand_bit_t(8)
self.b = vsc.rand_bit_t(8)
self.l = vsc.list_t(vsc.uint8_t())
for i in range(4):
self.l.append(i)
def __init__(self):
self.comment = ""
self.exception = vsc.rand_enum_t(illegal_instr_type_e)
self.reserved_c = vsc.rand_enum_t(reserved_c_instr_e)
self.instr_bin = vsc.rand_bit_t(32)
self.opcode = vsc.rand_bit_t(7)
self.compressed = vsc.rand_bit_t(1)
self.func3 = vsc.rand_bit_t(3)
self.func7 = vsc.rand_bit_t(7)
self.has_func3 = vsc.rand_bit_t(1)
self.has_func7 = vsc.rand_bit_t(1)
self.c_op = vsc.rand_bit_t(2)
self.c_msb = vsc.rand_bit_t(3)
self.csrs = []
# Default legal self.opcode for RV32I instructions
self.legal_opcode = vsc.list_t(vsc.bit_t(7))
self.legal_opcode = [3, 15, 19, 23, 35, 55, 99, 51, 103, 115, 111]
# Default legal self.opcode for RV32C instructions
self.legal_c00_opcode = vsc.list_t(vsc.bit_t(3))
self.legal_c00_opcode = [0, 2, 6]
self.legal_c10_opcode = vsc.list_t(vsc.bit_t(3))
self.legal_c10_opcode = [0, 2, 4, 6]
self.xlen = vsc.uint8_t(0)
self.xlen = rcs.XLEN
self.temp_1 = vsc.bit_t(6)
def __init__(self):
super().__init__()
self.a = vsc.rand_bit_t(4)
self.b = vsc.rand_attr(my_sub())
self.c = vsc.rand_attr(my_sub())
self.d = vsc.rand_attr(my_sub())
self.e = vsc.rand_attr(my_sub())
def __init__(self):
super().__init__()
self.num_of_avail_regs = 10
self.num_of_instr = vsc.rand_uint8_t()
self.init_val = vsc.rand_list_t(vsc.rand_bit_t(rcs.XLEN - 1), sz=10)
self.init_val_type = vsc.rand_list_t(vsc.enum_t(int_numeric_e), sz=10)
self.init_instr = []
def __init__(self):
self.bit_width = 0
self.reset_val = vsc.bit_t(rcs.XLEN)
self.val = vsc.rand_bit_t(rcs.XLEN)
self.access_type = vsc.enum_t(reg_field_access_t)
self.hard_wired = vsc.bit_t(1)
self.name = ""
def test_sum_overflow(self):
list = vsc.rand_list_t(vsc.rand_bit_t(32), 8)
for i in range(10):
with vsc.randomize_with(list):
list.sum <= 4096
self.assertLessEqual(list.sum, 4096)
def __init__(self):
self.L = 8
# random, unsigned (bit), and L-bits wide
self.rand_bit_1 = vsc.rand_bit_t(self.L)
self.rand_bit_1_hist = [0 for i in range(2**self.L)]
self.rand_bit_2 = vsc.rand_bit_t(self.L)
self.rand_bit_2_hist = [0 for i in range(2**self.L)]
self.rand_bit_3 = vsc.rand_bit_t(self.L)
self.rand_bit_3_hist = [0 for i in range(2**self.L)]
self.rand_bit_4 = vsc.rand_bit_t(self.L)
self.rand_bit_4_hist = [0 for i in range(2**self.L)]
def __init__(self):
# Instruction attributes
self.group = vsc.enum_t(riscv_instr_group_t)
self.format = vsc.enum_t(riscv_instr_format_t)
self.category = vsc.enum_t(riscv_instr_category_t)
self.instr_name = vsc.enum_t(riscv_instr_name_t)
self.imm_type = vsc.enum_t(imm_t)
self.imm_len = vsc.bit_t(5)
# Operands
self.csr = vsc.rand_bit_t(12)
self.rs2 = vsc.rand_enum_t(riscv_reg_t)
self.rs1 = vsc.rand_enum_t(riscv_reg_t)
self.rd = vsc.rand_enum_t(riscv_reg_t)
self.imm = vsc.rand_bit_t(32)
# Helper Fields
self.imm_mask = vsc.uint32_t(0xffffffff)
self.is_branch_target = None
self.has_label = 1
self.atomic = 0
self.branch_assigned = None
self.process_load_store = 1
self.is_compressed = None
self.is_illegal_instr = None
self.is_hint_instr = None
self.is_floating_point = None
self.imm_str = None
self.comment = ""
self.label = ""
self.is_local_numeric_label = None
self.idx = -1
self.has_rs1 = vsc.bit_t(1)
self.has_rs2 = vsc.bit_t(1)
self.has_rd = vsc.bit_t(1)
self.has_imm = vsc.bit_t(1)
self.has_rs1 = 1
self.has_rs2 = 1
self.has_rd = 1
self.has_imm = 1
self.shift_t = vsc.uint32_t(0xffffffff)
self.mask = 32
self.XLEN = vsc.uint32_t(
32) # XLEN is used in constraint throughout the generator.
# Hence, XLEN should be of PyVSC type in order to use it in a constraint block
self.XLEN = rcs.XLEN
def __init__(self):
self.loop_cnt_reg = vsc.randsz_list_t(vsc.enum_t(my_e))
self.loop_limit_reg = vsc.randsz_list_t(vsc.enum_t(my_e))
self.loop_init_val = vsc.randsz_list_t(vsc.uint32_t())
self.loop_step_val = vsc.randsz_list_t(vsc.uint32_t())
self.loop_limit_val = vsc.randsz_list_t(vsc.uint32_t())
self.num_of_nested_loop = vsc.rand_bit_t(3)
self.num_of_instr_in_loop = vsc.rand_uint32_t()
self.branch_type = vsc.randsz_list_t(vsc.enum_t(my_e))
def __init__(self):
self.a = vsc.rand_list_t(vsc.attr(Field('a', 10)))
for i in range(5):
self.a.append(vsc.attr(Field('a', 10)))
self.b = vsc.rand_list_t(vsc.attr(Field('b', 10)))
for i in range(5):
self.b.append(vsc.attr(Field('b', 10)))
self.test_bit = vsc.rand_bit_t(8)
def __init__(self):
self.instr_names = []
self.instr_group = defaultdict(list)
self.instr_category = defaultdict(list)
self.basic_instr = []
self.instr_template = {}
self.exclude_reg = []
self.include_reg = []
self.group = None
self.format = None
self.category = None
self.instr_name = None
self.imm_type = None
self.imm_len = 0
self.csr = vsc.rand_bit_t(12)
self.rs2 = vsc.rand_enum_t(riscv_reg_t)
self.rs1 = vsc.rand_enum_t(riscv_reg_t)
self.rd = vsc.rand_enum_t(riscv_reg_t)
self.imm = vsc.rand_bit_t(32)
self.imm_mask = vsc.uint32_t(0xffffffff)
self.is_branch_target = None
self.has_label = 1
self.atomic = 0
self.branch_assigned = None
self.process_load_store = 1
self.is_compressed = None
self.is_illegal_instr = None
self.is_hint_instr = None
self.is_floating_point = None
self.imm_str = None
self.comment = ""
self.label = ""
self.is_local_numeric_label = None
self.idx = -1
self.has_rs1 = 1
self.has_rs2 = 1
self.has_rd = 1
self.has_imm = 1
self.shift_t = vsc.uint32_t(0xffffffff)
def __init__(self):
super().__init__()
self.stack_len = 0
self.num_of_reg_to_save = 0
self.num_of_redundant_instr = 0
self.push_stack_instr = []
self.saved_regs = []
self.branch_instr = vsc.attr(riscv_instr())
self.enable_branch = vsc.rand_bit_t(1)
self.push_start_label = ''
def __init__(self):
super().__init__()
self.num_load_store = vsc.rand_uint32_t()
self.num_mixed_instr = vsc.rand_uint32_t()
self.base = vsc.rand_int32_t()
self.offset = []
self.addr = []
self.load_store_instr = []
self.data_page_id = vsc.rand_uint32_t()
self.rs1_reg = vsc.rand_enum_t(riscv_reg_t)
self.locality = vsc.rand_enum_t(locality_e)
self.max_load_store_offset = vsc.rand_int32_t()
self.use_sp_as_rs1 = vsc.rand_bit_t()
def __init__(self):
super().__init__()
self.loop_cnt_reg = vsc.randsz_list_t(vsc.enum_t(riscv_reg_t))
self.loop_limit_reg = vsc.randsz_list_t(vsc.enum_t(riscv_reg_t))
self.loop_init_val = vsc.randsz_list_t(vsc.int32_t())
self.loop_step_val = vsc.randsz_list_t(vsc.int32_t())
self.loop_limit_val = vsc.randsz_list_t(vsc.int32_t())
self.num_of_nested_loop = vsc.rand_bit_t(3)
self.num_of_instr_in_loop = vsc.rand_int32_t(0)
self.branch_type = vsc.randsz_list_t(vsc.enum_t(riscv_instr_name_t))
self.loop_init_instr = []
self.loop_update_instr = []
self.loop_branch_instr = []
self.loop_branch_target_instr = []
# Aggregated loop instruction stream
self.loop_instr = []
def init_gpr(self):
reg_val = vsc.rand_bit_t(pkg_ins.DATA_WIDTH)
for i in range(rcs.NUM_GPR):
if i in [cfg.sp.value, cfg.tp.value]:
continue
try:
with vsc.randomize_with(reg_val):
vsc.dist(reg_val, [vsc.weight(0, 1), vsc.weight(0x80000000, 1),
vsc.weight(vsc.rng(0x1, 0xf), 1),
vsc.weight(vsc.rng(0x10, 0xefffffff), 1),
vsc.weight(vsc.rng(0xf0000000, 0xffffffff), 1)])
except Exception:
logging.critical("Cannot Randomize reg_val")
sys.exit(1)
init_string = "{}li x{}, {}".format(pkg_ins.indent, i, hex(reg_val.get_val()))
self.instr_stream.append(init_string)
def __init__(self):
self.key = vsc.rand_bit_t(8)
def __init__(self):
self.a = vsc.rand_bit_t()
self.b = vsc.rand_uint8_t()
def __init__(self):
super().__init__()
self.v1_1 = vsc.rand_bit_t(4)
self.v1_2 = vsc.rand_bit_t(4)
self.v1_3 = vsc.rand_bit_t(4)
self.v1_4 = vsc.rand_bit_t(4)
self.v1_5 = vsc.rand_bit_t(4)
self.v1_6 = vsc.rand_bit_t(4)
self.v1_7 = vsc.rand_bit_t(4)
self.v1_8 = vsc.rand_bit_t(4)
self.v1_9 = vsc.rand_bit_t(4)
self.v1_10 = vsc.rand_bit_t(4)
self.v1_11 = vsc.rand_bit_t(4)
self.v1_12 = vsc.rand_bit_t(4)
self.v1_13 = vsc.rand_bit_t(4)
self.v1_14 = vsc.rand_bit_t(4)
self.v1_15 = vsc.rand_bit_t(4)
self.v1_16 = vsc.rand_bit_t(4)
self.v2_1 = vsc.rand_bit_t(4)
self.v2_2 = vsc.rand_bit_t(4)
self.v2_3 = vsc.rand_bit_t(4)
self.v2_4 = vsc.rand_bit_t(4)
self.v2_5 = vsc.rand_bit_t(4)
self.v2_6 = vsc.rand_bit_t(4)
self.v2_7 = vsc.rand_bit_t(4)
self.v2_8 = vsc.rand_bit_t(4)
self.v2_9 = vsc.rand_bit_t(4)
self.v2_10 = vsc.rand_bit_t(4)
self.v2_11 = vsc.rand_bit_t(4)
self.v2_12 = vsc.rand_bit_t(4)
self.v2_13 = vsc.rand_bit_t(4)
self.v2_14 = vsc.rand_bit_t(4)
self.v2_15 = vsc.rand_bit_t(4)
self.v2_16 = vsc.rand_bit_t(4)
self.v3_1 = vsc.rand_bit_t(4)
self.v3_2 = vsc.rand_bit_t(4)
self.v3_3 = vsc.rand_bit_t(4)
self.v3_4 = vsc.rand_bit_t(4)
self.v3_5 = vsc.rand_bit_t(4)
self.v3_6 = vsc.rand_bit_t(4)
self.v3_7 = vsc.rand_bit_t(4)
self.v3_8 = vsc.rand_bit_t(4)
self.v3_9 = vsc.rand_bit_t(4)
self.v3_10 = vsc.rand_bit_t(4)
self.v3_11 = vsc.rand_bit_t(4)
self.v3_12 = vsc.rand_bit_t(4)
self.v3_13 = vsc.rand_bit_t(4)
self.v3_14 = vsc.rand_bit_t(4)
self.v3_15 = vsc.rand_bit_t(4)
self.v3_16 = vsc.rand_bit_t(4)
self.v4_1 = vsc.rand_bit_t(4)
self.v4_2 = vsc.rand_bit_t(4)
self.v4_3 = vsc.rand_bit_t(4)
self.v4_4 = vsc.rand_bit_t(4)
self.v4_5 = vsc.rand_bit_t(4)
self.v4_6 = vsc.rand_bit_t(4)
self.v4_7 = vsc.rand_bit_t(4)
self.v4_8 = vsc.rand_bit_t(4)
self.v4_9 = vsc.rand_bit_t(4)
self.v4_10 = vsc.rand_bit_t(4)
self.v4_11 = vsc.rand_bit_t(4)
self.v4_12 = vsc.rand_bit_t(4)
self.v4_13 = vsc.rand_bit_t(4)
self.v4_14 = vsc.rand_bit_t(4)
self.v4_15 = vsc.rand_bit_t(4)
self.v4_16 = vsc.rand_bit_t(4)
def __init__(self):
# TODO Support for command line argument
self.main_program_instr_cnt = 100 # count of main_prog
self.sub_program_instr_cnt = [] # count of sub_prog
self.debug_program_instr_cnt = 0 # count of debug_rom
self.debug_sub_program_instr_cnt = [] # count of debug sub_progrms
self.max_directed_instr_stream_seq = 20
self.data_page_pattern = vsc.rand_enum_t(data_pattern_t)
self.argv = self.parse_args()
self.args_dict = vars(self.argv)
global rcs
rcs = import_module("pygen_src.target." + self.argv.target + ".riscv_core_setting")
self.m_mode_exception_delegation = {}
self.s_mode_exception_delegation = {}
self.m_mode_interrupt_delegation = {}
self.s_mode_interrupt_delegation = {}
# init_privileged_mode default to MACHINE_MODE
self.init_privileged_mode = privileged_mode_t.MACHINE_MODE
self.mstatus = vsc.rand_bit_t(rcs.XLEN - 1)
self.mie = vsc.rand_bit_t(rcs.XLEN - 1)
self.sstatus = vsc.rand_bit_t(rcs.XLEN - 1)
self.sie = vsc.rand_bit_t(rcs.XLEN - 1)
self.ustatus = vsc.rand_bit_t(rcs.XLEN - 1)
self.uie = vsc.rand_bit_t(rcs.XLEN - 1)
self.mstatus_mprv = vsc.rand_bit_t(1)
self.mstatus_mxr = vsc.rand_bit_t(1)
self.mstatus_sum = vsc.rand_bit_t(1)
self.mstatus_tvm = vsc.rand_bit_t(1)
self.mstatus_fs = vsc.rand_bit_t(2)
self.mstatus_vs = vsc.rand_bit_t(2)
self.mtvec_mode = vsc.rand_enum_t(mtvec_mode_t)
self.tvec_alignment = vsc.rand_uint8_t(self.argv.tvec_alignment)
self.fcsr_rm = vsc.rand_enum_t(f_rounding_mode_t)
self.enable_sfence = vsc.rand_bit_t(1)
self.gpr = []
# Helper fields for gpr
self.gpr0 = vsc.rand_enum_t(riscv_reg_t)
self.gpr1 = vsc.rand_enum_t(riscv_reg_t)
self.gpr2 = vsc.rand_enum_t(riscv_reg_t)
self.gpr3 = vsc.rand_enum_t(riscv_reg_t)
self.scratch_reg = vsc.rand_enum_t(riscv_reg_t)
self.pmp_reg = vsc.rand_enum_t(riscv_reg_t)
self.sp = vsc.rand_enum_t(riscv_reg_t)
self.tp = vsc.rand_enum_t(riscv_reg_t)
self.ra = vsc.rand_enum_t(riscv_reg_t)
self.check_misa_init_val = 0
self.check_xstatus = 1
self.virtual_addr_translation_on = 0
# Commenting out for now
# vector_cfg = riscv_vector_cfg # TODO
# pmp_cfg = riscv_pmp_cfg # TODO
self.mem_region = {
0: {'name': "region_0", 'size_in_bytes': 4096, 'xwr': 8},
1: {'name': "region_1", 'size_in_bytes': 4096 * 16, 'xwr': 8}
}
self.amo_region = {
0: {'name': "amo_0", 'size_in_bytes': 64, 'xwr': 8}
}
self.stack_len = 5000
self.s_mem_region = {
0: {'name': "s_region_0", 'size_in_bytes': 4096, 'xwr': 8},
1: {'name': "s_region_1", 'size_in_bytes': 4096, 'xwr': 8}
}
self.kernel_stack_len = 4000
self.kernel_program_instr_cnt = 400
# list of main implemented CSRs
self.invalid_priv_mode_csrs = []
self.num_of_sub_program = self.argv.num_of_sub_program
self.instr_cnt = self.argv.instr_cnt
self.num_of_tests = self.argv.num_of_tests
self.no_data_page = self.argv.no_data_page
self.no_branch_jump = self.argv.no_branch_jump
self.no_load_store = self.argv.no_load_store
self.no_csr_instr = self.argv.no_csr_instr
self.no_ebreak = self.argv.no_ebreak
self.no_dret = self.argv.no_dret
self.no_fence = self.argv.no_fence
self.no_wfi = self.argv.no_wfi
self.enable_unaligned_load_store = self.argv.enable_unaligned_load_store
self.illegal_instr_ratio = self.argv.illegal_instr_ratio
self.hint_instr_ratio = self.argv.hint_instr_ratio
self.num_of_harts = self.argv.num_of_harts
self.fix_sp = self.argv.fix_sp
self.use_push_data_section = self.argv.use_push_data_section
self.boot_mode_opts = self.argv.boot_mode
# self.isa = self.argv.isa
if self.boot_mode_opts:
logging.info("Got boot mode option - %0s", self.boot_mode_opts)
if self.boot_mode_opts == "m":
self.init_privileged_mode = privileged_mode_t.MACHINE_MODE
elif self.boot_mode_opts == "s":
self.init_privileged_mode = privileged_mode_t.SUPERVISOR_MODE
elif self.boot_mode_opts == "u":
self.init_privileged_mode = privileged_mode_t.USER_MODE
else:
logging.error("Illegal boot mode option - %0s", self.boot_mode_opts)
self.enable_page_table_exception = self.argv.enable_page_table_exception
self.no_directed_instr = self.argv.no_directed_instr
self.asm_test_suffix = self.argv.asm_test_suffix
self.enable_interrupt = self.argv.enable_interrupt
self.enable_nested_interrupt = self.argv.enable_nested_interrupt
self.enable_timer_irq = self.argv.enable_timer_irq
self.bare_program_mode = self.argv.bare_program_mode
self.enable_illegal_csr_instruction = self.argv.enable_illegal_csr_instruction
self.enable_access_invalid_csr_level = self.argv.enable_access_invalid_csr_level
self.enable_misaligned_instr = self.argv.enable_misaligned_instr
self.enable_dummy_csr_write = self.argv.enable_dummy_csr_write
self.randomize_csr = self.argv.randomize_csr
self.allow_sfence_exception = self.argv.allow_sfence_exception
self.no_delegation = self.argv.no_delegation
self.force_m_delegation = self.argv.force_m_delegation
self.force_s_delegation = self.argv.force_s_delegation
self.support_supervisor_mode = 0
self.disable_compressed_instr = self.argv.disable_compressed_instr
self.require_signature_addr = self.argv.require_signature_addr
if self.require_signature_addr:
self.signature_addr = int(self.argv.signature_addr, 16)
else:
self.signature_addr = 0xdeadbeef
self.gen_debug_section = self.argv.gen_debug_section
self.enable_ebreak_in_debug_rom = self.argv.enable_ebreak_in_debug_rom
self.set_dcsr_ebreak = self.argv.set_dcsr_ebreak
self.num_debug_sub_program = self.argv.num_debug_sub_program
self.enable_debug_single_step = self.argv.enable_debug_single_step
self.single_step_iterations = 0
self.set_mstatus_tw = self.argv.set_mstatus_tw
self.set_mstatus_mprv = self.argv.set_mstatus_mprv
self.min_stack_len_per_program = 10 * (rcs.XLEN / 8)
self.max_stack_len_per_program = 16 * (rcs.XLEN / 8)
self.max_branch_step = 20
self.reserved_regs = vsc.list_t(vsc.enum_t(riscv_reg_t))
self.enable_floating_point = self.argv.enable_floating_point
self.enable_vector_extension = self.argv.enable_vector_extension
self.enable_b_extension = self.argv.enable_b_extension
self.enable_bitmanip_groups = self.argv.enable_bitmanip_groups
self.dist_control_mode = 0
self.category_dist = {}
self.march_isa = self.argv.march_isa
if len(self.march_isa) != 0:
rcs.supported_isa = self.march_isa
if "RV32C" not in rcs.supported_isa:
self.disable_compressed_instr = 1
def __init__(self):
super().__init__()
self.a = vsc.rand_bit_t(16)
self.b = vsc.rand_bit_t(8)
self.c = vsc.rand_bit_t(2)
self.d = vsc.rand_bit_t(1)
self.e = vsc.rand_bit_t(16)
self.f = vsc.rand_bit_t(8)
self.g = vsc.rand_bit_t(2)
self.h = vsc.rand_bit_t(1)
self.i = vsc.rand_bit_t(16)
self.j = vsc.rand_bit_t(8)
self.k = vsc.rand_bit_t(2)
self.l = vsc.rand_bit_t(1)
def __init__(self):
self.a = vsc.rand_bit_t(8)
self.b = vsc.rand_bit_t(8)
def __init__(self):
self.value = vsc.rand_bit_t(32)
self.randselect = self.get_val()
def __init__(self):
super().__init__()
self.a = vsc.rand_bit_t(16)
self.b = vsc.rand_bit_t(16)
def __init__(self):
self.type = vsc.rand_bit_t(1)
self.disp = vsc.rand_bit_t(22)
def __init__(self):
self.value = vsc.rand_bit_t(4)
self.a = vsc.rand_bit_t(1)
self.b = vsc.rand_bit_t(1)
def __init__(self):
super().__init__()
self.a = vsc.rand_bit_t(8)
self.b = vsc.rand_bit_t(8)
self.l = list(range(4))
def __init__(self):
super().__init__()
self.a = vsc.rand_bit_t(8)
self.b = vsc.rand_bit_t(8)
self.temp = vsc.list_t(vsc.bit_t(8))
self.temp = [1, 2, 3, 4, 5, 6, 7, 8, 9]
def __init__(self):
self.num = vsc.rand_bit_t(8)
self.level = vsc.rand_enum_t(level_t)
self.addr = []
self.offset = []
