def main():
print (sys.argv)
if len(sys.argv) > 3:
print( "Usage: verilog2vhdl.py [infile] [outfile]" )
return 1
# Check if in file can be opened
try:
fin = open( sys.argv[1], 'r' )
allLines = fin.readlines()
outputStr = ""
for line in allLines:
try:
out = vtools.parse_net( line )
# Parse lines from tuple
component = out[0]
instance = out[1]
asList = out[3]
outputStr += component + ": " + instance + "("
for element in asList:
outputStr += element[0] + "=>" + element[1] + ", "
outputStr = outputStr[:-2]
outputStr += ";\n"
catch ValueError:
print( "Error: input file is not a valid Verilog port map!")
return 4
except IOError:
print IOError
return 2
# Check if out file can be opened
try:
fout = open( sys.argv[2], 'r' )
fout.write( outputStr )
except IOError:
print IOError
return 3
# All of these should cause an exception:
"BAD(.A(n32),.B(n5),.C(n3),.D(n6),.Y(n25))": (),
".A(n32),.B(n5),.C(n3),.D(n6),.Y(n25)": (),
"TEST TEST((.A(n32),.B(n5),.C(n3),.D(n6),.Y(n25)))": (),
"TEST $TEST(.A(n32),.B(n5),.C(n3),.D(n6),.Y(n25))": (),
"TEST TEST(.A(n32),.B(n5),.C(n3),.D(n6),.Y(n25)))": (),
"TEST TEST(.A(n32),.B(n5),.C(n3),.D(n6),.Y(n25)": ()
}
for k in tests:
print('Testing: parse_net("{}")'.format(k))
ex = False
ok = True
try:
r = vtools.parse_net(k)
if r != tests[k]:
print("ERROR: parse_net() did not produce a correct result.")
print(" Got: {}".format(r))
print(" Expected: {}".format(tests[k]))
ok = False
except Exception as e:
ex = True
if ex and len(tests[k]) > 0:
print("ERROR: parse_net() incorrectly raised an exception!")
ok = False
elif not ex and len(tests[k]) <= 0:
print("Usage: verilog2vhd1.py [infile] [outfile]")
sys.exit(1)
if(len(sys.argv) == 2):
infile = sys.argv[1]
try:
fp = open(sys.argv[1],"r")
except :
raise IOError(2)
sys.exit(2)
if(len(sys.argv) == 3):
infile = sys.argv[1]
try:
fp = open(sys.argv[1],"r")
except :
raise IOError(2)
sys.exit(2)
outfile = sys.argv[2]
try:
fp = open(sys.argv[2],"w")
except :
raise IOError(3)
sys.exit(3)
if(len(sys.argv) == 2):
lines = fp.readlines()
#print(lines)
for line in lines:
print(line)
comp,instance,cmp = vtools.parse_net(str(line))
fi = open(sys.argv[1], 'r')
except IOError as e:
print('Error: %s\n' % (e,))
exit(2)
if len(sys.argv) == 3:
#print('will output to file if file opens')
try:
fo = open(sys.argv[2], 'w')
except IOError as e:
print('Error: %s\n' % (e,))
exit(3)
for lines in fi:
#print(lines)
lines = lines.lstrip()
try:
tup = parse_net(lines)
#print(tup)
#print(tup[2])
#print(len(tup[2]))
except ValueError as e:
print('Error: input file is not a valid Verilog port map!')
print('%s\n' % (e,))
exit(4)
instance_name = tup[1]
component_name = tup[0]
assignment_list = tup[2]
len_assignment = len(assignment_list)
line_str = instance_name + ":" + " " + component_name + " PORT MAP("
#print(instance_name + ":" + " " + component_name + " PORT MAP(")
for i in range(0, len_assignment):
port = tup[2][i][0]
#!/usr/local/bin/python3.4
__author__ = 'ee364e10'
import sys
import vtools
if __name__ == "__main__":
if len(sys.argv) <= 2:
print("Usage: verilog2vhdl.py [infile] [outfile]")
exit(1)
try:
fp = open(sys.argv[1] , "r")
except IOError as e:
print("Error: ",e)
exit(2)
filename = sys.argv[1]
# print("The filename sis : " , filename)
c = 0
try:
with open(filename,"r") as inputFile:
for line in inputFile:
try:
a = vtools.parse_net(line)
except ValueError as e:
print("Error: input File is not a valid Verilog port map!")
print(e)
exit(4)
except:
pass
fi = open(sys.argv[1], 'r')
except IOError as e:
print('Error: %s\n' % (e, ))
exit(2)
if len(sys.argv) == 3:
#print('will output to file if file opens')
try:
fo = open(sys.argv[2], 'w')
except IOError as e:
print('Error: %s\n' % (e, ))
exit(3)
for lines in fi:
#print(lines)
lines = lines.lstrip()
try:
tup = parse_net(lines)
#print(tup)
#print(tup[2])
#print(len(tup[2]))
except ValueError as e:
print('Error: input file is not a valid Verilog port map!')
print('%s\n' % (e, ))
exit(4)
instance_name = tup[1]
component_name = tup[0]
assignment_list = tup[2]
len_assignment = len(assignment_list)
line_str = instance_name + ":" + " " + component_name + " PORT MAP("
#print(instance_name + ":" + " " + component_name + " PORT MAP(")
for i in range(0, len_assignment):
port = tup[2][i][0]