def bench():
# Parameters
DATA_WIDTH = 32
ADDR_WIDTH = 32
SELECT_WIDTH = 4
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
wbm_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
wbm_dat_i = Signal(intbv(0)[DATA_WIDTH:])
wbm_we_i = Signal(bool(0))
wbm_sel_i = Signal(intbv(0)[SELECT_WIDTH:])
wbm_stb_i = Signal(bool(0))
wbm_cyc_i = Signal(bool(0))
wbs0_dat_i = Signal(intbv(0)[DATA_WIDTH:])
wbs0_ack_i = Signal(bool(0))
wbs0_err_i = Signal(bool(0))
wbs0_rty_i = Signal(bool(0))
wbs0_addr = Signal(intbv(0)[ADDR_WIDTH:])
wbs0_addr_msk = Signal(intbv(0)[ADDR_WIDTH:])
wbs1_dat_i = Signal(intbv(0)[DATA_WIDTH:])
wbs1_ack_i = Signal(bool(0))
wbs1_err_i = Signal(bool(0))
wbs1_rty_i = Signal(bool(0))
wbs1_addr = Signal(intbv(0)[ADDR_WIDTH:])
wbs1_addr_msk = Signal(intbv(0)[ADDR_WIDTH:])
# Outputs
wbm_dat_o = Signal(intbv(0)[DATA_WIDTH:])
wbm_ack_o = Signal(bool(0))
wbm_err_o = Signal(bool(0))
wbm_rty_o = Signal(bool(0))
wbs0_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
wbs0_dat_o = Signal(intbv(0)[DATA_WIDTH:])
wbs0_we_o = Signal(bool(0))
wbs0_sel_o = Signal(intbv(0)[SELECT_WIDTH:])
wbs0_stb_o = Signal(bool(0))
wbs0_cyc_o = Signal(bool(0))
wbs1_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
wbs1_dat_o = Signal(intbv(0)[DATA_WIDTH:])
wbs1_we_o = Signal(bool(0))
wbs1_sel_o = Signal(intbv(0)[SELECT_WIDTH:])
wbs1_stb_o = Signal(bool(0))
wbs1_cyc_o = Signal(bool(0))
# WB master
wbm_inst = wb.WBMaster()
wbm_logic = wbm_inst.create_logic(clk,
adr_o=wbm_adr_i,
dat_i=wbm_dat_o,
dat_o=wbm_dat_i,
we_o=wbm_we_i,
sel_o=wbm_sel_i,
stb_o=wbm_stb_i,
ack_i=wbm_ack_o,
cyc_o=wbm_cyc_i,
name='master')
# WB RAM model
wb_ram0_inst = wb.WBRam(2**16)
wb_ram0_port0 = wb_ram0_inst.create_port(clk,
adr_i=wbs0_adr_o,
dat_i=wbs0_dat_o,
dat_o=wbs0_dat_i,
we_i=wbs0_we_o,
sel_i=wbs0_sel_o,
stb_i=wbs0_stb_o,
ack_o=wbs0_ack_i,
cyc_i=wbs0_cyc_o,
latency=1,
async=False,
name='slave0')
# WB RAM model
wb_ram1_inst = wb.WBRam(2**16)
wb_ram1_port0 = wb_ram1_inst.create_port(clk,
adr_i=wbs1_adr_o,
dat_i=wbs1_dat_o,
dat_o=wbs1_dat_i,
we_i=wbs1_we_o,
sel_i=wbs1_sel_o,
stb_i=wbs1_stb_o,
ack_o=wbs1_ack_i,
cyc_i=wbs1_cyc_o,
latency=1,
async=False,
name='slave1')
# DUT
dut = dut_wb_mux_2(clk, rst, current_test, wbm_adr_i, wbm_dat_i, wbm_dat_o,
wbm_we_i, wbm_sel_i, wbm_stb_i, wbm_ack_o, wbm_err_o,
wbm_rty_o, wbm_cyc_i, wbs0_adr_o, wbs0_dat_i,
wbs0_dat_o, wbs0_we_o, wbs0_sel_o, wbs0_stb_o,
wbs0_ack_i, wbs0_err_i, wbs0_rty_i, wbs0_cyc_o,
wbs0_addr, wbs0_addr_msk, wbs1_adr_o, wbs1_dat_i,
wbs1_dat_o, wbs1_we_o, wbs1_sel_o, wbs1_stb_o,
wbs1_ack_i, wbs1_err_i, wbs1_rty_i, wbs1_cyc_o,
wbs1_addr, wbs1_addr_msk)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
wbs0_addr.next = 0x00000000
wbs0_addr_msk.next = 0xFFFF0000
wbs1_addr.next = 0x00010000
wbs1_addr_msk.next = 0xFFFF0000
yield clk.posedge
print("test 1: write to slave 0")
current_test.next = 1
wbm_inst.init_write(0x00000004, b'\x11\x22\x33\x44')
yield wbm_inst.wait()
yield clk.posedge
data = wb_ram0_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram0_inst.read_mem(4, 4) == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 2: read from slave 0")
current_test.next = 2
wbm_inst.init_read(0x00000004, 4)
yield wbm_inst.wait()
yield clk.posedge
data = wbm_inst.get_read_data()
assert data[0] == 0x00000004
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 3: write to slave 1")
current_test.next = 3
wbm_inst.init_write(0x00010004, b'\x11\x22\x33\x44')
yield wbm_inst.wait()
yield clk.posedge
data = wb_ram1_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram1_inst.read_mem(4, 4) == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 4: read from slave 1")
current_test.next = 4
wbm_inst.init_read(0x00010004, 4)
yield wbm_inst.wait()
yield clk.posedge
data = wbm_inst.get_read_data()
assert data[0] == 0x00010004
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
raise StopSimulation
return dut, wbm_logic, wb_ram0_port0, wb_ram1_port0, clkgen, check
def bench():
# Parameters
DATA_WIDTH = 32
ADDR_WIDTH = 16
SELECT_WIDTH = 4
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
adr_i = Signal(intbv(0)[ADDR_WIDTH:])
dat_i = Signal(intbv(0)[DATA_WIDTH:])
we_i = Signal(bool(0))
sel_i = Signal(intbv(0)[SELECT_WIDTH:])
stb_i = Signal(bool(0))
cyc_i = Signal(bool(0))
# Outputs
dat_o = Signal(intbv(0)[DATA_WIDTH:])
ack_o = Signal(bool(0))
# WB master
wbm_inst = wb.WBMaster()
wbm_logic = wbm_inst.create_logic(clk,
adr_o=adr_i,
dat_i=dat_o,
dat_o=dat_i,
we_o=we_i,
sel_o=sel_i,
stb_o=stb_i,
ack_i=ack_o,
cyc_o=cyc_i,
name='master')
# DUT
dut = dut_wb_ram(clk,
rst,
current_test,
adr_i,
dat_i,
dat_o,
we_i,
sel_i,
stb_i,
ack_o,
cyc_i)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: read and write")
current_test.next = 1
wbm_inst.init_write(4, b'\x11\x22\x33\x44')
yield wbm_inst.wait()
yield clk.posedge
wbm_inst.init_read(4, 4)
yield wbm_inst.wait()
yield clk.posedge
data = wbm_inst.get_read_data()
assert data[0] == 4
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 2: various reads and writes")
current_test.next = 2
for length in range(1,8):
for offset in range(4):
wbm_inst.init_write(256*(16*offset+length)+offset, b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
yield wbm_inst.wait()
yield clk.posedge
for length in range(1,8):
for offset in range(4):
wbm_inst.init_read(256*(16*offset+length)+offset, length)
yield wbm_inst.wait()
yield clk.posedge
data = wbm_inst.get_read_data()
assert data[0] == 256*(16*offset+length)+offset
assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
raise StopSimulation
return dut, wbm_logic, clkgen, check
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
port0_adr_i = Signal(intbv(0)[32:])
port0_dat_i = Signal(intbv(0)[32:])
port0_we_i = Signal(bool(0))
port0_sel_i = Signal(intbv(0)[4:])
port0_stb_i = Signal(bool(0))
port0_cyc_i = Signal(bool(0))
# Outputs
port0_dat_o = Signal(intbv(0)[32:])
port0_ack_o = Signal(bool(0))
# WB master
wb_master_inst = wb.WBMaster()
wb_master_logic = wb_master_inst.create_logic(clk,
adr_o=port0_adr_i,
dat_i=port0_dat_o,
dat_o=port0_dat_i,
we_o=port0_we_i,
sel_o=port0_sel_i,
stb_o=port0_stb_i,
ack_i=port0_ack_o,
cyc_o=port0_cyc_i,
name='master')
# WB RAM model
wb_ram_inst = wb.WBRam(2**16)
wb_ram_port0 = wb_ram_inst.create_port(clk,
adr_i=port0_adr_i,
dat_i=port0_dat_i,
dat_o=port0_dat_o,
we_i=port0_we_i,
sel_i=port0_sel_i,
stb_i=port0_stb_i,
ack_o=port0_ack_o,
cyc_i=port0_cyc_i,
latency=1,
asynchronous=False,
name='port0')
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: baseline")
current_test.next = 1
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
yield delay(100)
yield clk.posedge
print("test 2: direct write")
current_test.next = 2
wb_ram_inst.write_mem(0, b'test')
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(0, 4) == b'test'
yield clk.posedge
print("test 3: write via port0")
current_test.next = 3
wb_master_inst.init_write(4, b'\x11\x22\x33\x44')
yield wb_master_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(4, 4) == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 4: read via port0")
current_test.next = 4
wb_master_inst.init_read(4, 4)
yield wb_master_inst.wait()
yield clk.posedge
data = wb_master_inst.get_read_data()
assert data[0] == 4
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 5: various writes")
current_test.next = 5
for length in range(1, 8):
for offset in range(4, 8):
wb_ram_inst.write_mem(256 * (16 * offset + length),
b'\xAA' * 32)
wb_master_inst.init_write(
256 * (16 * offset + length) + offset,
b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
yield wb_master_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(256 * (16 * offset + length), 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset,
length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset - 1, 1) == b'\xAA'
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset + length,
1) == b'\xAA'
yield delay(100)
yield clk.posedge
print("test 6: various reads")
current_test.next = 6
for length in range(1, 8):
for offset in range(4, 8):
wb_master_inst.init_read(256 * (16 * offset + length) + offset,
length)
yield wb_master_inst.wait()
yield clk.posedge
data = wb_master_inst.get_read_data()
assert data[0] == 256 * (16 * offset + length) + offset
assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
yield clk.posedge
print("test 7: write words")
current_test.next = 7
for offset in range(4):
wb_master_inst.init_write_words(
(0x4000 + offset * 64 + 0) / 2 + offset, [0x1234])
wb_master_inst.init_write_dwords(
(0x4000 + offset * 64 + 16) / 4 + offset, [0x12345678])
wb_master_inst.init_write_qwords(
(0x4000 + offset * 64 + 32) / 8 + offset, [0x1234567887654321])
yield wb_master_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(0x4000 + offset * 64, 64)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(
(0x4000 + offset * 64 + 0) + offset * 2, 2) == b'\x34\x12'
assert wb_ram_inst.read_mem(
(0x4000 + offset * 64 + 16) + offset * 4,
4) == b'\x78\x56\x34\x12'
assert wb_ram_inst.read_mem(
(0x4000 + offset * 64 + 32) + offset * 8,
8) == b'\x21\x43\x65\x87\x78\x56\x34\x12'
assert wb_ram_inst.read_words(
(0x4000 + offset * 64 + 0) / 2 + offset, 1)[0] == 0x1234
assert wb_ram_inst.read_dwords(
(0x4000 + offset * 64 + 16) / 4 + offset, 1)[0] == 0x12345678
assert wb_ram_inst.read_qwords(
(0x4000 + offset * 64 + 32) / 8 + offset,
1)[0] == 0x1234567887654321
yield delay(100)
yield clk.posedge
print("test 8: read words")
current_test.next = 8
for offset in range(4):
wb_master_inst.init_read_words(
(0x4000 + offset * 64 + 0) / 2 + offset, 1)
wb_master_inst.init_read_dwords(
(0x4000 + offset * 64 + 16) / 4 + offset, 1)
wb_master_inst.init_read_qwords(
(0x4000 + offset * 64 + 32) / 8 + offset, 1)
yield wb_master_inst.wait()
yield clk.posedge
data = wb_master_inst.get_read_data_words()
assert data[0] == (0x4000 + offset * 64 + 0) / 2 + offset
assert data[1][0] == 0x1234
data = wb_master_inst.get_read_data_dwords()
assert data[0] == (0x4000 + offset * 64 + 16) / 4 + offset
assert data[1][0] == 0x12345678
data = wb_master_inst.get_read_data_qwords()
assert data[0] == (0x4000 + offset * 64 + 32) / 8 + offset
assert data[1][0] == 0x1234567887654321
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
ADDR_WIDTH = 32
WBM_DATA_WIDTH = 8
WBM_SELECT_WIDTH = 1
WBS_DATA_WIDTH = 32
WBS_SELECT_WIDTH = 4
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
wbm_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
wbm_dat_i = Signal(intbv(0)[WBM_DATA_WIDTH:])
wbm_we_i = Signal(bool(0))
wbm_sel_i = Signal(intbv(0)[WBM_SELECT_WIDTH:])
wbm_stb_i = Signal(bool(0))
wbm_cyc_i = Signal(bool(0))
wbs_dat_i = Signal(intbv(0)[WBS_DATA_WIDTH:])
wbs_ack_i = Signal(bool(0))
wbs_err_i = Signal(bool(0))
wbs_rty_i = Signal(bool(0))
# Outputs
wbm_dat_o = Signal(intbv(0)[WBM_DATA_WIDTH:])
wbm_ack_o = Signal(bool(0))
wbm_err_o = Signal(bool(0))
wbm_rty_o = Signal(bool(0))
wbs_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
wbs_dat_o = Signal(intbv(0)[WBS_DATA_WIDTH:])
wbs_we_o = Signal(bool(0))
wbs_sel_o = Signal(intbv(0)[WBS_SELECT_WIDTH:])
wbs_stb_o = Signal(bool(0))
wbs_cyc_o = Signal(bool(0))
# WB master
wbm_inst = wb.WBMaster()
wbm_logic = wbm_inst.create_logic(clk,
adr_o=wbm_adr_i,
dat_i=wbm_dat_o,
dat_o=wbm_dat_i,
we_o=wbm_we_i,
sel_o=wbm_sel_i,
stb_o=wbm_stb_i,
ack_i=wbm_ack_o,
cyc_o=wbm_cyc_i,
name='master')
# WB RAM model
wb_ram_inst = wb.WBRam(2**16)
wb_ram_port0 = wb_ram_inst.create_port(clk,
adr_i=wbs_adr_o,
dat_i=wbs_dat_o,
dat_o=wbs_dat_i,
we_i=wbs_we_o,
sel_i=wbs_sel_o,
stb_i=wbs_stb_o,
ack_o=wbs_ack_i,
cyc_i=wbs_cyc_o,
latency=1,
asynchronous=False,
name='slave')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
wbm_adr_i=wbm_adr_i,
wbm_dat_i=wbm_dat_i,
wbm_dat_o=wbm_dat_o,
wbm_we_i=wbm_we_i,
wbm_sel_i=wbm_sel_i,
wbm_stb_i=wbm_stb_i,
wbm_ack_o=wbm_ack_o,
wbm_err_o=wbm_err_o,
wbm_rty_o=wbm_rty_o,
wbm_cyc_i=wbm_cyc_i,
wbs_adr_o=wbs_adr_o,
wbs_dat_i=wbs_dat_i,
wbs_dat_o=wbs_dat_o,
wbs_we_o=wbs_we_o,
wbs_sel_o=wbs_sel_o,
wbs_stb_o=wbs_stb_o,
wbs_ack_i=wbs_ack_i,
wbs_err_i=wbs_err_i,
wbs_rty_i=wbs_rty_i,
wbs_cyc_o=wbs_cyc_o)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: write")
current_test.next = 1
wbm_inst.init_write(4, b'\x11\x22\x33\x44')
yield wbm_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(4, 4) == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 2: read")
current_test.next = 2
wbm_inst.init_read(4, 4)
yield wbm_inst.wait()
yield clk.posedge
data = wbm_inst.get_read_data()
assert data[0] == 4
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 3: various writes")
current_test.next = 3
for length in range(1, 8):
for offset in range(4, 8):
wb_ram_inst.write_mem(256 * (16 * offset + length),
b'\xAA' * 16)
wbm_inst.init_write(
256 * (16 * offset + length) + offset,
b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
yield wbm_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(256 * (16 * offset + length), 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset,
length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset - 1, 1) == b'\xAA'
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset + length,
1) == b'\xAA'
yield delay(100)
yield clk.posedge
print("test 4: various reads")
current_test.next = 4
for length in range(1, 8):
for offset in range(4, 8):
wbm_inst.init_read(256 * (16 * offset + length) + offset,
length)
yield wbm_inst.wait()
yield clk.posedge
data = wbm_inst.get_read_data()
assert data[0] == 256 * (16 * offset + length) + offset
assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
wb_adr_i = Signal(intbv(0)[32:])
wb_dat_i = Signal(intbv(0)[8:])
wb_we_i = Signal(bool(0))
wb_stb_i = Signal(bool(0))
wb_cyc_i = Signal(bool(0))
mcb_cmd_empty = Signal(bool(0))
mcb_cmd_full = Signal(bool(0))
mcb_wr_empty = Signal(bool(0))
mcb_wr_full = Signal(bool(0))
mcb_wr_underrun = Signal(bool(0))
mcb_wr_count = Signal(intbv(0)[7:])
mcb_wr_error = Signal(bool(0))
mcb_rd_data = Signal(intbv(0)[32:])
mcb_rd_empty = Signal(bool(0))
mcb_rd_full = Signal(bool(0))
mcb_rd_overflow = Signal(bool(0))
mcb_rd_count = Signal(intbv(0)[7:])
mcb_rd_error = Signal(bool(0))
# Outputs
wb_dat_o = Signal(intbv(0)[8:])
wb_ack_o = Signal(bool(0))
mcb_cmd_clk = Signal(bool(0))
mcb_cmd_en = Signal(bool(0))
mcb_cmd_instr = Signal(intbv(0)[3:])
mcb_cmd_bl = Signal(intbv(0)[6:])
mcb_cmd_byte_addr = Signal(intbv(0)[32:])
mcb_wr_clk = Signal(bool(0))
mcb_wr_en = Signal(bool(0))
mcb_wr_mask = Signal(intbv(0)[4:])
mcb_wr_data = Signal(intbv(0)[32:])
mcb_rd_clk = Signal(bool(0))
mcb_rd_en = Signal(bool(1))
# WB master
wbm_inst = wb.WBMaster()
wbm_logic = wbm_inst.create_logic(clk,
adr_o=wb_adr_i,
dat_i=wb_dat_o,
dat_o=wb_dat_i,
we_o=wb_we_i,
stb_o=wb_stb_i,
ack_i=wb_ack_o,
cyc_o=wb_cyc_i,
name='master')
# MCB model
mcb_inst = mcb.MCB(2**16)
mcb_controller = mcb_inst.create_controller(clk, rst)
mcb_port0 = mcb_inst.create_readwrite_port(cmd_clk=mcb_cmd_clk,
cmd_en=mcb_cmd_en,
cmd_instr=mcb_cmd_instr,
cmd_bl=mcb_cmd_bl,
cmd_byte_addr=mcb_cmd_byte_addr,
cmd_empty=mcb_cmd_empty,
cmd_full=mcb_cmd_full,
wr_clk=mcb_wr_clk,
wr_en=mcb_wr_en,
wr_mask=mcb_wr_mask,
wr_data=mcb_wr_data,
wr_empty=mcb_wr_empty,
wr_full=mcb_wr_full,
wr_underrun=mcb_wr_underrun,
wr_count=mcb_wr_count,
wr_error=mcb_wr_error,
rd_clk=mcb_rd_clk,
rd_en=mcb_rd_en,
rd_data=mcb_rd_data,
rd_empty=mcb_rd_empty,
rd_full=mcb_rd_full,
rd_overflow=mcb_rd_overflow,
rd_count=mcb_rd_count,
rd_error=mcb_rd_error,
name='port0')
# DUT
dut = dut_wb_mcb_8(clk, rst, current_test, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, wb_ack_o, wb_cyc_i, mcb_cmd_clk,
mcb_cmd_en, mcb_cmd_instr, mcb_cmd_bl,
mcb_cmd_byte_addr, mcb_cmd_empty, mcb_cmd_full,
mcb_wr_clk, mcb_wr_en, mcb_wr_mask, mcb_wr_data,
mcb_wr_empty, mcb_wr_full, mcb_wr_underrun,
mcb_wr_count, mcb_wr_error, mcb_rd_clk, mcb_rd_en,
mcb_rd_data, mcb_rd_empty, mcb_rd_full, mcb_rd_overflow,
mcb_rd_count, mcb_rd_error)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: write")
current_test.next = 1
wbm_inst.init_write(4, '\x11\x22\x33\x44')
yield wbm_inst.wait()
yield clk.posedge
data = mcb_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join("{:02x}".format(ord(c)) for c in data[i:i + 16]))
assert mcb_inst.read_mem(4, 4) == '\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 2: read")
current_test.next = 2
wbm_inst.init_read(4, 4)
yield wbm_inst.wait()
yield clk.posedge
data = wbm_inst.get_read_data()
assert data[0] == 4
assert data[1] == '\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 3: various writes")
current_test.next = 3
for length in range(1, 8):
for offset in range(4):
wbm_inst.init_write(
256 * (16 * offset + length) + offset,
'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
yield wbm_inst.wait()
yield clk.posedge
data = mcb_inst.read_mem(256 * (16 * offset + length), 32)
for i in range(0, len(data), 16):
print(" ".join("{:02x}".format(ord(c))
for c in data[i:i + 16]))
assert mcb_inst.read_mem(
256 * (16 * offset + length) + offset,
length) == '\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
yield clk.posedge
print("test 4: various reads")
current_test.next = 4
for length in range(1, 8):
for offset in range(4):
wbm_inst.init_read(256 * (16 * offset + length) + offset,
length)
yield wbm_inst.wait()
yield clk.posedge
data = wbm_inst.get_read_data()
assert data[0] == 256 * (16 * offset + length) + offset
assert data[1] == '\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
raise StopSimulation
return dut, wbm_logic, mcb_controller, mcb_port0, clkgen, check
def bench():
# Parameters
DEFAULT_PRESCALE = 1
FIXED_PRESCALE = 0
CMD_FIFO = 1
CMD_FIFO_ADDR_WIDTH = 5
WRITE_FIFO = 1
WRITE_FIFO_ADDR_WIDTH = 5
READ_FIFO = 1
READ_FIFO_ADDR_WIDTH = 5
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
wbs_adr_i = Signal(intbv(0)[3:])
wbs_dat_i = Signal(intbv(0)[16:])
wbs_we_i = Signal(bool(0))
wbs_sel_i = Signal(intbv(0)[2:])
wbs_stb_i = Signal(bool(0))
wbs_cyc_i = Signal(bool(0))
i2c_scl_i = Signal(bool(1))
i2c_sda_i = Signal(bool(1))
s1_scl_i = Signal(bool(1))
s1_sda_i = Signal(bool(1))
s2_scl_i = Signal(bool(1))
s2_sda_i = Signal(bool(1))
# Outputs
wbs_dat_o = Signal(intbv(0)[16:])
wbs_ack_o = Signal(bool(0))
i2c_scl_o = Signal(bool(1))
i2c_scl_t = Signal(bool(1))
i2c_sda_o = Signal(bool(1))
i2c_sda_t = Signal(bool(1))
s1_scl_o = Signal(bool(1))
s1_scl_t = Signal(bool(1))
s1_sda_o = Signal(bool(1))
s1_sda_t = Signal(bool(1))
s2_scl_o = Signal(bool(1))
s2_scl_t = Signal(bool(1))
s2_sda_o = Signal(bool(1))
s2_sda_t = Signal(bool(1))
# WB master
wbm_inst = wb.WBMaster()
wbm_logic = wbm_inst.create_logic(clk,
adr_o=wbs_adr_i,
dat_i=wbs_dat_o,
dat_o=wbs_dat_i,
we_o=wbs_we_i,
sel_o=wbs_sel_i,
stb_o=wbs_stb_i,
ack_i=wbs_ack_o,
cyc_o=wbs_cyc_i,
name='master')
# I2C memory model 1
i2c_mem_inst1 = i2c.I2CMem(1024)
i2c_mem_logic1 = i2c_mem_inst1.create_logic(scl_i=s1_scl_i,
scl_o=s1_scl_o,
scl_t=s1_scl_t,
sda_i=s1_sda_i,
sda_o=s1_sda_o,
sda_t=s1_sda_t,
abw=2,
address=0x50,
latency=0,
name='slave1')
# I2C memory model 2
i2c_mem_inst2 = i2c.I2CMem(1024)
i2c_mem_logic2 = i2c_mem_inst2.create_logic(scl_i=s2_scl_i,
scl_o=s2_scl_o,
scl_t=s2_scl_t,
sda_i=s2_sda_i,
sda_o=s2_sda_o,
sda_t=s2_sda_t,
abw=2,
address=0x51,
latency=1000,
name='slave2')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
wbs_adr_i=wbs_adr_i,
wbs_dat_i=wbs_dat_i,
wbs_dat_o=wbs_dat_o,
wbs_we_i=wbs_we_i,
wbs_sel_i=wbs_sel_i,
wbs_stb_i=wbs_stb_i,
wbs_ack_o=wbs_ack_o,
wbs_cyc_i=wbs_cyc_i,
i2c_scl_i=i2c_scl_i,
i2c_scl_o=i2c_scl_o,
i2c_scl_t=i2c_scl_t,
i2c_sda_i=i2c_sda_i,
i2c_sda_o=i2c_sda_o,
i2c_sda_t=i2c_sda_t)
@always_comb
def bus():
# emulate I2C wired AND
i2c_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o
i2c_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o
s1_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o
s1_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o
s2_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o
s2_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: write")
current_test.next = 1
wbm_inst.init_write(2, b'\x50\x04\x00')
wbm_inst.init_write(3, b'\x04\x04')
wbm_inst.init_write(3, b'\x04\x11')
wbm_inst.init_write(3, b'\x04\x22')
wbm_inst.init_write(3, b'\x04\x33')
wbm_inst.init_write(3, b'\x14\x44')
yield wbm_inst.wait()
yield clk.posedge
while True:
wbm_inst.init_read(0, 1)
yield wbm_inst.wait()
data = wbm_inst.get_read_data()
if data[1][0] & 0x03 == 0:
break
data = i2c_mem_inst1.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert i2c_mem_inst1.read_mem(4, 4) == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 2: read")
current_test.next = 2
wbm_inst.init_write(2, b'\x50\x04\x00')
wbm_inst.init_write(3, b'\x04\x04')
wbm_inst.init_write(3, b'\x03')
wbm_inst.init_write(3, b'\x02')
wbm_inst.init_write(3, b'\x02')
wbm_inst.init_write(3, b'\x12')
yield wbm_inst.wait()
yield clk.posedge
while True:
wbm_inst.init_read(0, 1)
yield wbm_inst.wait()
data = wbm_inst.get_read_data()
if data[1][0] & 0x03 == 0:
break
wbm_inst.init_read(4, 2)
wbm_inst.init_read(4, 2)
wbm_inst.init_read(4, 2)
wbm_inst.init_read(4, 2)
yield wbm_inst.wait()
yield clk.posedge
data = wbm_inst.get_read_data()
assert data[1] == b'\x11\x00'
data = wbm_inst.get_read_data()
assert data[1] == b'\x22\x00'
data = wbm_inst.get_read_data()
assert data[1] == b'\x33\x00'
data = wbm_inst.get_read_data()
assert data[1] == b'\x44\x01'
yield delay(100)
yield clk.posedge
print("test 3: write to slave 2")
current_test.next = 3
wbm_inst.init_write(2, b'\x51\x08\x00\x00')
wbm_inst.init_write(4, b'\x04\x00')
wbm_inst.init_write(4, b'\x44\x00')
wbm_inst.init_write(4, b'\x33\x00')
wbm_inst.init_write(4, b'\x22\x00')
wbm_inst.init_write(4, b'\x11\x01')
wbm_inst.init_write(3, b'\x10')
yield wbm_inst.wait()
yield clk.posedge
while True:
wbm_inst.init_read(0, 1)
yield wbm_inst.wait()
data = wbm_inst.get_read_data()
if data[1][0] & 0x03 == 0:
break
data = i2c_mem_inst2.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert i2c_mem_inst2.read_mem(4, 4) == b'\x44\x33\x22\x11'
yield delay(100)
yield clk.posedge
print("test 4: read from slave 2")
current_test.next = 4
wbm_inst.init_write(2, b'\x51\x04\x00')
wbm_inst.init_write(3, b'\x04\x04')
wbm_inst.init_write(3, b'\x03')
wbm_inst.init_write(3, b'\x02')
wbm_inst.init_write(3, b'\x02')
wbm_inst.init_write(3, b'\x12')
yield wbm_inst.wait()
yield clk.posedge
while True:
wbm_inst.init_read(0, 1)
yield wbm_inst.wait()
data = wbm_inst.get_read_data()
if data[1][0] & 0x03 == 0:
break
wbm_inst.init_read(4, 2)
wbm_inst.init_read(4, 2)
wbm_inst.init_read(4, 2)
wbm_inst.init_read(4, 2)
yield wbm_inst.wait()
yield clk.posedge
data = wbm_inst.get_read_data()
assert data[1] == b'\x44\x00'
data = wbm_inst.get_read_data()
assert data[1] == b'\x33\x00'
data = wbm_inst.get_read_data()
assert data[1] == b'\x22\x00'
data = wbm_inst.get_read_data()
assert data[1] == b'\x11\x01'
yield delay(100)
yield clk.posedge
print("test 5: write to nonexistent device")
current_test.next = 5
wbm_inst.init_write(2, b'\x52\x04\x00')
wbm_inst.init_write(3, b'\x04\x04')
wbm_inst.init_write(3, b'\x04\xde')
wbm_inst.init_write(3, b'\x04\xad')
wbm_inst.init_write(3, b'\x04\xbe')
wbm_inst.init_write(3, b'\x14\xef')
yield wbm_inst.wait()
yield clk.posedge
got_missed_ack = False
while True:
wbm_inst.init_read(0, 1)
yield wbm_inst.wait()
data = wbm_inst.get_read_data()
if data[1][0] & 0x08:
got_missed_ack = True
if data[1][0] & 0x03 == 0:
break
assert got_missed_ack
yield delay(100)
raise StopSimulation
return dut, wbm_logic, i2c_mem_logic1, i2c_mem_logic2, bus, clkgen, check
def bench():
# Parameters
DATA_WIDTH = 32
ADDR_WIDTH = 32
SELECT_WIDTH = (DATA_WIDTH / 8)
ARB_TYPE = "PRIORITY"
LSB_PRIORITY = "HIGH"
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
wbm0_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
wbm0_dat_i = Signal(intbv(0)[DATA_WIDTH:])
wbm0_we_i = Signal(bool(0))
wbm0_sel_i = Signal(intbv(0)[SELECT_WIDTH:])
wbm0_stb_i = Signal(bool(0))
wbm0_cyc_i = Signal(bool(0))
wbm1_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
wbm1_dat_i = Signal(intbv(0)[DATA_WIDTH:])
wbm1_we_i = Signal(bool(0))
wbm1_sel_i = Signal(intbv(0)[SELECT_WIDTH:])
wbm1_stb_i = Signal(bool(0))
wbm1_cyc_i = Signal(bool(0))
wbs_dat_i = Signal(intbv(0)[DATA_WIDTH:])
wbs_ack_i = Signal(bool(0))
wbs_err_i = Signal(bool(0))
wbs_rty_i = Signal(bool(0))
# Outputs
wbm0_dat_o = Signal(intbv(0)[DATA_WIDTH:])
wbm0_ack_o = Signal(bool(0))
wbm0_err_o = Signal(bool(0))
wbm0_rty_o = Signal(bool(0))
wbm1_dat_o = Signal(intbv(0)[DATA_WIDTH:])
wbm1_ack_o = Signal(bool(0))
wbm1_err_o = Signal(bool(0))
wbm1_rty_o = Signal(bool(0))
wbs_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
wbs_dat_o = Signal(intbv(0)[DATA_WIDTH:])
wbs_we_o = Signal(bool(0))
wbs_sel_o = Signal(intbv(0)[SELECT_WIDTH:])
wbs_stb_o = Signal(bool(0))
wbs_cyc_o = Signal(bool(0))
# WB master
wbm0_inst = wb.WBMaster()
wbm0_logic = wbm0_inst.create_logic(clk,
adr_o=wbm0_adr_i,
dat_i=wbm0_dat_o,
dat_o=wbm0_dat_i,
we_o=wbm0_we_i,
sel_o=wbm0_sel_i,
stb_o=wbm0_stb_i,
ack_i=wbm0_ack_o,
cyc_o=wbm0_cyc_i,
name='master0')
# WB master
wbm1_inst = wb.WBMaster()
wbm1_logic = wbm1_inst.create_logic(clk,
adr_o=wbm1_adr_i,
dat_i=wbm1_dat_o,
dat_o=wbm1_dat_i,
we_o=wbm1_we_i,
sel_o=wbm1_sel_i,
stb_o=wbm1_stb_i,
ack_i=wbm1_ack_o,
cyc_o=wbm1_cyc_i,
name='master1')
# WB RAM model
wb_ram_inst = wb.WBRam(2**16)
wb_ram_port0 = wb_ram_inst.create_port(clk,
adr_i=wbs_adr_o,
dat_i=wbs_dat_o,
dat_o=wbs_dat_i,
we_i=wbs_we_o,
sel_i=wbs_sel_o,
stb_i=wbs_stb_o,
ack_o=wbs_ack_i,
cyc_i=wbs_cyc_o,
latency=1,
asynchronous=False,
name='slave')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
wbm0_adr_i=wbm0_adr_i,
wbm0_dat_i=wbm0_dat_i,
wbm0_dat_o=wbm0_dat_o,
wbm0_we_i=wbm0_we_i,
wbm0_sel_i=wbm0_sel_i,
wbm0_stb_i=wbm0_stb_i,
wbm0_ack_o=wbm0_ack_o,
wbm0_err_o=wbm0_err_o,
wbm0_rty_o=wbm0_rty_o,
wbm0_cyc_i=wbm0_cyc_i,
wbm1_adr_i=wbm1_adr_i,
wbm1_dat_i=wbm1_dat_i,
wbm1_dat_o=wbm1_dat_o,
wbm1_we_i=wbm1_we_i,
wbm1_sel_i=wbm1_sel_i,
wbm1_stb_i=wbm1_stb_i,
wbm1_ack_o=wbm1_ack_o,
wbm1_err_o=wbm1_err_o,
wbm1_rty_o=wbm1_rty_o,
wbm1_cyc_i=wbm1_cyc_i,
wbs_adr_o=wbs_adr_o,
wbs_dat_i=wbs_dat_i,
wbs_dat_o=wbs_dat_o,
wbs_we_o=wbs_we_o,
wbs_sel_o=wbs_sel_o,
wbs_stb_o=wbs_stb_o,
wbs_ack_i=wbs_ack_i,
wbs_err_i=wbs_err_i,
wbs_rty_i=wbs_rty_i,
wbs_cyc_o=wbs_cyc_o)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: master 0")
current_test.next = 1
wbm0_inst.init_write(0x00000000, b'\x11\x22\x33\x44')
yield wbm0_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(0x00000000, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(0, 4) == b'\x11\x22\x33\x44'
wbm0_inst.init_read(0x00000000, 4)
yield wbm0_inst.wait()
yield clk.posedge
data = wbm0_inst.get_read_data()
assert data[0] == 0x00000000
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 2: master 1")
current_test.next = 2
wbm1_inst.init_write(0x00001000, b'\x11\x22\x33\x44')
yield wbm1_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(0x00001000, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(0, 4) == b'\x11\x22\x33\x44'
wbm1_inst.init_read(0x00001000, 4)
yield wbm0_inst.wait()
yield wbm1_inst.wait()
yield clk.posedge
data = wbm1_inst.get_read_data()
assert data[0] == 0x00001000
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 3: arbitration")
current_test.next = 3
wbm0_inst.init_write(0x00000010, bytearray(range(16)))
wbm0_inst.init_write(0x00000020, bytearray(range(16)))
wbm1_inst.init_write(0x00001010, bytearray(range(16)))
wbm1_inst.init_write(0x00001020, bytearray(range(16)))
yield wbm1_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(0x00000010, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
data = wb_ram_inst.read_mem(0x00001010, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(0, 4) == b'\x11\x22\x33\x44'
wbm0_inst.init_read(0x00000010, 16)
wbm0_inst.init_read(0x00000020, 16)
wbm1_inst.init_read(0x00001010, 16)
wbm1_inst.init_read(0x00001020, 16)
yield wbm0_inst.wait()
yield wbm1_inst.wait()
yield clk.posedge
data = wbm0_inst.get_read_data()
assert data[0] == 0x00000010
assert data[1] == bytearray(range(16))
data = wbm0_inst.get_read_data()
assert data[0] == 0x00000020
assert data[1] == bytearray(range(16))
data = wbm1_inst.get_read_data()
assert data[0] == 0x00001010
assert data[1] == bytearray(range(16))
data = wbm1_inst.get_read_data()
assert data[0] == 0x00001020
assert data[1] == bytearray(range(16))
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
DATA_WIDTH = 32
ADDR_WIDTH = 32
SELECT_WIDTH = 4
# Inputs
a_clk = Signal(bool(0))
a_rst = Signal(bool(0))
b_clk = Signal(bool(0))
b_rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
a_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
a_dat_i = Signal(intbv(0)[DATA_WIDTH:])
a_we_i = Signal(bool(0))
a_sel_i = Signal(intbv(0)[SELECT_WIDTH:])
a_stb_i = Signal(bool(0))
a_cyc_i = Signal(bool(0))
b_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
b_dat_i = Signal(intbv(0)[DATA_WIDTH:])
b_we_i = Signal(bool(0))
b_sel_i = Signal(intbv(0)[SELECT_WIDTH:])
b_stb_i = Signal(bool(0))
b_cyc_i = Signal(bool(0))
# Outputs
a_dat_o = Signal(intbv(0)[DATA_WIDTH:])
a_ack_o = Signal(bool(0))
b_dat_o = Signal(intbv(0)[DATA_WIDTH:])
b_ack_o = Signal(bool(0))
# WB master A
wbm_inst_a = wb.WBMaster()
wbm_logic_a = wbm_inst_a.create_logic(a_clk,
adr_o=a_adr_i,
dat_i=a_dat_o,
dat_o=a_dat_i,
we_o=a_we_i,
sel_o=a_sel_i,
stb_o=a_stb_i,
ack_i=a_ack_o,
cyc_o=a_cyc_i,
name='master_a')
# WB master B
wbm_inst_b = wb.WBMaster()
wbm_logic_b = wbm_inst_b.create_logic(b_clk,
adr_o=b_adr_i,
dat_i=b_dat_o,
dat_o=b_dat_i,
we_o=b_we_i,
sel_o=b_sel_i,
stb_o=b_stb_i,
ack_i=b_ack_o,
cyc_o=b_cyc_i,
name='master_')
# DUT
dut = dut_wb_dp_ram(a_clk, a_rst, b_clk, b_rst, current_test, a_adr_i,
a_dat_i, a_dat_o, a_we_i, a_sel_i, a_stb_i, a_ack_o,
a_cyc_i, b_adr_i, b_dat_i, b_dat_o, b_we_i, b_sel_i,
b_stb_i, b_ack_o, b_cyc_i)
@always(delay(4))
def a_clkgen():
a_clk.next = not a_clk
@always(delay(5))
def b_clkgen():
b_clk.next = not b_clk
@instance
def check():
yield delay(100)
yield a_clk.posedge
a_rst.next = 1
b_rst.next = 1
yield a_clk.posedge
yield a_clk.posedge
yield a_clk.posedge
a_rst.next = 0
b_rst.next = 0
yield a_clk.posedge
yield delay(100)
yield a_clk.posedge
yield a_clk.posedge
print("test 1: read and write (port A)")
current_test.next = 1
wbm_inst_a.init_write(4, b'\x11\x22\x33\x44')
yield wbm_inst_a.wait()
yield a_clk.posedge
wbm_inst_a.init_read(4, 4)
yield wbm_inst_a.wait()
yield a_clk.posedge
data = wbm_inst_a.get_read_data()
assert data[0] == 4
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield a_clk.posedge
print("test 2: read and write (port B)")
current_test.next = 2
wbm_inst_b.init_write(4, b'\x11\x22\x33\x44')
yield wbm_inst_b.wait()
yield b_clk.posedge
wbm_inst_b.init_read(4, 4)
yield wbm_inst_b.wait()
yield b_clk.posedge
data = wbm_inst_b.get_read_data()
assert data[0] == 4
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield a_clk.posedge
print("test 3: various reads and writes (port A)")
current_test.next = 3
for length in range(1, 8):
for offset in range(4):
wbm_inst_a.init_write(
256 * (16 * offset + length) + offset,
b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
yield wbm_inst_a.wait()
yield a_clk.posedge
for length in range(1, 8):
for offset in range(4):
wbm_inst_a.init_read(256 * (16 * offset + length) + offset,
length)
yield wbm_inst_a.wait()
yield a_clk.posedge
data = wbm_inst_a.get_read_data()
assert data[0] == 256 * (16 * offset + length) + offset
assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
yield a_clk.posedge
print("test 4: various reads and writes (port B)")
current_test.next = 4
for length in range(1, 8):
for offset in range(4):
wbm_inst_b.init_write(
256 * (16 * offset + length) + offset,
b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
yield wbm_inst_b.wait()
yield b_clk.posedge
for length in range(1, 8):
for offset in range(4):
wbm_inst_b.init_read(256 * (16 * offset + length) + offset,
length)
yield wbm_inst_b.wait()
yield b_clk.posedge
data = wbm_inst_b.get_read_data()
assert data[0] == 256 * (16 * offset + length) + offset
assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
yield a_clk.posedge
print("test 5: simultaneous read and write")
current_test.next = 5
wbm_inst_a.init_write(8, b'\xAA\xAA\xAA\xAA')
wbm_inst_b.init_write(12, b'\xBB\xBB\xBB\xBB')
yield wbm_inst_a.wait()
yield wbm_inst_b.wait()
yield a_clk.posedge
wbm_inst_a.init_read(12, 4)
wbm_inst_b.init_read(8, 4)
yield wbm_inst_a.wait()
yield wbm_inst_b.wait()
yield a_clk.posedge
data = wbm_inst_a.get_read_data()
assert data[0] == 12
assert data[1] == b'\xBB\xBB\xBB\xBB'
data = wbm_inst_b.get_read_data()
assert data[0] == 8
assert data[1] == b'\xAA\xAA\xAA\xAA'
yield delay(100)
raise StopSimulation
return dut, wbm_logic_a, wbm_logic_b, a_clkgen, b_clkgen, check
def bench():
# Parameters
ADDR_WIDTH = 16
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
wb_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
wb_dat_i = Signal(intbv(0)[16:])
wb_we_i = Signal(bool(0))
wb_stb_i = Signal(bool(0))
wb_cyc_i = Signal(bool(0))
drp_di = Signal(intbv(0)[16:])
drp_rdy = Signal(bool(0))
# Outputs
wb_dat_o = Signal(intbv(0)[16:])
wb_ack_o = Signal(bool(0))
drp_addr = Signal(intbv(0)[ADDR_WIDTH:])
drp_do = Signal(intbv(0)[16:])
drp_en = Signal(bool(0))
drp_we = Signal(bool(0))
# WB master
wb_master_inst = wb.WBMaster()
wb_master_logic = wb_master_inst.create_logic(clk,
adr_o=wb_adr_i,
dat_i=wb_dat_o,
dat_o=wb_dat_i,
we_o=wb_we_i,
stb_o=wb_stb_i,
ack_i=wb_ack_o,
cyc_o=wb_cyc_i,
name='master')
# DRP model
drp_inst = drp.DRPRam(2**16)
drp_logic = drp_inst.create_port(clk,
addr=drp_addr,
di=drp_do,
do=drp_di,
en=drp_en,
we=drp_we,
rdy=drp_rdy,
latency=6,
name='drp')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
wb_adr_i=wb_adr_i,
wb_dat_i=wb_dat_i,
wb_dat_o=wb_dat_o,
wb_we_i=wb_we_i,
wb_stb_i=wb_stb_i,
wb_ack_o=wb_ack_o,
wb_cyc_i=wb_cyc_i,
drp_addr=drp_addr,
drp_do=drp_do,
drp_di=drp_di,
drp_en=drp_en,
drp_we=drp_we,
drp_rdy=drp_rdy)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: write words")
current_test.next = 1
for offset in range(4):
wb_master_inst.init_write_words(
(0x4000 + offset * 32 + 0) / 2 + offset, [0x1234])
wb_master_inst.init_write_dwords(
(0x4000 + offset * 32 + 16) / 4 + offset, [0x12345678])
yield wb_master_inst.wait()
yield clk.posedge
data = drp_inst.read_mem(0x4000 + offset * 32, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert drp_inst.read_mem((0x4000 + offset * 32 + 0) + offset * 2,
2) == b'\x34\x12'
assert drp_inst.read_mem((0x4000 + offset * 32 + 16) + offset * 4,
4) == b'\x78\x56\x34\x12'
assert drp_inst.read_words((0x4000 + offset * 32 + 0) / 2 + offset,
1)[0] == 0x1234
assert drp_inst.read_dwords(
(0x4000 + offset * 32 + 16) / 4 + offset, 1)[0] == 0x12345678
yield delay(100)
yield clk.posedge
print("test 2: read words")
current_test.next = 2
for offset in range(4):
wb_master_inst.init_read_words(
(0x4000 + offset * 32 + 0) / 2 + offset, 1)
wb_master_inst.init_read_dwords(
(0x4000 + offset * 32 + 16) / 4 + offset, 1)
yield wb_master_inst.wait()
yield clk.posedge
data = wb_master_inst.get_read_data_words()
assert data[0] == (0x4000 + offset * 32 + 0) / 2 + offset
assert data[1][0] == 0x1234
data = wb_master_inst.get_read_data_dwords()
assert data[0] == (0x4000 + offset * 32 + 16) / 4 + offset
assert data[1][0] == 0x12345678
yield delay(100)
raise StopSimulation
return dut, wb_master_logic, drp_logic, clkgen, check
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
port0_adr_i = Signal(intbv(0)[32:])
port0_dat_i = Signal(intbv(0)[32:])
port0_we_i = Signal(bool(0))
port0_sel_i = Signal(intbv(0)[4:])
port0_stb_i = Signal(bool(0))
port0_cyc_i = Signal(bool(0))
# Outputs
port0_dat_o = Signal(intbv(0)[32:])
port0_ack_o = Signal(bool(0))
# WB master
wb_master_inst = wb.WBMaster()
wb_master_logic = wb_master_inst.create_logic(clk,
adr_o=port0_adr_i,
dat_i=port0_dat_o,
dat_o=port0_dat_i,
we_o=port0_we_i,
sel_o=port0_sel_i,
stb_o=port0_stb_i,
ack_i=port0_ack_o,
cyc_o=port0_cyc_i,
name='master')
# WB RAM model
wb_ram_inst = wb.WBRam(2**16)
wb_ram_port0 = wb_ram_inst.create_port(clk,
adr_i=port0_adr_i,
dat_i=port0_dat_i,
dat_o=port0_dat_o,
we_i=port0_we_i,
sel_i=port0_sel_i,
stb_i=port0_stb_i,
ack_o=port0_ack_o,
cyc_i=port0_cyc_i,
latency=1,
async=False,
name='port0')
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: baseline")
current_test.next = 1
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
yield delay(100)
yield clk.posedge
print("test 2: direct write")
current_test.next = 2
wb_ram_inst.write_mem(0, b'test')
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(0, 4) == b'test'
yield clk.posedge
print("test 3: write via port0")
current_test.next = 3
wb_master_inst.init_write(4, b'\x11\x22\x33\x44')
yield wb_master_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(4, 4) == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 4: read via port0")
current_test.next = 4
wb_master_inst.init_read(4, 4)
yield wb_master_inst.wait()
yield clk.posedge
data = wb_master_inst.get_read_data()
assert data[0] == 4
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield clk.posedge
print("test 5: various writes")
current_test.next = 5
for length in range(1, 8):
for offset in range(4):
wb_master_inst.init_write(
256 * (16 * offset + length) + offset,
b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
yield wb_master_inst.wait()
yield clk.posedge
data = wb_ram_inst.read_mem(256 * (16 * offset + length), 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset,
length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
yield clk.posedge
print("test 6: various reads")
current_test.next = 6
for length in range(1, 8):
for offset in range(4):
wb_master_inst.init_read(256 * (16 * offset + length) + offset,
length)
yield wb_master_inst.wait()
yield clk.posedge
data = wb_master_inst.get_read_data()
assert data[0] == 256 * (16 * offset + length) + offset
assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
raise StopSimulation
return wb_master_logic, wb_ram_port0, clkgen, check
def bench():
# Parameters
DATA_WIDTH = 32
ADDR_WIDTH = 32
SELECT_WIDTH = 4
# Inputs
wbm_clk = Signal(bool(0))
wbm_rst = Signal(bool(0))
wbs_clk = Signal(bool(0))
wbs_rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
wbm_adr_i = Signal(intbv(0)[ADDR_WIDTH:])
wbm_dat_i = Signal(intbv(0)[DATA_WIDTH:])
wbm_we_i = Signal(bool(0))
wbm_sel_i = Signal(intbv(0)[SELECT_WIDTH:])
wbm_stb_i = Signal(bool(0))
wbm_cyc_i = Signal(bool(0))
wbs_dat_i = Signal(intbv(0)[DATA_WIDTH:])
wbs_ack_i = Signal(bool(0))
wbs_err_i = Signal(bool(0))
wbs_rty_i = Signal(bool(0))
# Outputs
wbm_dat_o = Signal(intbv(0)[DATA_WIDTH:])
wbm_ack_o = Signal(bool(0))
wbm_err_o = Signal(bool(0))
wbm_rty_o = Signal(bool(0))
wbs_adr_o = Signal(intbv(0)[ADDR_WIDTH:])
wbs_dat_o = Signal(intbv(0)[DATA_WIDTH:])
wbs_we_o = Signal(bool(0))
wbs_sel_o = Signal(intbv(0)[SELECT_WIDTH:])
wbs_stb_o = Signal(bool(0))
wbs_cyc_o = Signal(bool(0))
# WB master
wbm_inst = wb.WBMaster()
wbm_logic = wbm_inst.create_logic(wbm_clk,
adr_o=wbm_adr_i,
dat_i=wbm_dat_o,
dat_o=wbm_dat_i,
we_o=wbm_we_i,
sel_o=wbm_sel_i,
stb_o=wbm_stb_i,
ack_i=wbm_ack_o,
cyc_o=wbm_cyc_i,
name='master')
# WB RAM model
wb_ram_inst = wb.WBRam(2**16)
wb_ram_port0 = wb_ram_inst.create_port(wbs_clk,
adr_i=wbs_adr_o,
dat_i=wbs_dat_o,
dat_o=wbs_dat_i,
we_i=wbs_we_o,
sel_i=wbs_sel_o,
stb_i=wbs_stb_o,
ack_o=wbs_ack_i,
cyc_i=wbs_cyc_o,
latency=1,
async=False,
name='slave')
# DUT
dut = dut_wb_async_reg(wbm_clk, wbm_rst, wbs_clk, wbs_rst, current_test,
wbm_adr_i, wbm_dat_i, wbm_dat_o, wbm_we_i,
wbm_sel_i, wbm_stb_i, wbm_ack_o, wbm_err_o,
wbm_rty_o, wbm_cyc_i, wbs_adr_o, wbs_dat_i,
wbs_dat_o, wbs_we_o, wbs_sel_o, wbs_stb_o,
wbs_ack_i, wbs_err_i, wbs_rty_i, wbs_cyc_o)
@always(delay(4))
def wbm_clkgen():
wbm_clk.next = not wbm_clk
@always(delay(5))
def wbs_clkgen():
wbs_clk.next = not wbs_clk
@instance
def check():
yield delay(100)
yield wbm_clk.posedge
wbm_rst.next = 1
wbs_rst.next = 1
yield wbm_clk.posedge
yield wbm_clk.posedge
yield wbm_clk.posedge
wbm_rst.next = 0
wbs_rst.next = 0
yield wbm_clk.posedge
yield delay(100)
yield wbm_clk.posedge
yield wbm_clk.posedge
print("test 1: write")
current_test.next = 1
wbm_inst.init_write(4, b'\x11\x22\x33\x44')
yield wbm_inst.wait()
yield wbm_clk.posedge
data = wb_ram_inst.read_mem(0, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(4, 4) == b'\x11\x22\x33\x44'
yield delay(100)
yield wbm_clk.posedge
print("test 2: read")
current_test.next = 2
wbm_inst.init_read(4, 4)
yield wbm_inst.wait()
yield wbm_clk.posedge
data = wbm_inst.get_read_data()
assert data[0] == 4
assert data[1] == b'\x11\x22\x33\x44'
yield delay(100)
yield wbm_clk.posedge
print("test 3: various writes")
current_test.next = 3
for length in range(1, 8):
for offset in range(4):
wbm_inst.init_write(
256 * (16 * offset + length) + offset,
b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length])
yield wbm_inst.wait()
yield wbm_clk.posedge
data = wb_ram_inst.read_mem(256 * (16 * offset + length), 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert wb_ram_inst.read_mem(
256 * (16 * offset + length) + offset,
length) == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
yield wbm_clk.posedge
print("test 4: various reads")
current_test.next = 4
for length in range(1, 8):
for offset in range(4):
wbm_inst.init_read(256 * (16 * offset + length) + offset,
length)
yield wbm_inst.wait()
yield wbm_clk.posedge
data = wbm_inst.get_read_data()
assert data[0] == 256 * (16 * offset + length) + offset
assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
yield delay(100)
raise StopSimulation
return dut, wbm_logic, wb_ram_port0, wbm_clkgen, wbs_clkgen, check
