def check_iCEcube(self): iCEcube_path = self.flow_options.get("icecube_path") if xTools.not_exists(iCEcube_path, "iCEcube path"): return 1 self.ice_root_path = iCEcube_path self.ice_opt_path = xTools.win2unix( os.path.join(iCEcube_path, "sbt_backend", "bin", "win32", "opt")) self.lse_exe = xTools.win2unix( os.path.join(iCEcube_path, "LSE", "bin", "nt", "synthesis.exe")) self.synpwrap_exe = xTools.win2unix( os.path.join(self.ice_opt_path, "synpwrap", "synpwrap.exe")) os.environ["FOUNDRY"] = xTools.win2unix( os.path.join(iCEcube_path, "LSE")) os.environ["SYNPLIFY_PATH"] = xTools.win2unix( os.path.join(iCEcube_path, "synpbase"))
def run_synplify_flow(self, src_files, kwargs): if not self.run_synthesis: return kwargs["source_files"] = self.get_synp_source_files(src_files) if self.inc_path: _inc_path = xTools.to_abs_list(self.inc_path, self.src_design) else: _inc_path = list() _inc_path.append(xTools.win2unix(os.getcwd())) kwargs["search_path"] = "{%s}" % ";".join(_inc_path) if self.top_module: _tm = 'set_option -top_module "%s"' % self.top_module else: _tm = '' kwargs["top_module"] = _tm prj_template = os.path.join(self.conf, "synthesis", "run_synplify.prj") if xTools.not_exists(prj_template, "Synplify Project Template"): return 1 synplify_prj_file = "run_synplify.prj" xTools.generate_file(synplify_prj_file, prj_template, kwargs) synplify_cmd = 'synpwrap -prj "%s"' % synplify_prj_file sts = xTools.run_command(synplify_cmd, "my_run_synplify.log", "my_run_synplify.time") return sts
def run_check_flow(self): # // run check flow always! report_path = self.scripts_options.get("cwd") #if(os.path.abspath(report_path) == os.path.abspath(self.job_dir)):# update by Yzhao1 # report_path = os.path.join(self.job_dir,self.design) if not self.check_rpt: report = "check_flow.csv" else: _check_rpt = xTools.get_abs_path(self.check_rpt, report_path) report_path, report = os.path.split(_check_rpt) check_py = os.path.join(os.path.dirname(__file__), '..', '..', 'tools', 'check', "check.py") check_py = os.path.abspath(check_py) if xTools.not_exists(check_py, "source script file"): return 1 cmd_kwargs = dict() cmd_kwargs["top_dir"] = "--top-dir=%s" % self.job_dir cmd_kwargs["design"] = "--design=%s" % self.design _check_conf = self.scripts_options.get("check_conf") if _check_conf: cmd_kwargs["conf_file"] = "--conf-file=%s" % _check_conf else: cmd_kwargs["conf_file"] = "" cmd_kwargs["report_path"] = "--report-path=%s" % report_path cmd_kwargs["tag"] = "--tag=%s" % self.tag cmd_kwargs["report"] = "--report=%s" % report cmd_kwargs["rerun_path"] = "--rerun-path=%s" % report_path # NEW check flow if self.scripts_options.get("synthesis_only"): _ = self.scripts_options.get("synthesis") if _ == "lse": cmd_kwargs["lse_check"] = "--lse-check" else: cmd_kwargs["synp_check"] = "--synp-check" else: for _ in ("run_par_trace", "run_par", "pushbutton"): if self.scripts_options.get(_): if self.scripts_options.get( "till_map"): # till map has higher priority pass else: cmd_kwargs["partrce_check"] = "--partrce-check" else: for _ in ("run_map", "till_map", "run_map_trace"): if self.scripts_options.get(_): cmd_kwargs["map_check"] = "--map-check" # cmd_line = r"%s %s " % (sys.executable, check_py) for key, value in cmd_kwargs.items(): cmd_line += " %s " % value cmd_line = xTools.win2unix(cmd_line, 0) xTools.say_it(" Launching %s" % cmd_line) sts, text = xTools.get_status_output(cmd_line) xTools.say_it(text) return sts
def create_sim_lib_path(self): diamond_version = xLattice.get_diamond_version() ver_name = "Diamond" + "".join(diamond_version) self.sim_name = self.family if self.hdl_type == "verilog": self.sim_name = "ovi_" + self.sim_name real_path = os.path.join(self.root_lib_path, self.sim_vendor_name, ver_name, self.sim_name) self.sim_lib_path = xTools.win2unix(real_path, 0)
def get_file_list(section_case, src_design): # say_it(section_case, "Section Case:") _file_list = section_case.get("file list") _file_list = re.split(",", _file_list) _file_list = [item.strip() for item in _file_list] file_list = list() tb_file = "" uut_name = "" p_tb = re.compile("(\w+)_tb$", re.I) for item in _file_list: fname = get_fname(item) fext = get_fext_lower(item) item = win2unix(item, 0) m_tb = p_tb.search(fname) if m_tb: tb_file = item continue if fext in (".v", ".vhd", ".sv"): file_list.append(item) else: say_it("Warning. %s found in _qas.info" % item) if tb_file: new_tb_file = get_relative_path(tb_file, src_design) if not os.path.isfile(new_tb_file): say_it("-Error. Not found testbench file: %s" % tb_file) else: base_module_name = "" for item in ("module", "project"): base_module_name = section_case.get(item) if base_module_name: break if not base_module_name: say_it("Error. Not found base module name") return tb_file, file_list, uut_name p_uut_name_verilog = re.compile("%s\s+(\w+)" % base_module_name) # add_16_SIGNED post( p_uut_name_vhdl = re.compile("(\S+)\s*:\s*%s" % base_module_name) # uut: mac_ecp4_m5678_09x09_ir_or_dc_mclk_up PORT MAP( fext = get_fext_lower(new_tb_file) if fext == ".v": matched_uut_name = simple_parser(new_tb_file, [ p_uut_name_verilog, ]) else: matched_uut_name = simple_parser(new_tb_file, [ p_uut_name_vhdl, ]) if not matched_uut_name: say_it("-Warning. can not find uut name in %s" % tb_file) else: uut_name = matched_uut_name[1].group(1) return tb_file, file_list, uut_name
def __init__(self, diamond_path, sim_vendor_name, sim_bin_path, hdl_type, family, root_lib_path): """ hdl_type: verilog or vhdl """ self.diamond_path = diamond_path self.sim_vendor_name = sim_vendor_name self.sim_bin_path = xTools.win2unix(sim_bin_path, 0) self.hdl_type = hdl_type self.family = family self.root_lib_path = root_lib_path self.sim_lib_name = ""
def create_dev_xml_file(self): xml_file = xTools.win2unix(self.xml_file) xml_path = os.path.dirname(xml_file) recov = xTools.ChangeDir(xml_path) sts = xTools.run_safety(create_diamond_dev_xml, xml_file) while True: if not os.path.isfile(xTools.LOCK_FILE): break try: os.remove(xTools.LOCK_FILE) break except OSError: xTools.say_it("Try to remove %s in %s" % (xTools.LOCK_FILE, os.getcwd())) time.sleep(3) recov.comeback() return sts
def run_lse_flow(self, src_files, kwargs): synthesis_cmd = self.section_cmd.get("synthesis") new_src_files = self.get_lse_source_files(src_files) if not self.run_synthesis: return if synthesis_cmd: sts, lse_cmd = xTools.get_cmd(synthesis_cmd, dict(src_files=new_src_files)) if sts: return 1 # sometimes the user do NOT use -f for specify the source files lse_cmd = re.sub("\s+", " ", lse_cmd) sts = xTools.run_command(lse_cmd, "my_run_lse.log", "my_run_lse.time") return sts # --------------------- if not self.synp_goal: self.synp_goal = "Timing" else: self.synp_goal = self.synp_goal.capitalize() kwargs["goal"] = self.synp_goal _tm = "" if self.top_module: _tm = "-top %s" % self.top_module kwargs["top_module"] = _tm if self.inc_path: _inc_path = xTools.to_abs_list(self.inc_path, self.src_design) else: _inc_path = list() _inc_path.append(xTools.win2unix(os.getcwd())) kwargs["search_path"] = '"%s"' % '" '.join(_inc_path) kwargs["source_files"] = new_src_files synproj_template = os.path.join(self.conf, "synthesis", "run_lse.synproj") if xTools.not_exists(synproj_template, "LSE Project Template"): return 1 lse_synproj_file = "run_lse.synproj" xTools.generate_file(lse_synproj_file, synproj_template, kwargs) lse_cmd = "synthesis -f %s" % lse_synproj_file sts = xTools.run_command(lse_cmd, "my_run_lse.log", "my_run_lse.time") return sts
def add_vlog_vcom_lines(self, src_files, add_tb=0): self.use_vhd = 0 if add_tb and not self.normal_tb: # use them directly. v_v_lines = src_files[:] else: v_v_lines = list() for item in src_files: fext = xTools.get_fext_lower(item) item = xTools.win2unix(item, 0) if fext in (".v", ".vo", ".sv"): v_v_lines.append("vlog %s" % item) elif fext in (".vho", ".vhd", ".vhdl"): v_v_lines.append("vcom %s" % item) if not self.use_vhd: self.use_vhd = 1 elif fext == ".lpf": continue else: xTools.say_it("-Warning. Unknown file: %s" % item) continue return v_v_lines
def process(self): sim_vendor_bin = os.getenv("SIM_VENDOR_BIN") if xTools.not_exists(sim_vendor_bin, "Simulation tool bin path"): return 1 self.sim_vendor_bin = xTools.win2unix(sim_vendor_bin) if self.flatten_options(): # ///////////////// # do the implementation flow pass # return 1 # #run Your PUSHBUTTON FLOW firstly user_options = self.get_user_options() sts = 0 task_list = xLattice.get_task_list(self.flow_options, user_options) if task_list: # sts = xLattice.run_ldf_file("run_firstly.tcl", self.final_ldf_file, task_list) # updated for new log name sts = xLattice.run_ldf_file("foundry_flow.tcl", self.final_ldf_file, task_list) if sts: xTools.say_it( "-Warning. errors found in normal implementation flow") for (sim_type, sim_path, sim_func) in ( (self.sim_rtl, "sim_rtl", self.run_rtl_simulation), (self.sim_syn_vhd, "sim_syn_vhd", self.run_syn_vhd_simulation), (self.sim_syn_vlg, "sim_syn_vlg", self.run_syn_vlg_simulation), (self.sim_map_vhd, "sim_map_vhd", self.run_map_vhd_simulation), (self.sim_map_vlg, "sim_map_vlg", self.run_map_vlg_simulation), (self.sim_par_vhd, "sim_par_vhd", self.run_par_vhd_simulation), (self.sim_par_vlg, "sim_par_vlg", self.run_par_vlg_simulation), ): if sim_type: sts = sim_func(sim_path) if self.run_simrel: sts = self.run_simrel_flow() return sts
def _run_simulation(self, sim_path, source_files, user_options): if xTools.wrap_md(sim_path, "Simulation Path"): return 1 _recov = xTools.ChangeDir(sim_path) if self.copy_tb_files(""): _recov.comeback() return 1 use_source_do_file = 0 if not user_options: # rtl simulation if self.others_path: self.copy_other_files() src_lines = xTools.get_content_in_start_end( self.do_template, self.p_src_start, self.p_src_end) for src in src_lines: if re.search("(vlog|vcom)", src): use_source_do_file = 1 do_lines = list() need_remove_ovi = 0 if use_source_do_file: # modify do file and use it! start_source = 0 start_tb = 0 for line in open(self.do_template): line = line.rstrip() m_src_start = self.p_src_start.search(line) m_src_end = self.p_src_end.search(line) m_tb_start = self.p_tb_start.search(line) m_tb_end = self.p_tb_end.search(line) if not start_source: start_source = m_src_start if m_src_end: start_source = 0 if not start_tb: start_tb = m_tb_start if m_tb_end: start_tb = 0 if not (start_source or start_tb): do_lines.append(line) elif start_source or start_tb: new_line = get_new_real_path(self.do_template, line) if start_source: line_list = re.split("\s+", line.strip()) if line_list[0] in ("vlog", "vcom"): hdl_file = line_list[-1] real_hdl_file = xTools.get_relative_path( hdl_file, os.getcwd()) if not os.path.isfile(real_hdl_file): real_hdl_file = xTools.get_relative_path( hdl_file, os.path.join("../../sim")) if not os.path.isfile(real_hdl_file): pass else: modified, real_hdl_file = get_real_hdl_file( real_hdl_file, self.run_scuba) cur_fext = xTools.get_fext_lower(real_hdl_file) if modified: if cur_fext == ".vhd": line_list = ["vcom", ""] else: line_list = ["vlog", ""] line_list[-1] = real_hdl_file if not need_remove_ovi: if xTools.get_fext_lower( real_hdl_file) in (".vho", ".vhd", ".vhdl"): need_remove_ovi = 1 new_line = " ".join(line_list) do_lines.append(new_line) else: start_source = start_tb = 0 for line in open(self.do_template): line = line.rstrip() if re.search("%", line): line = line % self.do_args do_lines.append(line) continue if start_source: if self.p_src_end.search(line): if not user_options: # RTL simulation source_files = [ xTools.get_relative_path( item, self.dst_design) for item in source_files ] v_v_line = self.add_vlog_vcom_lines(source_files) if not v_v_line: xTools.say_it( "Error. Not any source files for running %s" % sim_path) xTools.say_it("") _recov.comeback() return 1 need_remove_ovi = self.use_vhd do_lines += v_v_line[:] start_source = 0 do_lines.append(line) continue else: start_source = self.p_src_start.search(line) if start_source: do_lines.append(line) continue if start_tb: if self.p_tb_end.search(line): _kk = self.use_vhd v_v_line = self.add_vlog_vcom_lines( self.final_tb_files, add_tb=1) self.use_vhd = _kk do_lines += v_v_line[:] start_tb = 0 do_lines.append(line) continue else: start_tb = self.p_tb_start.search(line) if start_tb: do_lines.append(line) continue do_lines.append(line) do_file = "do_%s.do" % sim_path new_do_lines = list() lib_name = xTools.get_fname(self.dev_lib) if need_remove_ovi: lib_name = re.sub("ovi_", "", lib_name) p1 = re.compile("vmap\s+(\S+)\s+(\$dev_lib)") p2 = "" tmp_lib_name = "" for _ in do_lines: if p1: m1 = p1.search(_) if m1: p1 = "" p2 = re.compile("vsim.+\s+-L\s+%s" % m1.group(1)) tmp_lib_name = m1.group(1) _ = "vmap %s %s" % (lib_name, m1.group(2)) elif p2: m2 = p2.search(_) if m2: p2 = "" _ = re.sub("-L\s+%s" % tmp_lib_name, "-L %s" % lib_name, _) new_do_lines.append(_) xTools.write_file(do_file, new_do_lines) utils.update_simulation_do_file(self.sim_vendor_name, do_file, self.lst_precision) args = "%s %s %s cmd %s %s" % (do_file, self.dev_lib, self.pri_lib, self.diamond, self.src_lib) if self.run_modelsim or self.run_questasim: sim_cmd = '%s/vsim -l sim_log.txt -c -do "do %s"' % ( self.sim_vendor_bin, args) else: sim_cmd = "%s/vsimsa -l sim_log.txt -do %s" % (self.sim_vendor_bin, args) sim_cmd = xTools.win2unix(sim_cmd, 0) if need_remove_ovi: sim_cmd = re.sub("ovi_", "", sim_cmd) # /* # * If license not found, will launch again in 10 times. # */ log_file = "run_%s.log" % sim_path time_file = "run_%s.time" % sim_path sts = 0 for i in range(10): if xTools.remove_dir_without_error(log_file): _recov.comeback() return 1 sts = xTools.run_command(sim_cmd, log_file, time_file) if sts: if xTools.simple_parser( log_file, [re.compile("Unable to checkout a license")]): xTools.say_it( "Warning. No licence for running simulation. waiting ..." ) time.sleep(i * 10) else: break else: break dump_vcd_file() _recov.comeback() return sts
def flatten_options(self): foundry_path = os.getenv("FOUNDRY") if xTools.not_exists(foundry_path, "Foundry Path"): return 1 self.src_design = self.flow_options.get("src_design") self.dst_design = self.flow_options.get("dst_design") self.synthesis = self.flow_options.get("synthesis") if not self.synthesis: self.synthesis = "synplify" self.sim_rtl = xTools.get_true(self.flow_options, "sim_rtl") self.sim_syn_vlg = xTools.get_true(self.flow_options, "sim_syn_vlg") self.sim_syn_vhd = xTools.get_true(self.flow_options, "sim_syn_vhd") self.sim_map_vlg = xTools.get_true(self.flow_options, "sim_map_vlg") self.sim_map_vhd = xTools.get_true(self.flow_options, "sim_map_vhd") self.sim_par_vlg = xTools.get_true(self.flow_options, "sim_par_vlg") self.sim_par_vhd = xTools.get_true(self.flow_options, "sim_par_vhd") self.sim_all = xTools.get_true(self.flow_options, "sim_all") self.simrel_path = self.flow_options.get("simrel_path") self.run_simrel = self.flow_options.get("run_simrel") self.pmi = xTools.get_true(self.flow_options, "pmi") self.lst_precision = self.flow_options.get("lst_precision") if self.sim_all: self.sim_rtl = self.sim_map_vhd = self.sim_map_vlg = self.sim_par_vhd = self.sim_par_vlg = 1 self.sim_syn_vlg = 1 if self.sim_syn_vlg: self.sim_syn_vhd = 0 others_path = self.flow_options.get("others_path") if others_path: others_path = os.path.join(self.src_design, others_path) if os.path.isdir(others_path): self.others_path = others_path else: self.others_path = "" sim_section = self.flow_options.get("sim") if not sim_section: xTools.say_it("-Error. Not any simulation settings found.") return 1 self.dev_lib = sim_section.get("dev_lib") self.pri_lib = sim_section.get("pri_lib") self.src_lib = sim_section.get("src_lib") diamond = os.path.dirname(foundry_path) self.diamond = diamond = xTools.win2unix(diamond) if self.pri_lib: self.pri_lib = re.sub('\$diamond', diamond, xTools.win2unix(self.pri_lib, 0)) else: self.pri_lib = "work" if self.src_lib: self.src_lib = re.sub('\$diamond', diamond, xTools.win2unix(self.src_lib, 0)) else: self.src_lib = "" self.tb_file = sim_section.get("tb_file") self.tb_vector = sim_section.get("tb_vector") self.sim_top = sim_section.get("sim_top") if not self.sim_top: self.sim_top = "sim_top" self.src_top_module = sim_section.get("src_top_module") if not self.src_top_module: self.src_top_module = self.sim_top self.uut_name = sim_section.get("uut_name") self.resolution = sim_section.get("resolution") if not self.uut_name: self.uut_name = "UUT" self.sim_time = sim_section.get("sim_time") self.do_msim = sim_section.get("do_msim") self.do_qsim = sim_section.get("do_qsim") self.do_ahdl = sim_section.get("do_asim") self.do_riviera = sim_section.get("do_rsim") _conf = self.flow_options.get("conf") if not self.do_msim: self.do_msim = os.path.join(_conf, "sim", "msim_do.template") if not self.do_qsim: self.do_qsim = os.path.join(_conf, "sim", "qsim_do.template") if not self.do_riviera: self.do_riviera = os.path.join(_conf, "sim", "rsim_do.template") if not self.do_ahdl: if self.pmi: self.do_ahdl = os.path.join(_conf, "sim", "pmi_ahdl.template") else: self.do_ahdl = os.path.join(_conf, "sim", "ahdl_do.template") self.run_modelsim = xTools.get_true(self.flow_options, "run_modelsim") self.run_questasim = xTools.get_true(self.flow_options, "run_questasim") self.run_riviera = xTools.get_true(self.flow_options, "run_riviera") if self.run_modelsim: self.do_template = self.do_msim self.sim_vendor_name = "Modelsim" elif self.run_questasim: self.do_template = self.do_qsim self.sim_vendor_name = "QuestaSim" elif self.run_riviera: self.do_template = self.do_riviera self.sim_vendor_name = "Riviera" else: self.do_template = self.do_ahdl self.sim_vendor_name = "Active" if not os.path.isfile(self.do_template): self.do_template = xTools.get_abs_path(self.do_template, self.src_design) if xTools.not_exists(self.do_template, "DO Template File"): return 1 bali_node = self.final_ldf_dict.get("bali") impl_node = self.final_ldf_dict.get("impl") # ------------- # Fix bugs for getting impl name #<BaliProject version="3.2" title="top" device="LFE5UM-85F-6MG285C" default_implementation="DV100V1"> #<Options/> # <Implementation title="DV100V1" dir="Video" description="Video" synthesis="synplify" default_strategy="Video_timing"> self.impl_name = bali_node.get("default_implementation") self.impl_dir = impl_node.get("dir") if not self.impl_dir: self.impl_dir = self.impl_name # self.project_name = bali_node.get("title") # device = bali_node.get("device") big_version, small_version = xLattice.get_diamond_version() xml_file = os.path.join( _conf, "DiamondDevFile_%s%s.xml" % (big_version, small_version)) self.devkit_parser = xLatticeDev.DevkitParser(xml_file) if self.devkit_parser.process(): return 1 std_devkit = self.devkit_parser.get_std_devkit(device) if not std_devkit: xTools.say_it("Error. Unknown device %s" % device) return 1 family_name = std_devkit.get("family") conf_file = os.path.join(_conf, "sim", "map_lib.ini") if xTools.not_exists(conf_file, "Simulation Library Pairs File"): return 1 sts, raw_lib_dict = xTools.get_conf_options(conf_file) if sts: return 1 my_dict = raw_lib_dict.get("family_map_sim_lib") fam_lower = family_name.lower() map_lib_name = my_dict.get(fam_lower) if not map_lib_name: map_lib_name = fam_lower xTools.say_it("Message: Use map lib name: %s" % fam_lower) if self.dev_lib: map_lib_name = self.dev_lib map_lib_name = re.sub("ovi_", "", map_lib_name) else: if self.run_modelsim or self.run_questasim or self.run_riviera: self.create_dev_lib(map_lib_name) else: self.dev_lib = os.path.join(foundry_path, "..", "active-hdl", "Vlib", "ovi_" + map_lib_name, "ovi_" + map_lib_name + ".lib") self.dev_lib = os.path.abspath(self.dev_lib) # self.pri_lib = "work" self.do_args = dict() self.do_args["sim_top"] = self.sim_top self.do_args["src_top_module"] = self.src_top_module self.do_args["uut_name"] = self.uut_name self.do_args["lib_name"] = "ovi_" + map_lib_name self.do_args["dev_name"] = map_lib_name self.do_args["diamond"] = os.path.dirname( foundry_path ) # On Linux, ENV-KEY FOUNDRY and foundry are different if self.resolution: self.do_args["resolution"] = "-t %s" % self.resolution else: self.do_args["resolution"] = "" if self.sim_time: _sim_time = self.sim_time else: _sim_time = "10 us" self.do_args["sim_time"] = _sim_time
def prepare_kwargs(self): self.conf = self.flow_options.get("conf") same_ldf_dir = self.flow_options.get("same_ldf_dir") use_ice_prj = self.flow_options.get("use_ice_prj") self.kwargs = dict() if use_ice_prj: _project = self.flow_options.get("Project") implmnt_path = _project.get("Implementations") if not implmnt_path: xTools.say_it( "-Error. Not found Implementations in project file") return 1 self.kwargs["ProjectName"] = _project.get("ProjectName", "DEF_PRJ_NAME") self.kwargs["implmnt_path"] = implmnt_path _src_files = _project.get("ProjectVFiles") _sdc_file = _project.get("ProjectCFiles") if _sdc_file: _sdc_file = xTools.get_relative_path(_sdc_file, same_ldf_dir) sdc_file = self.flow_options.get("sdc_file") ldc_file = self.flow_options.get("ldc_file") if sdc_file: sdc_file = xTools.get_relative_path(sdc_file, same_ldf_dir) if ldc_file: ldc_file = xTools.get_relative_path(ldc_file, same_ldf_dir) _src_files = re.split(",", _src_files) _src_files = [re.sub("=\w+", "", item) for item in _src_files] _src_files = [[xTools.get_relative_path(item, same_ldf_dir)] for item in _src_files] ##################### _implmnt = self.flow_options.get(implmnt_path) if not _implmnt: xTools.say_it("Error. Not found section: %s" % implmnt_path) return 1 self.kwargs["DeviceFamily"] = _implmnt.get("DeviceFamily") self.kwargs["Device"] = _implmnt.get("Device") self.kwargs["DevicePackage"] = _implmnt.get("DevicePackage") else: _devkit = self.flow_options.get("devkit") _top_name = self.flow_options.get("top_module") _src_files = self.flow_options.get("src_files") _sdc_file = "" for item in _src_files: fext = xTools.get_fext_lower(item) if fext == ".sdc": _sdc_file = item break sdc_file = self.flow_options.get("sdc_file") ldc_file = self.flow_options.get("ldc_file") if sdc_file: sdc_file = xTools.get_relative_path(sdc_file, same_ldf_dir) if ldc_file: ldc_file = xTools.get_relative_path(ldc_file, same_ldf_dir) _src_files = [[xTools.get_relative_path(item, same_ldf_dir)] for item in _src_files] implmnt_path = _top_name + "_Implmnt" _implmnt = dict() self.kwargs["ProjectName"] = _top_name self.kwargs["implmnt_path"] = implmnt_path self.kwargs["source_files"] = _src_files _dev_list = re.split("\s*,\s*", _devkit) self.kwargs["DeviceFamily"], self.kwargs["Device"], self.kwargs[ "DevicePackage"] = _dev_list # -------------- self.synthesis = self.flow_options.get("synthesis") if not self.synthesis: self.synthesis = "synplify" if self.synthesis == "synplify": _source_files = super_run.get_synp_source_files(_src_files) if sdc_file: kk = sdc_file elif _sdc_file: kk = _sdc_file else: kk = "" if kk: sdc_file = "add_file -constraint %s" % kk else: sdc_file = "" else: _source_files = super_run.get_lse_source_files(_src_files) if ldc_file: sdc_file = "-sdc %s" % ldc_file else: sdc_file = "" self.kwargs["source_files"] = _source_files self.kwargs["sdc_file"] = sdc_file # -------------- _goal = self.flow_options.get("goal") _frequency = self.flow_options.get("frequency") if not _frequency: if self.synthesis == "lse": _frequency = 200 else: _frequency = "Auto" _mixed_drivers = xTools.get_true(self.flow_options, "mixed_drivers") if _mixed_drivers: _mixed_drivers = "-resolve_mixed_drivers 1" # For LSE else: _mixed_drivers = "" self.kwargs["mixed_drivers"] = _mixed_drivers if not _goal: _goal = "Timing" self.kwargs["goal"] = _goal self.kwargs["frequency"] = _frequency _DesignCell = _implmnt.get("DesignCell") if not _DesignCell: _DesignCell = self.kwargs["ProjectName"] self.kwargs["DesignCell"] = _DesignCell self.kwargs["cwd"] = xTools.win2unix(os.getcwd()) self.kwargs["ice_opt_path"] = self.ice_opt_path ice_map_file = os.path.join(self.conf, "ice_synthesis", "ice.map") sts, ice_map_options = xTools.get_conf_options(ice_map_file, key_lower=False) if sts: return sts _family = ice_map_options.get(self.kwargs.get("DeviceFamily")) if not _family: xTools.say_it("Warning. Not support Family: %s" % self.kwargs.get("DeviceFamily")) return 1 dev_lib = _family.get(self.kwargs.get("Device")) if not dev_lib: xTools.say_it("Warning. Not support %s" % self.kwargs.get("Device")) return 1 dev, lib = re.split("\s*,\s*", dev_lib) self.kwargs["dev_file"] = os.path.abspath( os.path.join(self.ice_root_path, "sbt_backend", "devices", dev)) self.kwargs["lib_file"] = xTools.win2unix( os.path.join(self.ice_root_path, "sbt_backend", "devices", lib)) # create dir _sbt_path = os.path.join(os.getcwd(), implmnt_path, "sbt") for item in ("bitmap", "gui", "netlister", "packer", "placer", "router", "simulation_netlist", "timer"): tt = os.path.join(_sbt_path, "outputs", item) xTools.wrap_md(tt, "ice results path") for item in ("netlist", "sds"): tt = os.path.join(_sbt_path, "outputs", item) xTools.wrap_md(tt, "ice results path") self.kwargs["sdc_translator"] = os.path.abspath( os.path.join(self.ice_root_path, r"sbt_backend\bin\sdc_translator.tcl")) info_line = "%s%s-%s" % (self.kwargs["DeviceFamily"], self.kwargs["Device"], self.kwargs["DevicePackage"]) xTools.append_file( os.path.join(_sbt_path, "outputs", "device_info.txt"), info_line, False) tool_options = self.flow_options.get("tool options", dict()) _BitmapInitRamBank = tool_options.get("BitmapInitRamBank") if not _BitmapInitRamBank: _BitmapInitRamBank = "1111" self.kwargs["BitmapInitRamBank"] = _BitmapInitRamBank