class BaseBus(MemObject): type = 'BaseBus' abstract = True slave = VectorSlavePort("vector port for connecting masters") master = VectorMasterPort("vector port for connecting slaves") # Override the default clock clock = '1GHz' header_cycles = Param.Cycles(1, "cycles of overhead per transaction") width = Param.Unsigned(8, "bus width (bytes)") block_size = Param.Unsigned(64, "The default block size if not set by " \ "any connected module") # The default port can be left unconnected, or be used to connect # a default slave port default = MasterPort("Port for connecting an optional default slave") # The default port can be used unconditionally, or based on # address range, in which case it may overlap with other # ports. The default range is always checked first, thus creating # a two-level hierarchical lookup. This is useful e.g. for the PCI # bus configuration. use_default_range = Param.Bool(False, "Perform address mapping for " \ "the default port") #TLB move to memory-side// if buildEnv['TARGET_ISA'] == 'alpha': dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") interrupts = Param.AlphaInterrupts( NULL, "Interrupt Controller")
class BaseCPU(MemObject): type = 'BaseCPU' abstract = True cxx_header = "cpu/base.hh" @classmethod def export_methods(cls, code): code(''' void switchOut(); void takeOverFrom(BaseCPU *cpu); bool switchedOut(); void flushTLBs(); Counter totalInsts(); void scheduleInstStop(ThreadID tid, Counter insts, const char *cause); void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause); ''') @classmethod def memory_mode(cls): """Which memory mode does this CPU require?""" return 'invalid' @classmethod def require_caches(cls): """Does the CPU model require caches? Some CPU models might make assumptions that require them to have caches. """ return False @classmethod def support_take_over(cls): """Does the CPU model support CPU takeOverFrom?""" return False def takeOverFrom(self, old_cpu): self._ccObject.takeOverFrom(old_cpu._ccObject) system = Param.System(Parent.any, "system object") cpu_id = Param.Int(-1, "CPU identifier") socket_id = Param.Unsigned(0, "Physical Socket identifier") numThreads = Param.Unsigned(1, "number of HW thread contexts") function_trace = Param.Bool(False, "Enable function trace") function_trace_start = Param.Tick(0, "Tick to start function trace") checker = Param.BaseCPU(NULL, "checker CPU") do_checkpoint_insts = Param.Bool(True, "enable checkpoint pseudo instructions") do_statistics_insts = Param.Bool(True, "enable statistics pseudo instructions") profile = Param.Latency('0ns', "trace the kernel stack") do_quiesce = Param.Bool(True, "enable quiesce instructions") workload = VectorParam.Process([], "processes to run") if buildEnv['TARGET_ISA'] == 'sparc': dtb = Param.SparcTLB(SparcTLB(), "Data TLB") itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") interrupts = Param.SparcInterrupts(NULL, "Interrupt Controller") isa = VectorParam.SparcISA([isa_class()], "ISA instance") elif buildEnv['TARGET_ISA'] == 'alpha': dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") interrupts = Param.AlphaInterrupts(NULL, "Interrupt Controller") isa = VectorParam.AlphaISA([isa_class()], "ISA instance") elif buildEnv['TARGET_ISA'] == 'x86': dtb = Param.X86TLB(X86TLB(), "Data TLB") itb = Param.X86TLB(X86TLB(), "Instruction TLB") interrupts = Param.X86LocalApic(NULL, "Interrupt Controller") isa = VectorParam.X86ISA([isa_class()], "ISA instance") elif buildEnv['TARGET_ISA'] == 'mips': dtb = Param.MipsTLB(MipsTLB(), "Data TLB") itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") interrupts = Param.MipsInterrupts(NULL, "Interrupt Controller") isa = VectorParam.MipsISA([isa_class()], "ISA instance") elif buildEnv['TARGET_ISA'] == 'arm': dtb = Param.ArmTLB(ArmTLB(), "Data TLB") itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans") dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans") interrupts = Param.ArmInterrupts(NULL, "Interrupt Controller") isa = VectorParam.ArmISA([isa_class()], "ISA instance") elif buildEnv['TARGET_ISA'] == 'power': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") dtb = Param.PowerTLB(PowerTLB(), "Data TLB") itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") interrupts = Param.PowerInterrupts(NULL, "Interrupt Controller") isa = VectorParam.PowerISA([isa_class()], "ISA instance") else: print "Don't know what TLB to use for ISA %s" % \ buildEnv['TARGET_ISA'] sys.exit(1) max_insts_all_threads = Param.Counter( 0, "terminate when all threads have reached this inst count") max_insts_any_thread = Param.Counter( 0, "terminate when any thread reaches this inst count") simpoint_start_insts = VectorParam.Counter( [], "starting instruction counts of simpoints") max_loads_all_threads = Param.Counter( 0, "terminate when all threads have reached this load count") max_loads_any_thread = Param.Counter( 0, "terminate when any thread reaches this load count") progress_interval = Param.Frequency( '0Hz', "frequency to print out the progress message") switched_out = Param.Bool(False, "Leave the CPU switched out after startup (used when switching " \ "between CPU models)") tracer = Param.InstTracer(default_tracer, "Instruction tracer") icache_port = MasterPort("Instruction Port") dcache_port = MasterPort("Data Port") _cached_ports = ['icache_port', 'dcache_port'] if buildEnv['TARGET_ISA'] in ['x86', 'arm']: _cached_ports += ["itb.walker.port", "dtb.walker.port"] _uncached_slave_ports = [] _uncached_master_ports = [] if buildEnv['TARGET_ISA'] == 'x86': _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"] _uncached_master_ports += ["interrupts.int_master"] def createInterruptController(self): if buildEnv['TARGET_ISA'] == 'sparc': self.interrupts = SparcInterrupts() elif buildEnv['TARGET_ISA'] == 'alpha': self.interrupts = AlphaInterrupts() elif buildEnv['TARGET_ISA'] == 'x86': self.apic_clk_domain = DerivedClockDomain( clk_domain=Parent.clk_domain, clk_divider=16) self.interrupts = X86LocalApic(clk_domain=self.apic_clk_domain, pio_addr=0x2000000000000000) _localApic = self.interrupts elif buildEnv['TARGET_ISA'] == 'mips': self.interrupts = MipsInterrupts() elif buildEnv['TARGET_ISA'] == 'arm': self.interrupts = ArmInterrupts() elif buildEnv['TARGET_ISA'] == 'power': self.interrupts = PowerInterrupts() else: print "Don't know what Interrupt Controller to use for ISA %s" % \ buildEnv['TARGET_ISA'] sys.exit(1) def connectCachedPorts(self, bus): for p in self._cached_ports: exec('self.%s = bus.slave' % p) def connectUncachedPorts(self, bus): for p in self._uncached_slave_ports: exec('self.%s = bus.master' % p) for p in self._uncached_master_ports: exec('self.%s = bus.slave' % p) def connectAllPorts(self, cached_bus, uncached_bus=None): self.connectCachedPorts(cached_bus) if not uncached_bus: uncached_bus = cached_bus self.connectUncachedPorts(uncached_bus) def addPrivateSplitL1Caches(self, ic, dc, iwc=None, dwc=None): self.icache = ic self.dcache = dc self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] # AK: Add nvwrite side to icache and dcache self._uncached_master_ports = [ 'icache.nvwrite_side', 'dcache.nvwrite_side' ] if buildEnv['TARGET_ISA'] in ['x86', 'arm']: if iwc and dwc: self.itb_walker_cache = iwc self.dtb_walker_cache = dwc self.itb.walker.port = iwc.cpu_side self.dtb.walker.port = dwc.cpu_side self._cached_ports += ["itb_walker_cache.mem_side", \ "dtb_walker_cache.mem_side"] else: self._cached_ports += ["itb.walker.port", "dtb.walker.port"] # Checker doesn't need its own tlb caches because it does # functional accesses only if self.checker != NULL: self._cached_ports += ["checker.itb.walker.port", \ "checker.dtb.walker.port"] def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None): self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) self.toL2Bus = L2XBar() self.connectCachedPorts(self.toL2Bus) self.l2cache = l2c self.toL2Bus.master = self.l2cache.cpu_side self._cached_ports = ['l2cache.mem_side'] def createThreads(self): self.isa = [isa_class() for i in xrange(self.numThreads)] if self.checker != NULL: self.checker.createThreads() def addCheckerCpu(self): pass
class BaseCPU(MemObject): type = 'BaseCPU' abstract = True cxx_header = "cpu/base.hh" cxx_exports = [ PyBindMethod("switchOut"), PyBindMethod("takeOverFrom"), PyBindMethod("switchedOut"), PyBindMethod("flushTLBs"), PyBindMethod("totalInsts"), PyBindMethod("scheduleInstStop"), PyBindMethod("scheduleLoadStop"), PyBindMethod("getCurrentInstCount"), ] @classmethod def memory_mode(cls): """Which memory mode does this CPU require?""" return 'invalid' @classmethod def require_caches(cls): """Does the CPU model require caches? Some CPU models might make assumptions that require them to have caches. """ return False @classmethod def support_take_over(cls): """Does the CPU model support CPU takeOverFrom?""" return False def takeOverFrom(self, old_cpu): self._ccObject.takeOverFrom(old_cpu._ccObject) system = Param.System(Parent.any, "system object") cpu_id = Param.Int(-1, "CPU identifier") socket_id = Param.Unsigned(0, "Physical Socket identifier") numThreads = Param.Unsigned(1, "number of HW thread contexts") pwr_gating_latency = Param.Cycles( 300, "Latency to enter power gating state when all contexts are suspended") power_gating_on_idle = Param.Bool(False, "Control whether the core goes "\ "to the OFF power state after all thread are disabled for "\ "pwr_gating_latency cycles") function_trace = Param.Bool(False, "Enable function trace") function_trace_start = Param.Tick(0, "Tick to start function trace") checker = Param.BaseCPU(NULL, "checker CPU") syscallRetryLatency = Param.Cycles(10000, "Cycles to wait until retry") do_checkpoint_insts = Param.Bool(True, "enable checkpoint pseudo instructions") do_statistics_insts = Param.Bool(True, "enable statistics pseudo instructions") profile = Param.Latency('0ns', "trace the kernel stack") do_quiesce = Param.Bool(True, "enable quiesce instructions") wait_for_remote_gdb = Param.Bool(False, "Wait for a remote GDB connection") workload = VectorParam.Process([], "processes to run") if buildEnv['TARGET_ISA'] == 'sparc': dtb = Param.SparcTLB(SparcTLB(), "Data TLB") itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") interrupts = VectorParam.SparcInterrupts([], "Interrupt Controller") isa = VectorParam.SparcISA([], "ISA instance") elif buildEnv['TARGET_ISA'] == 'alpha': dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") interrupts = VectorParam.AlphaInterrupts([], "Interrupt Controller") isa = VectorParam.AlphaISA([], "ISA instance") elif buildEnv['TARGET_ISA'] == 'x86': dtb = Param.X86TLB(X86TLB(), "Data TLB") itb = Param.X86TLB(X86TLB(), "Instruction TLB") interrupts = VectorParam.X86LocalApic([], "Interrupt Controller") isa = VectorParam.X86ISA([], "ISA instance") elif buildEnv['TARGET_ISA'] == 'mips': dtb = Param.MipsTLB(MipsTLB(), "Data TLB") itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") interrupts = VectorParam.MipsInterrupts([], "Interrupt Controller") isa = VectorParam.MipsISA([], "ISA instance") elif buildEnv['TARGET_ISA'] == 'arm': dtb = Param.ArmTLB(ArmTLB(), "Data TLB") itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans") dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans") interrupts = VectorParam.ArmInterrupts([], "Interrupt Controller") isa = VectorParam.ArmISA([], "ISA instance") elif buildEnv['TARGET_ISA'] == 'power': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") dtb = Param.PowerTLB(PowerTLB(), "Data TLB") itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") interrupts = VectorParam.PowerInterrupts([], "Interrupt Controller") isa = VectorParam.PowerISA([], "ISA instance") elif buildEnv['TARGET_ISA'] == 'riscv': dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB") itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB") interrupts = VectorParam.RiscvInterrupts([], "Interrupt Controller") isa = VectorParam.RiscvISA([], "ISA instance") else: print "Don't know what TLB to use for ISA %s" % \ buildEnv['TARGET_ISA'] sys.exit(1) max_insts_all_threads = Param.Counter( 0, "terminate when all threads have reached this inst count") max_insts_any_thread = Param.Counter( 0, "terminate when any thread reaches this inst count") simpoint_start_insts = VectorParam.Counter( [], "starting instruction counts of simpoints") max_loads_all_threads = Param.Counter( 0, "terminate when all threads have reached this load count") max_loads_any_thread = Param.Counter( 0, "terminate when any thread reaches this load count") progress_interval = Param.Frequency( '0Hz', "frequency to print out the progress message") switched_out = Param.Bool(False, "Leave the CPU switched out after startup (used when switching " \ "between CPU models)") tracer = Param.InstTracer(default_tracer, "Instruction tracer") icache_port = MasterPort("Instruction Port") dcache_port = MasterPort("Data Port") _cached_ports = ['icache_port', 'dcache_port'] if buildEnv['TARGET_ISA'] in ['x86', 'arm']: _cached_ports += ["itb.walker.port", "dtb.walker.port"] _uncached_slave_ports = [] _uncached_master_ports = [] if buildEnv['TARGET_ISA'] == 'x86': _uncached_slave_ports += [ "interrupts[0].pio", "interrupts[0].int_slave" ] _uncached_master_ports += ["interrupts[0].int_master"] def createInterruptController(self): if buildEnv['TARGET_ISA'] == 'sparc': self.interrupts = [ SparcInterrupts() for i in xrange(self.numThreads) ] elif buildEnv['TARGET_ISA'] == 'alpha': self.interrupts = [ AlphaInterrupts() for i in xrange(self.numThreads) ] elif buildEnv['TARGET_ISA'] == 'x86': self.apic_clk_domain = DerivedClockDomain( clk_domain=Parent.clk_domain, clk_divider=16) self.interrupts = [ X86LocalApic(clk_domain=self.apic_clk_domain, pio_addr=0x2000000000000000) for i in xrange(self.numThreads) ] _localApic = self.interrupts elif buildEnv['TARGET_ISA'] == 'mips': self.interrupts = [ MipsInterrupts() for i in xrange(self.numThreads) ] elif buildEnv['TARGET_ISA'] == 'arm': self.interrupts = [ ArmInterrupts() for i in xrange(self.numThreads) ] elif buildEnv['TARGET_ISA'] == 'power': self.interrupts = [ PowerInterrupts() for i in xrange(self.numThreads) ] elif buildEnv['TARGET_ISA'] == 'riscv': self.interrupts = \ [RiscvInterrupts() for i in xrange(self.numThreads)] else: print "Don't know what Interrupt Controller to use for ISA %s" % \ buildEnv['TARGET_ISA'] sys.exit(1) def connectCachedPorts(self, bus): for p in self._cached_ports: exec('self.%s = bus.slave' % p) def connectUncachedPorts(self, bus): for p in self._uncached_slave_ports: exec('self.%s = bus.master' % p) for p in self._uncached_master_ports: exec('self.%s = bus.slave' % p) def connectAllPorts(self, cached_bus, uncached_bus=None): self.connectCachedPorts(cached_bus) if not uncached_bus: uncached_bus = cached_bus self.connectUncachedPorts(uncached_bus) def addPrivateSplitL1Caches(self, ic, dc, iwc=None, dwc=None, dspm=None): if dspm: self.icache = ic self.icache_port = ic.cpu_side self.dspm = dspm self.dcache_port = dspm.cpu_side #weird but correct! if dc: self.dcache = dc self.dspm.mem_side = self.dcache.cpu_side self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] else: self._cached_ports = ['icache.mem_side', 'dspm.mem_side'] else: self.icache = ic self.dcache = dc self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] if buildEnv['TARGET_ISA'] in ['x86', 'arm']: if iwc and dwc: self.itb_walker_cache = iwc self.dtb_walker_cache = dwc self.itb.walker.port = iwc.cpu_side self.dtb.walker.port = dwc.cpu_side self._cached_ports += ["itb_walker_cache.mem_side", \ "dtb_walker_cache.mem_side"] else: self._cached_ports += ["itb.walker.port", "dtb.walker.port"] # Checker doesn't need its own tlb caches because it does # functional accesses only if self.checker != NULL: self._cached_ports += ["checker.itb.walker.port", \ "checker.dtb.walker.port"] def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None): self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) self.toL2Bus = L2XBar() self.connectCachedPorts(self.toL2Bus) self.l2cache = l2c self.toL2Bus.master = self.l2cache.cpu_side self._cached_ports = ['l2cache.mem_side'] def createThreads(self): # If no ISAs have been created, assume that the user wants the # default ISA. if len(self.isa) == 0: self.isa = [default_isa_class() for i in xrange(self.numThreads)] else: if len(self.isa) != int(self.numThreads): raise RuntimeError("Number of ISA instances doesn't " "match thread count") if self.checker != NULL: self.checker.createThreads() def addCheckerCpu(self): pass
class BaseCPU(MemObject): type = 'BaseCPU' abstract = True @classmethod def export_method_cxx_predecls(cls, code): code('#include "cpu/base.hh"') @classmethod def export_methods(cls, code): code(''' void switchOut(); void takeOverFrom(BaseCPU *cpu); ''') def takeOverFrom(self, old_cpu): self._ccObject.takeOverFrom(old_cpu._ccObject) system = Param.System(Parent.any, "system object") cpu_id = Param.Int(-1, "CPU identifier") numThreads = Param.Unsigned(1, "number of HW thread contexts") function_trace = Param.Bool(False, "Enable function trace") function_trace_start = Param.Tick(0, "Tick to start function trace") checker = Param.BaseCPU(NULL, "checker CPU") do_checkpoint_insts = Param.Bool(True, "enable checkpoint pseudo instructions") do_statistics_insts = Param.Bool(True, "enable statistics pseudo instructions") profile = Param.Latency('0ns', "trace the kernel stack") do_quiesce = Param.Bool(True, "enable quiesce instructions") workload = VectorParam.Process([], "processes to run") #vcpu = Param.Bool(False, "if this is a vcpu") #vcpu_hyperperiod = Param.Tick(10000, "") #vcpu_start_tick = Param.Tick(0, "when should this vcpu start processing") #vcpu_stop_tick = Param.Tick(10000, "when should this vcpu stop processing and schedule next event in next start") if buildEnv['TARGET_ISA'] == 'sparc': dtb = Param.SparcTLB(SparcTLB(), "Data TLB") itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") interrupts = Param.SparcInterrupts(NULL, "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'alpha': dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") interrupts = Param.AlphaInterrupts(NULL, "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'x86': dtb = Param.X86TLB(X86TLB(), "Data TLB") itb = Param.X86TLB(X86TLB(), "Instruction TLB") interrupts = Param.X86LocalApic(NULL, "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'mips': dtb = Param.MipsTLB(MipsTLB(), "Data TLB") itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") interrupts = Param.MipsInterrupts(NULL, "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'arm': dtb = Param.ArmTLB(ArmTLB(), "Data TLB") itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") interrupts = Param.ArmInterrupts(NULL, "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'power': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") dtb = Param.PowerTLB(PowerTLB(), "Data TLB") itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") interrupts = Param.PowerInterrupts(NULL, "Interrupt Controller") else: print "Don't know what TLB to use for ISA %s" % \ buildEnv['TARGET_ISA'] sys.exit(1) max_insts_all_threads = Param.Counter( 0, "terminate when all threads have reached this inst count") max_insts_any_thread = Param.Counter( 0, "terminate when any thread reaches this inst count") max_loads_all_threads = Param.Counter( 0, "terminate when all threads have reached this load count") max_loads_any_thread = Param.Counter( 0, "terminate when any thread reaches this load count") progress_interval = Param.Frequency( '0Hz', "frequency to print out the progress message") defer_registration = Param.Bool( False, "defer registration with system (for sampling)") tracer = Param.InstTracer(default_tracer, "Instruction tracer") icache_port = MasterPort("Instruction Port") dcache_port = MasterPort("Data Port") _cached_ports = ['icache_port', 'dcache_port'] if buildEnv['TARGET_ISA'] in ['x86', 'arm']: _cached_ports += ["itb.walker.port", "dtb.walker.port"] _uncached_slave_ports = [] _uncached_master_ports = [] if buildEnv['TARGET_ISA'] == 'x86': _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"] _uncached_master_ports += ["interrupts.int_master"] def createInterruptController(self): if buildEnv['TARGET_ISA'] == 'sparc': self.interrupts = SparcInterrupts() elif buildEnv['TARGET_ISA'] == 'alpha': self.interrupts = AlphaInterrupts() elif buildEnv['TARGET_ISA'] == 'x86': _localApic = X86LocalApic(pio_addr=0x2000000000000000) self.interrupts = _localApic elif buildEnv['TARGET_ISA'] == 'mips': self.interrupts = MipsInterrupts() elif buildEnv['TARGET_ISA'] == 'arm': self.interrupts = ArmInterrupts() elif buildEnv['TARGET_ISA'] == 'power': self.interrupts = PowerInterrupts() else: print "Don't know what Interrupt Controller to use for ISA %s" % \ buildEnv['TARGET_ISA'] sys.exit(1) def connectCachedPorts(self, bus): for p in self._cached_ports: exec('self.%s = bus.slave' % p) def connectUncachedPorts(self, bus): for p in self._uncached_slave_ports: exec('self.%s = bus.master' % p) for p in self._uncached_master_ports: exec('self.%s = bus.slave' % p) def connectAllPorts(self, cached_bus, uncached_bus=None): self.connectCachedPorts(cached_bus) if not uncached_bus: uncached_bus = cached_bus self.connectUncachedPorts(uncached_bus) def addPrivateSplitL1Caches(self, ic, dc, iwc=None, dwc=None): self.icache = ic self.dcache = dc self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] if buildEnv['TARGET_ISA'] in ['x86', 'arm']: if iwc and dwc: self.itb_walker_cache = iwc self.dtb_walker_cache = dwc self.itb.walker.port = iwc.cpu_side self.dtb.walker.port = dwc.cpu_side self._cached_ports += ["itb_walker_cache.mem_side", \ "dtb_walker_cache.mem_side"] else: self._cached_ports += ["itb.walker.port", "dtb.walker.port"] # Checker doesn't need its own tlb caches because it does # functional accesses only if self.checker != NULL: self._cached_ports += ["checker.itb.walker.port", \ "checker.dtb.walker.port"] def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None): self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) # Override the default bus clock of 1 GHz and uses the CPU # clock for the L1-to-L2 bus, and also set a width of 32 bytes # (256-bits), which is four times that of the default bus. self.toL2Bus = CoherentBus(clock=Parent.clock, width=32) self.connectCachedPorts(self.toL2Bus) self.l2cache = l2c self.toL2Bus.master = self.l2cache.cpu_side self._cached_ports = ['l2cache.mem_side'] def addCheckerCpu(self): pass
class BaseCPU(MemObject): type = 'BaseCPU' abstract = True system = Param.System(Parent.any, "system object") cpu_id = Param.Int(-1, "CPU identifier") numThreads = Param.Unsigned(2, "number of HW thread contexts") function_trace = Param.Bool(False, "Enable function trace") function_trace_start = Param.Tick(0, "Cycle to start function trace") checker = Param.BaseCPU(NULL, "checker CPU") do_checkpoint_insts = Param.Bool(True, "enable checkpoint pseudo instructions") do_statistics_insts = Param.Bool(True, "enable statistics pseudo instructions") profile = Param.Latency('0ns', "trace the kernel stack") do_quiesce = Param.Bool(True, "enable quiesce instructions") workload = VectorParam.Process([], "processes to run") if buildEnv['TARGET_ISA'] == 'sparc': dtb = Param.SparcTLB(SparcTLB(), "Data TLB") itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") interrupts = Param.SparcInterrupts(NULL, "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'alpha': dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") interrupts = Param.AlphaInterrupts(NULL, "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'x86': dtb = Param.X86TLB(X86TLB(), "Data TLB") itb = Param.X86TLB(X86TLB(), "Instruction TLB") interrupts = Param.X86LocalApic(NULL, "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'mips': dtb = Param.MipsTLB(MipsTLB(), "Data TLB") itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") interrupts = Param.MipsInterrupts(NULL, "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'arm': dtb = Param.ArmTLB(ArmTLB(), "Data TLB") itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") interrupts = Param.ArmInterrupts(NULL, "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'power': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") dtb = Param.PowerTLB(PowerTLB(), "Data TLB") itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") interrupts = Param.PowerInterrupts(NULL, "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'mapu': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") dtb = Param.MapuTLB(MapuTLB(), "Data TLB") itb = Param.MapuTLB(MapuTLB(), "Instruction TLB") interrupts = Param.MapuInterrupts(NULL, "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'ucp': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") dtb = Param.UcpTLB(UcpTLB(), "Data TLB") itb = Param.UcpTLB(UcpTLB(), "Instruction TLB") interrupts = Param.UcpInterrupts(NULL, "Interrupt Controller") else: print "Don't know what TLB to use for ISA %s" % \ buildEnv['TARGET_ISA'] sys.exit(1) max_insts_all_threads = Param.Counter( 0, "terminate when all threads have reached this inst count") max_insts_any_thread = Param.Counter( 0, "terminate when any thread reaches this inst count") max_loads_all_threads = Param.Counter( 0, "terminate when all threads have reached this load count") max_loads_any_thread = Param.Counter( 0, "terminate when any thread reaches this load count") progress_interval = Param.Tick( 0, "interval to print out the progress message") defer_registration = Param.Bool( False, "defer registration with system (for sampling)") clock = Param.Clock('1t', "clock speed") phase = Param.Latency('0ns', "clock phase") tracer = Param.InstTracer(default_tracer, "Instruction tracer") icache_port = MasterPort("Instruction Port") dcache_port = MasterPort("Data Port") micache_port = MasterPort("MPU Instruction Port") _cached_ports = ['icache_port', 'dcache_port', 'micache_port'] if buildEnv['TARGET_ISA'] in ['x86', 'arm']: _cached_ports += ["itb.walker.port", "dtb.walker.port"] _uncached_slave_ports = [] _uncached_master_ports = [] if buildEnv['TARGET_ISA'] == 'x86': _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"] _uncached_master_ports += ["interrupts.int_master"] def createInterruptController(self): if buildEnv['TARGET_ISA'] == 'sparc': self.interrupts = SparcInterrupts() elif buildEnv['TARGET_ISA'] == 'alpha': self.interrupts = AlphaInterrupts() elif buildEnv['TARGET_ISA'] == 'x86': _localApic = X86LocalApic(pio_addr=0x2000000000000000) self.interrupts = _localApic elif buildEnv['TARGET_ISA'] == 'mips': self.interrupts = MipsInterrupts() elif buildEnv['TARGET_ISA'] == 'arm': self.interrupts = ArmInterrupts() elif buildEnv['TARGET_ISA'] == 'power': self.interrupts = PowerInterrupts() elif buildEnv['TARGET_ISA'] == 'mapu': self.interrupts = MapuInterrupts() else: print "Don't know what Interrupt Controller to use for ISA %s" % \ buildEnv['TARGET_ISA'] sys.exit(1) def connectCachedPorts(self, bus): for p in self._cached_ports: exec('self.%s = bus.slave' % p) def connectUncachedPorts(self, bus): for p in self._uncached_slave_ports: exec('self.%s = bus.master' % p) for p in self._uncached_master_ports: exec('self.%s = bus.slave' % p) def connectAllPorts(self, cached_bus, uncached_bus=None): self.connectCachedPorts(cached_bus) if not uncached_bus: uncached_bus = cached_bus self.connectUncachedPorts(uncached_bus) def addPrivateSplitL1Caches(self, ic, dc, mic=None, iwc=None, dwc=None): self.icache = ic self.micache = mic self.dcache = dc self.icache_port = ic.cpu_side self.micache_port = mic.cpu_side self.dcache_port = dc.cpu_side self._cached_ports = [ 'icache.mem_side', 'dcache.mem_side', 'micache.mem_side' ] if buildEnv['TARGET_ISA'] in ['x86', 'arm']: if iwc and dwc: self.itb_walker_cache = iwc self.dtb_walker_cache = dwc self.itb.walker.port = iwc.cpu_side self.dtb.walker.port = dwc.cpu_side self._cached_ports += ["itb_walker_cache.mem_side", \ "dtb_walker_cache.mem_side"] else: self._cached_ports += ["itb.walker.port", "dtb.walker.port"] # Checker doesn't need its own tlb caches because it does # functional accesses only if self.checker != NULL: self._cached_ports += ["checker.itb.walker.port", \ "checker.dtb.walker.port"] def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None): self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) self.toL2Bus = CoherentBus() self.connectCachedPorts(self.toL2Bus) self.l2cache = l2c self.toL2Bus.master = self.l2cache.cpu_side self._cached_ports = ['l2cache.mem_side'] def addCheckerCpu(self): pass
class BaseCPU(MemObject): type = 'BaseCPU' abstract = True system = Param.System(Parent.any, "system object") cpu_id = Param.Int(-1, "CPU identifier") numThreads = Param.Unsigned(1, "number of HW thread contexts") function_trace = Param.Bool(False, "Enable function trace") function_trace_start = Param.Tick(0, "Cycle to start function trace") checker = Param.BaseCPU(NULL, "checker CPU") do_checkpoint_insts = Param.Bool(True, "enable checkpoint pseudo instructions") do_statistics_insts = Param.Bool(True, "enable statistics pseudo instructions") if buildEnv['FULL_SYSTEM']: profile = Param.Latency('0ns', "trace the kernel stack") do_quiesce = Param.Bool(True, "enable quiesce instructions") else: workload = VectorParam.Process("processes to run") if buildEnv['TARGET_ISA'] == 'sparc': dtb = Param.SparcTLB(SparcTLB(), "Data TLB") itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") if buildEnv['FULL_SYSTEM']: interrupts = Param.SparcInterrupts(SparcInterrupts(), "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'alpha': dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") if buildEnv['FULL_SYSTEM']: interrupts = Param.AlphaInterrupts(AlphaInterrupts(), "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'x86': dtb = Param.X86TLB(X86TLB(), "Data TLB") itb = Param.X86TLB(X86TLB(), "Instruction TLB") if buildEnv['FULL_SYSTEM']: _localApic = X86LocalApic(pio_addr=0x2000000000000000) interrupts = \ Param.X86LocalApic(_localApic, "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'mips': dtb = Param.MipsTLB(MipsTLB(), "Data TLB") itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") if buildEnv['FULL_SYSTEM']: interrupts = Param.MipsInterrupts(MipsInterrupts(), "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'arm': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") dtb = Param.ArmTLB(ArmTLB(), "Data TLB") itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") if buildEnv['FULL_SYSTEM']: interrupts = Param.ArmInterrupts(ArmInterrupts(), "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'power': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") dtb = Param.PowerTLB(PowerTLB(), "Data TLB") itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") if buildEnv['FULL_SYSTEM']: interrupts = Param.PowerInterrupts(PowerInterrupts(), "Interrupt Controller") else: print "Don't know what TLB to use for ISA %s" % \ buildEnv['TARGET_ISA'] sys.exit(1) max_insts_all_threads = Param.Counter( 0, "terminate when all threads have reached this inst count") max_insts_any_thread = Param.Counter( 0, "terminate when any thread reaches this inst count") max_loads_all_threads = Param.Counter( 0, "terminate when all threads have reached this load count") max_loads_any_thread = Param.Counter( 0, "terminate when any thread reaches this load count") progress_interval = Param.Tick( 0, "interval to print out the progress message") defer_registration = Param.Bool( False, "defer registration with system (for sampling)") clock = Param.Clock('1t', "clock speed") phase = Param.Latency('0ns', "clock phase") tracer = Param.InstTracer(default_tracer, "Instruction tracer") _mem_ports = [] if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: _mem_ports = [ "itb.walker.port", "dtb.walker.port", "interrupts.pio", "interrupts.int_port" ] def connectMemPorts(self, bus): for p in self._mem_ports: if p != 'physmem_port': exec('self.%s = bus.port' % p) def addPrivateSplitL1Caches(self, ic, dc): assert (len(self._mem_ports) < 6) self.icache = ic self.dcache = dc self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: self._mem_ports += ["itb.walker_port", "dtb.walker_port"] def addTwoLevelCacheHierarchy(self, ic, dc, l2c): self.addPrivateSplitL1Caches(ic, dc) self.toL2Bus = Bus() self.connectMemPorts(self.toL2Bus) self.l2cache = l2c self.l2cache.cpu_side = self.toL2Bus.port self._mem_ports = ['l2cache.mem_side'] if buildEnv['TARGET_ISA'] == 'mips': CP0_IntCtl_IPTI = Param.Unsigned(0, "No Description") CP0_IntCtl_IPPCI = Param.Unsigned(0, "No Description") CP0_SrsCtl_HSS = Param.Unsigned(0, "No Description") CP0_EBase_CPUNum = Param.Unsigned(0, "No Description") CP0_PRId_CompanyOptions = Param.Unsigned( 0, "Company Options in Processor ID Register") CP0_PRId_CompanyID = Param.Unsigned( 0, "Company Identifier in Processor ID Register") CP0_PRId_ProcessorID = Param.Unsigned( 1, "Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company" ) CP0_PRId_Revision = Param.Unsigned( 0, "Processor Revision Number in Processor ID Register") CP0_Config_BE = Param.Unsigned(0, "Big Endian?") CP0_Config_AT = Param.Unsigned(0, "No Description") CP0_Config_AR = Param.Unsigned(0, "No Description") CP0_Config_MT = Param.Unsigned(0, "No Description") CP0_Config_VI = Param.Unsigned(0, "No Description") CP0_Config1_M = Param.Unsigned(0, "Config2 Implemented?") CP0_Config1_MMU = Param.Unsigned(0, "MMU Type") CP0_Config1_IS = Param.Unsigned(0, "No Description") CP0_Config1_IL = Param.Unsigned(0, "No Description") CP0_Config1_IA = Param.Unsigned(0, "No Description") CP0_Config1_DS = Param.Unsigned(0, "No Description") CP0_Config1_DL = Param.Unsigned(0, "No Description") CP0_Config1_DA = Param.Unsigned(0, "No Description") CP0_Config1_C2 = Param.Bool(False, "No Description") CP0_Config1_MD = Param.Bool(False, "No Description") CP0_Config1_PC = Param.Bool(False, "No Description") CP0_Config1_WR = Param.Bool(False, "No Description") CP0_Config1_CA = Param.Bool(False, "No Description") CP0_Config1_EP = Param.Bool(False, "No Description") CP0_Config1_FP = Param.Bool(False, "FPU Implemented?") CP0_Config2_M = Param.Bool(False, "Config3 Implemented?") CP0_Config2_TU = Param.Unsigned(0, "No Description") CP0_Config2_TS = Param.Unsigned(0, "No Description") CP0_Config2_TL = Param.Unsigned(0, "No Description") CP0_Config2_TA = Param.Unsigned(0, "No Description") CP0_Config2_SU = Param.Unsigned(0, "No Description") CP0_Config2_SS = Param.Unsigned(0, "No Description") CP0_Config2_SL = Param.Unsigned(0, "No Description") CP0_Config2_SA = Param.Unsigned(0, "No Description") CP0_Config3_M = Param.Bool(False, "Config4 Implemented?") CP0_Config3_DSPP = Param.Bool(False, "DSP Extensions Present?") CP0_Config3_LPA = Param.Bool(False, "No Description") CP0_Config3_VEIC = Param.Bool(False, "No Description") CP0_Config3_VInt = Param.Bool(False, "No Description") CP0_Config3_SP = Param.Bool(False, "No Description") CP0_Config3_MT = Param.Bool(False, "Multithreading Extensions Present?") CP0_Config3_SM = Param.Bool(False, "No Description") CP0_Config3_TL = Param.Bool(False, "No Description") CP0_WatchHi_M = Param.Bool(False, "No Description") CP0_PerfCtr_M = Param.Bool(False, "No Description") CP0_PerfCtr_W = Param.Bool(False, "No Description") CP0_PRId = Param.Unsigned(0, "CP0 Status Register") CP0_Config = Param.Unsigned(0, "CP0 Config Register") CP0_Config1 = Param.Unsigned(0, "CP0 Config1 Register") CP0_Config2 = Param.Unsigned(0, "CP0 Config2 Register") CP0_Config3 = Param.Unsigned(0, "CP0 Config3 Register")