def _RunCompile(self, netlist, lseArgumentFile):
synth = self._toolChain.GetSynthesizer()
synth.Parameters[synth.SwitchProjectFile] = netlist.ModuleName + ".prj"
try:
synth.Compile(lseArgumentFile.LogFile)
except LatticeException as ex:
raise CompilerException("Error while compiling '{0!s}'.".format(netlist)) from ex
if synth.HasErrors:
raise SkipableCompilerException("Error while compiling '{0!s}'.".format(netlist))
def _RunCompile(self, netlist):
reportFilePath = self.Directories.Working / (netlist.ModuleName + ".log")
synth = self._toolChain.GetSynthesizer()
synth.Parameters[synth.SwitchSourceFile] = netlist.ModuleName + ".tcl"
synth.Parameters[synth.SwitchLogFile] = str(reportFilePath)
try:
synth.Compile()
except VivadoException as ex:
raise CompilerException("Error while compiling '{0!s}'.".format(netlist)) from ex
if synth.HasErrors:
raise SkipableCompilerException("Error while compiling '{0!s}'.".format(netlist))
def _RunCompile(self, netlist):
q2map = self._toolChain.GetMap()
q2map.Parameters[q2map.ArgProjectName] = str(netlist.QsfFile)
try:
q2map.Compile()
except QuartusException as ex:
raise CompilerException(
"Error while compiling '{0!s}'.".format(netlist)) from ex
if q2map.HasErrors:
raise SkipableCompilerException(
"Error while compiling '{0!s}'.".format(netlist))
def _RunCompile(self, netlist):
reportFilePath = self.Directories.Working / (netlist.ModuleName + ".log")
xst = self._toolChain.GetXst()
xst.Parameters[xst.SwitchIntStyle] = "xflow"
xst.Parameters[xst.SwitchXstFile] = netlist.ModuleName + ".xst"
xst.Parameters[xst.SwitchReportFile] = str(reportFilePath)
try:
xst.Compile()
except ISEException as ex:
raise CompilerException("Error while compiling '{0!s}'.".format(netlist)) from ex
if xst.HasErrors:
raise SkipableCompilerException("Error while compiling '{0!s}'.".format(netlist))
def _RunCompile(self, netlist, device):
self.LogVerbose("Patching coregen.cgp and .cgc files...")
# read netlist settings from configuration file
xcoInputFilePath = netlist.XcoFile
cgcTemplateFilePath = self.Directories.Netlist / "template.cgc"
cgpFilePath = self.Directories.Working / "coregen.cgp"
cgcFilePath = self.Directories.Working / "coregen.cgc"
xcoFilePath = self.Directories.Working / xcoInputFilePath.name
if (self.Host.Platform == "Windows"):
WorkingDirectory = ".\\temp\\"
else:
WorkingDirectory = "./temp/"
# write CoreGenerator project file
cgProjectFileContent = dedent("""\
SET addpads = false
SET asysymbol = false
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = {Device}
SET devicefamily = {DeviceFamily}
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = {Package}
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = {SpeedGrade}
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = {WorkingDirectory}
""".format(
Device=device.ShortName.lower(),
DeviceFamily=device.FamilyName.lower(),
Package=(str(device.Package).lower() + str(device.PinCount)),
SpeedGrade=device.SpeedGrade,
WorkingDirectory=WorkingDirectory
))
self.LogDebug("Writing CoreGen project file to '{0}'.".format(cgpFilePath))
with cgpFilePath.open('w') as cgpFileHandle:
cgpFileHandle.write(cgProjectFileContent)
# write CoreGenerator content? file
self.LogDebug("Reading CoreGen content file to '{0}'.".format(cgcTemplateFilePath))
with cgcTemplateFilePath.open('r') as cgcFileHandle:
cgContentFileContent = cgcFileHandle.read()
cgContentFileContent = cgContentFileContent.format(
name="lcd_ChipScopeVIO",
device=device.ShortName,
devicefamily=device.FamilyName,
package=(str(device.Package) + str(device.PinCount)),
speedgrade=device.SpeedGrade
)
self.LogDebug("Writing CoreGen content file to '{0}'.".format(cgcFilePath))
with cgcFilePath.open('w') as cgcFileHandle:
cgcFileHandle.write(cgContentFileContent)
# copy xco file into temporary directory
self.LogVerbose("Copy CoreGen xco file to '{0}'.".format(xcoFilePath))
self.LogDebug("cp {0!s} {1!s}".format(xcoInputFilePath, self.Directories.Working))
try:
shutil_copy(str(xcoInputFilePath), str(xcoFilePath), follow_symlinks=True)
except OSError as ex:
raise CompilerException("Error while copying '{0!s}'.".format(xcoInputFilePath)) from ex
# change working directory to temporary CoreGen path
self.LogDebug("cd {0!s}".format(self.Directories.Working))
try:
chdir(str(self.Directories.Working))
except OSError as ex:
raise CompilerException("Error while changing to '{0!s}'.".format(self.Directories.Working)) from ex
# running CoreGen
# ==========================================================================
self.LogVerbose("Executing CoreGen...")
coreGen = self._toolChain.GetCoreGenerator()
coreGen.Parameters[coreGen.SwitchProjectFile] = "." # use current directory and the default project name
coreGen.Parameters[coreGen.SwitchBatchFile] = str(xcoFilePath)
coreGen.Parameters[coreGen.FlagRegenerate] = True
try:
coreGen.Generate()
except ISEException as ex:
raise CompilerException("Error while compiling '{0!s}'.".format(netlist)) from ex
if coreGen.HasErrors:
raise SkipableCompilerException("Error while compiling '{0!s}'.".format(netlist))
def _WriteXstOptionsFile(self, netlist, device):
self.LogVerbose("Generating XST options file.")
# read XST options file template
self.LogDebug("Reading Xilinx Compiler Tool option file from '{0!s}'".format(netlist.XstTemplateFile))
if (not netlist.XstTemplateFile.exists()):
raise CompilerException("XST template files '{0!s}' not found.".format(netlist.XstTemplateFile))\
from FileNotFoundError(str(netlist.XstTemplateFile))
with netlist.XstTemplateFile.open('r') as fileHandle:
xstFileContent = fileHandle.read()
xstTemplateDictionary = {
'prjFile': str(netlist.PrjFile),
'UseNewParser': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.UseNewParser'],
'InputFormat': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.InputFormat'],
'OutputFormat': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.OutputFormat'],
'OutputName': netlist.ModuleName,
'Part': str(device),
'TopModuleName': netlist.ModuleName,
'OptimizationMode': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.OptimizationMode'],
'OptimizationLevel': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.OptimizationLevel'],
'PowerReduction': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.PowerReduction'],
'IgnoreSynthesisConstraintsFile': self.Host.PoCConfig[netlist.ConfigSectionName]['XSTOption.IgnoreSynthesisConstraintsFile'],
'SynthesisConstraintsFile': str(netlist.XcfFile),
'KeepHierarchy': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.KeepHierarchy'],
'NetListHierarchy': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.NetListHierarchy'],
'GenerateRTLView': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.GenerateRTLView'],
'GlobalOptimization': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.Globaloptimization'],
'ReadCores': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.ReadCores'],
'SearchDirectories': '"{0!s}"'.format(self.Directories.Destination),
'WriteTimingConstraints': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.WriteTimingConstraints'],
'CrossClockAnalysis': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.CrossClockAnalysis'],
'HierarchySeparator': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.HierarchySeparator'],
'BusDelimiter': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.BusDelimiter'],
'Case': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.Case'],
'SliceUtilizationRatio': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.SliceUtilizationRatio'],
'BRAMUtilizationRatio': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.BRAMUtilizationRatio'],
'DSPUtilizationRatio': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.DSPUtilizationRatio'],
'LUTCombining': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.LUTCombining'],
'ReduceControlSets': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.ReduceControlSets'],
'Verilog2001': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.Verilog2001'],
'FSMExtract': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.FSMExtract'],
'FSMEncoding': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.FSMEncoding'],
'FSMSafeImplementation': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.FSMSafeImplementation'],
'FSMStyle': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.FSMStyle'],
'RAMExtract': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.RAMExtract'],
'RAMStyle': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.RAMStyle'],
'ROMExtract': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.ROMExtract'],
'ROMStyle': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.ROMStyle'],
'MUXExtract': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.MUXExtract'],
'MUXStyle': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.MUXStyle'],
'DecoderExtract': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.DecoderExtract'],
'PriorityExtract': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.PriorityExtract'],
'ShRegExtract': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.ShRegExtract'],
'ShiftExtract': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.ShiftExtract'],
'XorCollapse': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.XorCollapse'],
'AutoBRAMPacking': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.AutoBRAMPacking'],
'ResourceSharing': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.ResourceSharing'],
'ASyncToSync': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.ASyncToSync'],
'UseDSP48': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.UseDSP48'],
'IOBuf': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.IOBuf'],
'MaxFanOut': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.MaxFanOut'],
'BufG': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.BufG'],
'RegisterDuplication': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.RegisterDuplication'],
'RegisterBalancing': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.RegisterBalancing'],
'SlicePacking': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.SlicePacking'],
'OptimizePrimitives': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.OptimizePrimitives'],
'UseClockEnable': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.UseClockEnable'],
'UseSyncSet': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.UseSyncSet'],
'UseSyncReset': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.UseSyncReset'],
'PackIORegistersIntoIOBs': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.PackIORegistersIntoIOBs'],
'EquivalentRegisterRemoval': self.Host.PoCConfig[netlist.ConfigSectionName] ['XSTOption.EquivalentRegisterRemoval'],
'SliceUtilizationRatioMaxMargin': self.Host.PoCConfig[netlist.ConfigSectionName]['XSTOption.SliceUtilizationRatioMaxMargin']
}
xstFileContent = xstFileContent.format(**xstTemplateDictionary)
hdlParameters=self._GetHDLParameters(netlist.ConfigSectionName)
if(len(hdlParameters)>0):
xstFileContent += "-generics {"
for keyValuePair in hdlParameters.items():
xstFileContent += " {0}={1}".format(*keyValuePair)
xstFileContent += " }\n"
self.LogDebug("Writing Xilinx Compiler Tool option file to '{0!s}'".format(netlist.XstFile))
with netlist.XstFile.open('w') as fileHandle:
fileHandle.write(xstFileContent)