def elaborate_logic(s):
s.pt = PassThrough(s.nbits)
s.reg0 = Register(s.nbits)
s.connect(s.in_, s.pt.in_)
s.connect(s.pt.out, s.reg0.in_)
s.connect(s.reg0.out, s.out)
def elaborate_logic(s):
s.reg_ = Register(s.nbits)
@s.combinational
def comb():
s.other.value = s.in_
s.connect(s.reg_.in_, s.other)
s.connect(s.reg_.out, s.out)
def elaborate_logic(s):
# Submodules
s.reg0 = Register(s.nbits)
s.split = s.subclass(s.nbits, s.groupings)
# Connections
s.connect(s.in_, s.reg0.in_)
s.connect(s.reg0.out, s.split.in_)
for i, x in enumerate(s.out):
s.connect(s.split.out[i], x)
def elaborate_logic(s):
s.reg_ = Register(s.nbits)
@s.combinational
def comb():
s.other.value = s.in_
for i in range(s.nbits):
s.connect(s.reg_.in_[i], s.other[i])
s.connect(s.reg_.out, s.out)
def elaborate_logic(s):
s.reg_ = Register(s.nbits)
s.connect(s.in_, s.other)
for i in range(s.nbits):
s.connect(s.reg_.in_[i], s.other[i])
s.connect(s.reg_.out, s.out)
def elaborate_logic(s):
s.reg_ = Register(s.nbits)
s.connect(s.in_, s.other)
s.connect(s.reg_.in_, s.other)
s.connect(s.reg_.out, s.out)