Пример #1
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def test_cap():
    mydir = pathlib.Path(__file__).resolve()
    pdk_path = mydir.parent.parent.parent / "pdks" / "FinFET14nm_Mock_PDK"
    config_path = mydir.parent.parent / "files"
    test_path = mydir.parent.parent / "files" / "test_circuits" / "test_cap.sp"
    gen_const_path = mydir.parent / "Results" / "TEST_CAP.verilog.json"
    gold_const_path = (mydir.parent.parent / "files" / "test_results" /
                       "test_cap.const.json")

    updated_ckt = compiler_input(test_path, "test_cap", pdk_path, config_path)
    assert updated_ckt.find("TEST_CAP")
    primitives, generators = call_primitive_generator(updated_ckt, pdk_path,
                                                      True)
    verilog_tbl = constraint_generator(updated_ckt, generators)
    compiler_output(
        updated_ckt,
        "TEST_CAP",
        verilog_tbl,
        pathlib.Path(__file__).parent / "Results",
    )
    assert "CAP_30f" in primitives.keys()
    with open(gen_const_path, "r") as const_fp:
        gen_const = next(x for x in json.load(const_fp)["modules"]
                         if x["name"] == "TEST_CAP")["constraints"]
        gen_const.sort(key=lambda item: item.get("constraint"))
    with open(gold_const_path, "r") as const_fp:
        gold_const = json.load(const_fp)
        gold_const.sort(key=lambda item: item.get("constraint"))
    assert gold_const == gen_const
Пример #2
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def test_compiler_output():
    updated_ckt, library = test_compiler()
    # Every example should contain a setup file
    test_path = pathlib.Path(__file__).resolve().parent / 'ota.sp'
    compiler_output(
        test_path, library, updated_ckt, 'ota',
        pathlib.Path(__file__).parent / 'Results',
        pathlib.Path(__file__).parent.parent.parent / 'pdks' /
        'FinFET14nm_Mock_PDK')
Пример #3
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def test_compiler_output():
    updated_ckt = test_compiler()
    # Every example should contain a setup file
    verilog_tbl = constraint_generator(
        updated_ckt, ["CMC_PMOS", "SCM_NMOS", "CMC_S_NMOS_B", "DP_NMOS_B"])
    compiler_output(
        updated_ckt,
        "ota",
        verilog_tbl,
        pathlib.Path(__file__).parent / "Results",
    )
Пример #4
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def primitives(cn):
    mydir = pathlib.Path(__file__).resolve()
    pdk_path = mydir.parent.parent.parent / 'pdks' / 'FinFET14nm_Mock_PDK'
    test_path = mydir.parent / 'test_circuits' / (cn + '.sp')
    updated_ckt, library = compiler(test_path, cn, pdk_path)
    assert cn in updated_ckt
    return compiler_output(test_path, library, updated_ckt, 'sizing',
                           pathlib.Path(__file__).parent / 'Results', pdk_path)
Пример #5
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def test_group_block_hsc(test_compiler_hsc):
    updated_ckt, library, dir_name = test_compiler_hsc

    test_path = pathlib.Path(__file__).resolve(
    ).parent / 'test_circuits' / dir_name / ('high_speed_comparator.sp')
    out_path = pathlib.Path(__file__).resolve().parent
    result_path = out_path / 'Results' / dir_name
    pdk_path = pathlib.Path(
        __file__).parent.parent.parent / 'pdks' / 'FinFET14nm_Mock_PDK'
    compiler_output(test_path, library, updated_ckt, 'high_speed_comparator',
                    result_path, pdk_path)
    gen_const_path = result_path / 'high_speed_comparator.const.json'
    gold_const_path = out_path / 'test_results' / (dir_name + '.const.json')
    with open(gen_const_path, "r") as const_fp:
        gen_const = json.load(const_fp)
    with open(gold_const_path, "r") as const_fp:
        gold_const = json.load(const_fp)
    assert gold_const == gen_const
Пример #6
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def test_sizing1():
    mydir = pathlib.Path(__file__).resolve()
    test_path = mydir.parent / 'test_circuits' / 'intel_circuit1.sp'
    updated_ckt,library = compiler(test_path, "intel_circuit1",0 )
    all_subckt_list = [ele["name"] for ele in updated_ckt]
    assert 'intel_circuit1' in all_subckt_list
    pdk_path = mydir.parent.parent.parent / 'pdks' / 'FinFET14nm_Mock_PDK' 
    primitives = compiler_output(test_path, library, updated_ckt, 'sizing', pathlib.Path(__file__).parent / 'Results', pdk_path )
    assert primitives['DCL_PMOS_nfin6_m4_n12_X2_Y1_ST6_HVT']['stack']==6
    assert primitives['DCL_PMOS_nfin6_m4_n12_X2_Y1_ST6_HVT']['vt_type']=='HVT'
Пример #7
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def test_sizing4(path):
    test_path, pdk_path = path
    updated_ckt, library = compiler(test_path, 'intel_circuit4', pdk_path)
    assert 'SCM_PMOS' in updated_ckt
    assert 'CMB_PMOS_2' in updated_ckt
    assert 'INV_B' in updated_ckt
    assert 'intel_circuit4' in updated_ckt
    primitives = compiler_output(test_path, library, updated_ckt, 'sizing',
                                 pathlib.Path(__file__).parent / 'Results',
                                 pdk_path)
    assert len(primitives) == 7
Пример #8
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def test_sizing4():
    mydir = pathlib.Path(__file__).resolve()
    test_path = mydir.parent / 'test_circuits' / 'intel_circuit4.sp'
    updated_ckt,library = compiler(test_path, "intel_circuit4",0 )
    all_subckt_list = [ele["name"] for ele in updated_ckt]
    assert 'SCM_PMOS' in all_subckt_list
    assert 'CMB_PMOS_2' in all_subckt_list
    assert 'INV_B' in all_subckt_list
    assert 'intel_circuit4' in all_subckt_list
    pdk_path = mydir.parent.parent.parent / 'pdks' / 'FinFET14nm_Mock_PDK' 
    primitives = compiler_output(test_path, library, updated_ckt, 'sizing', pathlib.Path(__file__).parent / 'Results', pdk_path )
    assert  len(primitives) ==9
Пример #9
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def test_sizing3():
    mydir = pathlib.Path(__file__).resolve()
    test_path = mydir.parent / 'test_circuits' / 'intel_circuit3.sp'
    updated_ckt,library = compiler(test_path, "intel_circuit3",0 )
    all_subckt_list = [ele["name"] for ele in updated_ckt]
    assert 'DP_NMOS_B' in all_subckt_list
    assert 'intel_circuit3' in all_subckt_list
    pdk_path = mydir.parent.parent.parent / 'pdks' / 'FinFET14nm_Mock_PDK' 
    primitives = compiler_output(test_path, library, updated_ckt, 'sizing', pathlib.Path(__file__).parent / 'Results', pdk_path )
    assert  len(primitives) ==6
    assert 'Switch_PMOS_nfin4_nf1_m4_n12_X2_Y1_ST3' in primitives.keys()
    assert primitives['Switch_PMOS_nfin4_nf1_m4_n12_X2_Y1_ST3']['stack']==3
    assert primitives['Switch_PMOS_nfin6_nf4_m3_n12_X3_Y2_LVT']['vt_type']=='LVT'
Пример #10
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def test_cap():
    mydir = pathlib.Path(__file__).resolve()
    pdk_path = mydir.parent.parent.parent / 'pdks' / 'FinFET14nm_Mock_PDK'
    test_path = mydir.parent / 'test_circuits' / 'test_cap.sp'
    gen_const_path = mydir.parent / 'Results' / 'test_cap.const.json'
    gold_const_path = mydir.parent / 'test_results' / 'test_cap.const.json'

    updated_ckt, library = compiler(test_path, "test_cap", pdk_path)
    assert 'test_cap' in updated_ckt
    primitives = compiler_output(test_path, library, updated_ckt, 'test_cap',
                                 pathlib.Path(__file__).parent / 'Results',
                                 pdk_path)
    assert 'Cap_12f' in primitives.keys()
    with open(gen_const_path, "r") as const_fp:
        gen_const = json.load(const_fp)
    with open(gold_const_path, "r") as const_fp:
        gold_const = json.load(const_fp)
    assert gold_const == gen_const