def test_dont_constrain_clk():
# TODO Do not constrain clock connected devices
name = f'ckt_{get_test_id()}'.upper()
netlist = ota_six(name)
constraints = [{
"constraint": "PowerPorts",
"ports": ["VCCX"]
}, {
"constraint": "GroundPorts",
"ports": ["VSSX"]
}, {
"constraint": "ClockPorts",
"ports": ["vin"]
}]
example = build_example(name, netlist, constraints)
generate_hierarchy(example, name, out_path, False, pdk_path, False)
clean_data(name)
pass
def test_merge_parallel():
# TODO Do not identify array when setup set as false
name = f'ckt_{get_test_id()}'.upper()
netlist = ota_six(name)
constraints = [{
"constraint": "PowerPorts",
"ports": ["VCCX"]
}, {
"constraint": "GroundPorts",
"ports": ["VSSX"]
}, {
"constraint": "MergeParallelDevices",
"isTrue": False
}]
example = build_example(name, netlist, constraints)
generate_hierarchy(example, name, out_path, False, pdk_path, False)
clean_data(name)
pass
def test_dont_const():
name = f'ckt_{get_test_id()}'.upper()
netlist = ota_six(name)
constraints = [{
"constraint": "PowerPorts",
"ports": ["VCCX"]
}, {
"constraint": "GroundPorts",
"ports": ["VSSX"]
}, {
"constraint": "AutoConstraint",
"isTrue": False
}]
example = build_example(name, netlist, constraints)
generate_hierarchy(example, name, out_path, False, pdk_path, False)
gen_const_path = out_path / f'{name}.verilog.json'
with open(gen_const_path, "r") as fp:
gen_const = next(x for x in json.load(fp)['modules']
if x['name'] == name)["constraints"]
assert len(gen_const) == 3, f"{gen_const}"
clean_data(name)