def oprel(i):
to = i.misc['to']
if to is not None: return '*' + str(to)
return '.%+d' % i.operands[0].value
# main intel formats:
format_intel_default = (mnemo, opers)
format_intel_ptr = (mnemo, opsize, opers)
format_intel_str = (pfx, mnemo, opers)
format_intel_rel = (mnemo, oprel)
# formats:
IA32_Intel_formats = {
'ia32_strings': format_intel_str,
'ia32_mov_adr': format_intel_ptr,
'ia32_ptr_ib': format_intel_ptr,
'ia32_ptr_iwd': format_intel_ptr,
'ia32_rm8': format_intel_ptr,
'ia32_rm32': format_intel_ptr,
'ia32_imm_rel': format_intel_rel,
}
IA32_Intel = Formatter(IA32_Intel_formats)
IA32_Intel.default = format_intel_default
else:
res.append((Token.Register, '%s' % r))
res.append((Token.Literal, ','))
if len(res) > 0: res.pop()
return res
def target(i):
res = []
if i.operands:
r = i.operands[0]
if r._is_cst:
res.append((Token.Constant, '.%+d' % r.value))
elif r._is_mem:
res.append((Token.Memory, '@%s' % r.a))
else:
res.append((Token.Register, '%s' % r))
return res
format_sh2_default = (mnemo, operands)
SH2_full_formats = {
'sh2_branch': [mnemo, target],
'sh2_jsr_nn':
[mnemo, lambda i: [(Token.Memory, '@@(%s)' % i.operands[0].ptr)]],
}
SH2_full = Formatter(SH2_full_formats)
SH2_full.default = format_sh2_default
return subpc
def opadr(pos):
def subabs(i, pos=pos):
tgt = i.operands[pos]
return [(Token.Address, "*" + str(tgt))]
return subabs
def format_prepare(i):
L = oplist(0)(i)
l = opers(i, 1)
return L + [(Token.Literal, ", ")] + l
v850_full_formats = {
"v850_ld_st": [mnemo_ldst, opers],
"v850_br_cond": [mnemo_cond, opers],
"v850_cccc": [mnemo, cond_opers],
"v850_dispose": [mnemo, listjoin(opmem(0), oplist(1))],
"v850_prepare": [mnemo, format_prepare],
"v850_pcrel": [mnemo, pcrel(0)],
"v850_call": [mnemo, opadr(0)],
}
v850_full = Formatter(v850_full_formats)
v850_full.default = [mnemo, opers]
mn = "BREQ"
elif b == "N":
mn = "BRMI"
elif b == "V":
mn = "BRVS"
elif b == "S":
mn = "BRLT"
elif b == "H":
mn = "BRHS"
elif b == "T":
mn = "BRTS"
elif b == "I":
mn = "BRIE"
L = [(Token.Mnemonic, "%s" % (mn.lower()).ljust(12))]
L.extend(pcrel(1)(i))
return L
AVR_full_formats = {
"avr_default": [mnemo, opers],
"avr_ld": [mnemo, format_mem],
"avr_lax": [mnemo, listjoin(opmem(0), opreg(1))],
"avr_brc": [format_brc],
"avr_br": [mnemo, pcrel(0)],
"avr_noops": [mnemo],
"avr_call": [mnemo, opadr(0)],
}
AVR_full = Formatter(AVR_full_formats)
AVR_full.default = [mnemo, opers]
if not isinstance(op, str) and op._is_mem:
op = op.a
if op.base._is_eqn:
s = str(op)[1:-1]
ops.append(s)
continue
ops.append("%s" % op)
return ", ".join(ops)
default_format = [mnemo, opers]
Mostek_full_formats = {
"mostek_ld": default_format,
"mostek_arithmetic": default_format,
"mostek_gpa_cpuc": [mnemo],
"mostek_rotshift": default_format,
"mostek_bitset": default_format,
"mostek_jump": default_format,
"mostek_call": default_format,
"mostek_ret": default_format,
"mostek_rst": default_format,
"mostek_io": default_format,
}
Mostek_full = Formatter(Mostek_full_formats)
Mostek_full.default = default_format
GB_full = Mostek_full
for op in i.operands:
if not isinstance(op,str) and op._is_mem:
op = op.a
if op.base._is_eqn:
s = str(op)[1:-1]
ops.append(s)
continue
ops.append('%s'%op)
return ', '.join(ops)
default_format = [mnemo, opers]
Mostek_full_formats = {
'mostek_ld' : default_format,
'mostek_arithmetic': default_format,
'mostek_gpa_cpuc' : [mnemo],
'mostek_rotshift' : default_format,
'mostek_bitset' : default_format,
'mostek_jump' : default_format,
'mostek_call' : default_format,
'mostek_ret' : default_format,
'mostek_rst' : default_format,
'mostek_io' : default_format,
}
Mostek_full = Formatter(Mostek_full_formats)
Mostek_full.default = default_format
GB_full = Mostek_full
"sparc_Bicc": format_xb,
"call": format_call,
"jmpl": format_jmpl,
"rett": format_addr,
"t": format_t,
"sparc_rd_": [mnemo, LambdaTokenListJoin(", ", regs)],
"sparc_wr_": format_wr,
"stbar": [mnemo],
"flush": format_addr,
"sparc_Fpop1_group1": [mnemo, LambdaTokenListJoin(", ", regs)],
"sparc_Fpop1_group2": [mnemo, LambdaTokenListJoin(", ", regs)],
"sparc_Fpop2_": [mnemo, LambdaTokenListJoin(", ", regs)],
"sparc_Cpop": format_cpop,
}
SPARC_V8_full = Formatter(SPARC_V8_full_formats)
CONDB = {
0b1000: "ba",
0b0000: "bn",
0b1001: "bne",
0b0001: "be",
0b1010: "bg",
0b0010: "ble",
0b1011: "bge",
0b0011: "bl",
0b1100: "bgu",
0b0100: "bleu",
0b1101: "bcc",
0b0101: "bcs",
0b1110: "bpos",
assert a._is_eqn
l, r = a.l, a.r
if l == pc and i.address:
s.append('*%s' % (i.address + r))
else:
s.append('%s(%s)' % (r, l))
return ', '.join(s)
MSP430_full_formats = {
'msp430_doubleop': [mnemo, ops],
'msp430_singleop': [mnemo, ops],
'msp430_jumps': [mnemo_cond, ops],
}
MSP430_full = Formatter(MSP430_full_formats)
def MSP430_synthetic(null, i):
s = MSP430_full(i)
if i.mnemonic == 'ADDC' and i.operands[0] == 0:
return s.replace('addc', 'adc').replace('#0x0,', '')
if i.mnemonic == 'DADD' and i.operands[0] == 0:
return s.replace('dadd', 'dadc').replace('#0x0,', '')
if i.mnemonic == 'CMP' and i.operands[0] == 0:
return s.replace('cmp', 'tst').replace('#0x0,', '')
if i.mnemonic == 'MOV':
if i.operands[1] is pc:
return s.replace('mov', 'br').replace(',pc', '')
elif i.operands[0] == 0:
return s.replace('mov', 'clr').replace('#0x0,', '')
elif op.sf:
s.append((Token.Constant, "%+d" % op.value))
else:
s.append((Token.Constant, op.__str__()))
elif op._is_reg:
s.append((Token.Register, op.__str__()))
s.append((Token.Literal, ", "))
if len(s) > 0:
s.pop()
return s
def opers_pcr(i):
s = opers(i)
if i.misc["pc_ref"] is not None and i.address is not None:
adr = i.address + i.length + i.misc["pc_ref"].value
s[-1] = (Token.Address, "%s" % (adr))
return s
format_default = (mnemo, opers)
w65c02_full_formats = {
"w65c02_pcr": (mnemo, opers_pcr),
"w65c02_bb": (mnemo, opers_pcr),
}
w65c02_full = Formatter(w65c02_full_formats)
w65c02_full.default = format_default
m = i.mnemonic.lower()
if i.misc['postinc']: return m+'*+'
elif i.misc['postdec']: return m+'*-'
elif i.misc['preinc'] : return m+'+*'
return m
format_byte = [mnemo, op0, dest1, accessbank]
format_bit = [mnemo, op0, bitb, accessbank]
format_imm = [mnemo, op0]
format_rel = [mnemo, rel0]
format_call = [mnemo, adr]
PIC_full_formats = {
'byte_oriented': format_byte,
'bit_oriented' : format_bit,
'control' : format_imm,
'control_rel' : format_rel,
'noop' : [mnemo],
'tblrw' : [tblrw],
'literal' : format_imm,
'LFSR' : [mnemo, op0, op1],
'decode_movff' : [mnemo, op0, op1],
'CALL' : format_call,
'MOVWF' : [mnemo, op0, accessbank],
'CLRF' : [mnemo, op0, accessbank],
'MULWF' : [mnemo, op0, accessbank],
}
PIC_full = Formatter(PIC_full_formats)
to = i.misc['to']
if to is not None: return '*'+str(to)
if (i.address is not None) and i.operands[0]._is_cst:
v = i.address + i.operands[0].signextend(32) + i.length
i.misc['to'] = v
return '*'+str(v)
return '.%+d'%i.operands[0].value
# main intel formats:
format_intel_default = (mnemo,opers)
format_intel_ptr = (mnemo,opers)
format_intel_str = (pfx,mnemo,opers)
format_intel_rel = (mnemo,oprel)
# formats:
IA32_Intel_formats = {
'ia32_strings' : format_intel_str,
'ia32_mov_adr' : format_intel_ptr,
'ia32_ptr_ib' : format_intel_ptr,
'ia32_ptr_iwd' : format_intel_ptr,
'ia32_rm8' : format_intel_ptr,
'ia32_rm32' : format_intel_ptr,
'ia32_imm_rel' : format_intel_rel,
}
IA32_Intel = Formatter(IA32_Intel_formats)
IA32_Intel.default = format_intel_default
if i.address is None:
s[-1] = (Token.Address, ".%+d" % i.operands[-1])
else:
imm_ref = i.address + i.length + (i.operands[-1] * 8)
s[-1] = (Token.Address, "#%s" % (imm_ref))
return s
def opers_adr2(i):
s = opers(i)
if i.address is None:
s[-3] = (Token.Address, ".%+d" % i.operands[-2])
s[-1] = (Token.Address, ".%+d" % i.operands[-1])
else:
imm_ref1 = i.address + i.length * (i.operands[-2] + 1)
imm_ref2 = i.address + i.length * (i.operands[-1] + 1)
s[-3] = (Token.Address, "#%s" % (imm_ref1))
s[-1] = (Token.Address, "#%s" % (imm_ref2))
return s
format_default = (mnemo, opers)
eBPF_full_formats = {
"ebpf_jmp_": (mnemo, opers_adr),
"bpf_jmp_": (mnemo, opers_adr2),
}
eBPF_full = Formatter(eBPF_full_formats)
eBPF_full.default = format_default
def opers_rel(i):
s = opers(i)
if i.misc["imm_ref"] is None and i.address is not None:
imm_ref = composer([cst(0, 2), i.operands[-1], i.address[28:32]])
s[-1] = (Token.Address, "%s" % (imm_ref))
return s
format_default = (mnemo, opers)
MIPS_full_formats = {
"mips1_loadstore": (mnemo, opers_mem),
"mips1_jump_abs": (mnemo, opers),
"mips1_jump_rel": (mnemo, opers_rel),
"mips1_branch": (mnemo, opers_adr),
}
MIPS_full = Formatter(MIPS_full_formats)
MIPS_full.default = format_default
def MIPS_synthetic(null, i, toks=False):
s = MIPS_full(i, toks)
return MIPS_Synthetic_renaming(s, i)
def MIPS_Synthetic_renaming(s, i):
# TODO
return s
'A64_generic': format_default,
'A64_load_store': format_ld_st,
'A64_Bcond': format_B,
'A64_B': format_B,
'A64_CBx': format_CBx,
'A64_CCMx': format_CCMx,
'ASRV': ['asr '] + format_allregs,
'LSLV': ['lsl '] + format_allregs,
'LSRV': ['lsr '] + format_allregs,
'RORV': ['ror '] + format_allregs,
'ADD': [alias_ADD],
'SUB': [alias_SUB],
'AND': [alias_AND],
'BFM': [alias_BFM],
'SBFM': [alias_SBFM],
'UBFM': [alias_UBFM],
'CSINC': [alias_CSINC],
'CSINV': [alias_CSINV],
'CSNEG': [alias_CSNEG],
'EXTR': [alias_EXTR],
'HINT': [alias_HINT],
'MADD': [alias_MADD],
'SMADDL': [alias_SMADDL],
'MSUB': [alias_MSUB],
'ORR': [alias_ORR],
'ORN': [alias_ORN],
'SBC': [alias_SBC],
}
ARM_V8_full = Formatter(ARM_V8_full_formats)
return []
def intarg(i):
return [(Token.Constant, str(i.operands[0]))]
def adrarg(i):
loc = i.operands[0]
return [(Token.Address, str(loc))]
def relarg(i):
off = i.operands[0]
loc = i.address + i.length + off
return [(Token.Address, str(loc))]
DW_full_formats = {
'dw_op_0': [mnemo],
'dw_op_jmp': [mnemo, relarg],
'dw_op_1': [mnemo, intarg],
'dw_op_addr': [mnemo, adrarg],
'dw_op_lit': [mnemo_lit],
'dw_op_reg': [mnemo_reg],
'dw_op_breg': [mnemo_breg],
}
DW_full = Formatter(DW_full_formats)
DW_full.default = [mnemo, hexarg]
format_intel_str = (pfx, mnemo, opers)
format_intel_rel = (pfx, mnemo, oprel)
# intel formats:
IA32e_Intel_formats = {
"ia32_strings": format_intel_str,
"ia32_mov_adr": format_intel_ptr,
"ia32_ptr_ib": format_intel_ptr,
"ia32_ptr_iwd": format_intel_ptr,
"ia32_rm8": format_intel_ptr,
"ia32_rm32": format_intel_ptr,
"ia32_imm_rel": format_intel_rel,
}
IA32e_Intel = Formatter(IA32e_Intel_formats)
IA32e_Intel.default = format_intel_default
# ------------------------------------------------------------------------------
# AT&T formats:
def mnemo_att(i):
mnemo = i.mnemonic.replace("cc", "")
opdsz = i.misc["opdsz"]
if opdsz == 16:
mnemo += "w"
elif opdsz == 8:
mnemo += "b"
elif hasattr(i, "cond"):
mnemo += i.cond[0].split("/")[0]
format_intel_str = (pfx, mnemo, opers)
format_intel_rel = (pfx, mnemo, oprel)
# intel formats:
IA32_Intel_formats = {
'ia32_strings': format_intel_str,
'ia32_mov_adr': format_intel_ptr,
'ia32_ptr_ib': format_intel_ptr,
'ia32_ptr_iwd': format_intel_ptr,
'ia32_rm8': format_intel_ptr,
'ia32_rm32': format_intel_ptr,
'ia32_imm_rel': format_intel_rel,
}
IA32_Intel = Formatter(IA32_Intel_formats)
IA32_Intel.default = format_intel_default
#------------------------------------------------------------------------------
# AT&T formats:
def mnemo_att(i):
mnemo = i.mnemonic.replace('cc', '')
opdsz = i.misc['opdsz']
if opdsz == 16: mnemo += 'w'
elif opdsz == 8: mnemo += 'b'
elif hasattr(i, 'cond'):
mnemo += i.cond[0].split('/')[0]
return [(Token.Mnemonic, '{: <12}'.format(mnemo.lower()))]
s.append((Token.Constant, op.__str__()))
elif op._is_reg:
s.append((Token.Register, op.__str__().ljust(3, ' ')))
elif op._is_cmp:
s.append(
(Token.Register, "/".join(x.__str__()
for x in [op[0:32], op[32:64]])))
s.append((Token.Literal, ", "))
if len(s) > 0:
s.pop()
return s
def opers_adr(i):
s = opers(i)
if i.misc["imm_ref"] is None and i.address is not None:
imm_ref = i.address + i.operands[-1]
s[-1] = (Token.Address, "%s" % (imm_ref))
return s
format_default = (mnemo, opers)
tricore_full_formats = {
"tricore_branch": (mnemo, opers_adr),
"tricore_jcc": (mnemo, opers_adr),
}
TriCore_full = Formatter(tricore_full_formats)
TriCore_full.default = format_default
def opers_adr(i):
s = opers(i)
if i.misc['imm_ref'] is None and i.address is not None:
imm_ref = i.address+i.operands[-1]
s[-1] = (Token.Address,u'%s'%(imm_ref))
return s
format_default = (mnemo,opers)
RISCV_full_formats = {
'riscv_b' : (mnemo,opers_adr),
'riscv_jal': (mnemo,opers_adr),
}
RISCV_full = Formatter(RISCV_full_formats)
RISCV_full.default = format_default
def RISCV_synthetic(null,i,toks=False):
s = RISCV_full(i,toks)
return RISCV_Synthetic_renaming(s, i)
def RISCV_Synthetic_renaming(s, i):
if i.mnemonic=='jalr' and i.operands[0]==x[0] and i.operands[1]==x[1] and i.operands[2]==0:
return 'ret'
if i.mnemonic=='addi' and i.operands[0]==i.operands[1]==x[0] and i.operands[2]==0:
return 'nop'
if i.mnemonic=='addi' and i.operands[2]==0:
return s.replace('addi','mv').replace(', 0','')
if i.mnemonic=='xori' and i.operands[2]==-1:
return s.replace('xori','not').replace(', -1','')
