def execute(self, processor):
if processor.condition_passed():
address = bits_add(align(processor.registers.get_pc(), 4),
self.imm32, 32) if self.add else bits_sub(
align(processor.registers.get_pc(), 4),
self.imm32, 32)
processor.hint_preload_data(address)
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(15)
except EndOfInstruction:
pass
else:
address = bits_add(align(processor.registers.get_pc(), 4),
self.imm32, 32) if self.add else bits_sub(
align(processor.registers.get_pc(), 4),
self.imm32, 32)
if have_lpae() and address[29:32] == "0b000":
data = processor.mem_a_get(address, 8)
if processor.big_endian():
processor.registers.set(self.t, data[0:32])
processor.registers.set(self.t2, data[32:64])
else:
processor.registers.set(self.t, data[32:64])
processor.registers.set(self.t2, data[0:32])
else:
processor.registers.set(self.t,
processor.mem_a_get(address, 4))
processor.registers.set(
self.t2,
processor.mem_a_get(
bits_add(address, BitArray(bin="0b100"), 32), 4))
def execute(self, processor):
if processor.condition_passed():
if not processor.coproc_accepted(self.cp, processor.this_instr()):
processor.generate_coprocessor_exception()
else:
try:
processor.null_check_if_thumbee(15)
except EndOfInstruction:
pass
else:
offset_addr = bits_add(
align(processor.registers.get_pc(), 4), self.imm32,
32) if self.add else bits_sub(
align(processor.registers.get_pc(), 4), self.imm32,
32)
address = offset_addr if self.index else align(
processor.registers.get_pc(), 4)
first_pass = True
while first_pass or processor.coproc_done_loading(
self.cp, processor.this_instr()):
first_pass = False
processor.coproc_send_loaded_word(
processor.mem_a_get(address, 4), self.cp,
processor.this_instr())
address = bits_add(address, BitArray(bin="100"), 32)
def execute(self, processor):
if processor.condition_passed():
result = bits_add(align(processor.registers.get_pc(), 4),
self.imm32, 32) if self.add else bits_sub(
align(processor.registers.get_pc(), 4),
self.imm32, 32)
if self.d == 15:
processor.alu_write_pc(result)
else:
processor.registers.set(self.d, result)
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(15)
except EndOfInstruction:
pass
else:
base = align(processor.registers.get_pc(), 4)
address = bits_add(base, self.imm32,
32) if self.add else bits_sub(
base, self.imm32, 32)
data = processor.mem_u_get(address, 4)
if self.t == 15:
if lower_chunk(address, 2) == 0b00:
processor.load_write_pc(data)
else:
print('unpredictable')
elif processor.unaligned_support() or lower_chunk(address,
2) == 0b00:
processor.registers.set(self.t, data)
else:
if processor.registers.current_instr_set() == InstrSet.ARM:
processor.registers.set(
self.t, ror(data, 32, 8 * lower_chunk(address, 2)))
else:
processor.registers.set(self.t, 0x00000000) # unknown
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(15)
except EndOfInstruction:
pass
else:
pc = align(processor.registers.get_pc(), 4)
address = bits_add(pc, self.imm32,
32) if self.add else bits_sub(
pc, self.imm32, 32)
if have_lpae() and substring(address, 2, 0) == 0b000:
data = processor.mem_a_get(address, 8)
if processor.big_endian():
processor.registers.set(self.t,
substring(data, 63, 32))
processor.registers.set(self.t2,
substring(data, 31, 0))
else:
processor.registers.set(self.t, substring(data, 31, 0))
processor.registers.set(self.t2,
substring(data, 63, 32))
else:
processor.registers.set(self.t,
processor.mem_a_get(address, 4))
processor.registers.set(
self.t2,
processor.mem_a_get(bits_add(address, 4, 32), 4))
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(15)
except EndOfInstruction:
pass
else:
base = align(processor.registers.get_pc(), 4)
address = bits_add(base, self.imm32,
32) if self.add else bits_sub(
base, self.imm32, 32)
processor.registers.set(
self.t, zero_extend(processor.mem_u_get(address, 1), 32))
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(15)
except EndOfInstruction:
pass
else:
base = align(processor.registers.get_pc(), 4)
address = bits_add(base, self.imm32, 32) if self.add else bits_sub(base, self.imm32, 32)
data = processor.mem_u_get(address, 2)
if processor.unaligned_support() or not address[31]:
processor.registers.set(self.t, sign_extend(data, 32))
else:
processor.registers.set(self.t, BitArray(length=32)) # unkown
def execute(self, processor):
if processor.condition_passed():
if processor.registers.current_instr_set() == InstrSet.ARM:
processor.registers.set_lr(
sub(processor.registers.get_pc(), 4, 32))
else:
processor.registers.set_lr(processor.registers.get_pc() | 0b1)
if self.target_instr_set == InstrSet.ARM:
target_address = add(align(processor.registers.get_pc(), 4),
self.imm32, 32)
else:
target_address = add(processor.registers.get_pc(), self.imm32,
32)
processor.registers.select_instr_set(self.target_instr_set)
processor.branch_write_pc(target_address)
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(15)
except EndOfInstruction:
pass
else:
base = align(processor.registers.get_pc(), 4)
address = bits_add(base, self.imm32,
32) if self.add else bits_sub(
base, self.imm32, 32)
data = processor.mem_u_get(address, 2)
if processor.unaligned_support() or not bit_at(address, 0):
processor.registers.set(self.t, data)
else:
processor.registers.set(self.t, 0x00000000) # unknown
def execute(self, processor):
if processor.condition_passed():
try:
processor.null_check_if_thumbee(15)
except EndOfInstruction:
pass
else:
base = align(processor.registers.get_pc(), 4)
address = bits_add(base, self.imm32, 32) if self.add else bits_sub(base, self.imm32, 32)
data = processor.mem_u_get(address, 4)
if self.t == 15:
if address[30:32] == "0b00":
processor.load_write_pc(data)
else:
print "unpredictable"
elif processor.unaligned_support() or address[30:32] == "0b00":
processor.registers.set(self.t, data)
else:
if processor.registers.current_instr_set() == InstrSet.InstrSet_ARM:
processor.registers.set(self.t, ror(data, 8 * address[30:32].uint))
else:
processor.registers.set(self.t, BitArray(length=32)) # unknown
