def execute(self, processor): if processor.condition_passed(): rotated = ror(processor.registers.get(self.m), 32, self.rotation) processor.registers.set( self.d, add(processor.registers.get(self.n), sign_extend(lower_chunk(rotated, 8), 8, 32), 32) )
def execute(self, processor): if processor.condition_passed(): rotated = ror(processor.registers.get(self.m), 32, self.rotation) temp_rd = set_substring(0, 15, 0, substring(rotated, 7, 0)) temp_rd = set_substring(temp_rd, 31, 16, substring(rotated, 23, 16)) processor.registers.set(self.d, temp_rd)
def execute(self, processor): if processor.condition_passed(): if processor.registers.current_mode_is_hyp(): print "unpredictable" else: try: processor.null_check_if_thumbee(self.n) except EndOfInstruction: pass else: offset = shift(processor.registers.get( self.m), self.shift_t, self.shift_n, processor.registers.cpsr.get_c() ) if self.register_form else self.imm32 offset_addr = bits_add(processor.registers.get( self.n), offset, 32) if self.add else bits_sub( processor.registers.get(self.n), offset, 32) address = processor.registers.get( self.n) if self.post_index else offset_addr data = processor.mem_u_unpriv_get(address, 4) if self.post_index: processor.registers.set(self.n, offset_addr) if processor.unaligned_support( ) or address[30:32] == "0b00": processor.registers.set(self.t, data) else: if processor.registers.current_instr_set( ) == InstrSet.InstrSet_ARM: processor.registers.set( self.t, ror(data, 8 * address[30:32].uint)) else: processor.registers.set( self.t, BitArray(length=32)) # unknown
def execute(self, processor): if processor.condition_passed(): try: processor.null_check_if_thumbee(15) except EndOfInstruction: pass else: base = align(processor.registers.get_pc(), 4) address = bits_add(base, self.imm32, 32) if self.add else bits_sub( base, self.imm32, 32) data = processor.mem_u_get(address, 4) if self.t == 15: if lower_chunk(address, 2) == 0b00: processor.load_write_pc(data) else: print('unpredictable') elif processor.unaligned_support() or lower_chunk(address, 2) == 0b00: processor.registers.set(self.t, data) else: if processor.registers.current_instr_set() == InstrSet.ARM: processor.registers.set( self.t, ror(data, 32, 8 * lower_chunk(address, 2))) else: processor.registers.set(self.t, 0x00000000) # unknown
def execute(self, processor): if processor.condition_passed(): operand2 = ror(processor.registers.get(self.m), 32, 16) if self.m_swap else processor.registers.get(self.m) n = processor.registers.get(self.n) product1 = to_signed(substring(n, 15, 0), 16) * to_signed(substring(operand2, 15, 0), 16) product2 = to_signed(substring(n, 31, 16), 16) * to_signed(substring(operand2, 31, 16), 16) result = product1 + product2 processor.registers.set(self.d, to_unsigned(result, 32)) if result != to_signed(to_unsigned(result, 32), 32): processor.registers.cpsr.q = 1
def execute(self, processor): if processor.condition_passed(): rotated = ror(processor.registers.get(self.m), 32, self.rotation) n = processor.registers.get(self.n) lower_half = add(substring(n, 15, 0), substring(rotated, 7, 0), 16) temp_rd = set_substring(0, 15, 0, lower_half) upper_half = add(substring(n, 31, 16), substring(rotated, 23, 16), 16) temp_rd = set_substring(temp_rd, 31, 16, upper_half) processor.registers.set(self.d, temp_rd)
def execute(self, processor): if processor.condition_passed(): operand2 = ror(processor.registers.get(self.m), 32, 16) if self.m_swap else processor.registers.get( self.m) n = processor.registers.get(self.n) product1 = to_signed(substring(n, 15, 0), 16) * to_signed( substring(operand2, 15, 0), 16) product2 = to_signed(substring(n, 31, 16), 16) * to_signed( substring(operand2, 31, 16), 16) d_total = to_signed( set_substring(processor.registers.get(self.d_lo), 63, 32, processor.registers.get(self.d_hi)), 64) result = to_unsigned(product1 - product2 + d_total, 64) processor.registers.set(self.d_hi, substring(result, 63, 32)) processor.registers.set(self.d_lo, substring(result, 31, 0))
def execute(self, processor): if processor.condition_passed(): offset_addr = bits_add(processor.registers.get( self.n), self.imm32, 32) if self.add else bits_sub( processor.registers.get(self.n), self.imm32, 32) address = offset_addr if self.index else processor.registers.get( self.n) data = processor.mem_u_get(address, 4) if self.wback: processor.registers.set(self.n, offset_addr) if self.t == 15: if address[30:32] == "0b00": processor.load_write_pc(data) else: print "unpredictable" elif processor.unaligned_support() or address[30:32] == "0b00": processor.registers.set(self.t, data) else: processor.registers.set(self.t, ror(data, 8 * address[30:32].uint))
def execute(self, processor): if processor.condition_passed(): offset_addr = bits_add(processor.registers.get( self.n), self.imm32, 32) if self.add else bits_sub( processor.registers.get(self.n), self.imm32, 32) address = offset_addr if self.index else processor.registers.get( self.n) data = processor.mem_u_get(address, 4) if self.wback: processor.registers.set(self.n, offset_addr) if self.t == 15: if lower_chunk(address, 2) == 0b00: processor.load_write_pc(data) else: print('unpredictable') elif processor.unaligned_support() or lower_chunk(address, 2) == 0b00: processor.registers.set(self.t, data) else: processor.registers.set( self.t, ror(data, 32, 8 * lower_chunk(address, 2)))
def execute(self, processor): if processor.condition_passed(): offset = shift(processor.registers.get(self.m), 32, self.shift_t, self.shift_n, processor.registers.cpsr.c) n = processor.registers.get(self.n) offset_addr = (n + offset) if self.add else (n - offset) address = offset_addr if self.index else n data = processor.mem_u_get(address, 4) if self.wback: processor.registers.set(self.n, offset_addr) if self.t == 15: if substring(address, 1, 0) == 0b00: processor.load_write_pc(address) else: print('unpredictable') elif processor.unaligned_support() or substring(address, 1, 0) == 0b00: processor.registers.set(self.t, data) else: processor.registers.set( self.t, ror(data, 32, 8 * substring(address, 1, 0)))
def execute(self, processor): if processor.condition_passed(): try: processor.null_check_if_thumbee(15) except EndOfInstruction: pass else: base = align(processor.registers.get_pc(), 4) address = bits_add(base, self.imm32, 32) if self.add else bits_sub(base, self.imm32, 32) data = processor.mem_u_get(address, 4) if self.t == 15: if address[30:32] == "0b00": processor.load_write_pc(data) else: print "unpredictable" elif processor.unaligned_support() or address[30:32] == "0b00": processor.registers.set(self.t, data) else: if processor.registers.current_instr_set() == InstrSet.InstrSet_ARM: processor.registers.set(self.t, ror(data, 8 * address[30:32].uint)) else: processor.registers.set(self.t, BitArray(length=32)) # unknown
def execute(self, processor): if processor.condition_passed(): rotated = ror(processor.registers.get(self.m), 32, self.rotation) processor.registers.set(self.d, lower_chunk(rotated, 16))