def __init__(self, platform, sys_crg, jesd_crg, dac):
self.submodules.jesd = jesd204_tools.UltrascaleTX(
platform, sys_crg, jesd_crg, dac)
self.submodules.sawgs = [sawg.Channel(width=16, parallelism=4) for i in range(4)]
for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs):
assert len(Cat(ch.o)) == len(conv)
self.sync.jesd += conv.eq(Cat(ch.o))
def __init__(self, platform, sys_crg, jesd_crg, dac):
# Kintex Ultrascale GTH, speed grade -1C:
# CPLL linerate (D=1): 4.0 - 8.5 Gb/s
self.submodules.jesd = jesd204_tools.UltrascaleTX(
platform, sys_crg, jesd_crg, dac)
self.submodules.sawgs = [sawg.Channel(width=16, parallelism=4) for i in range(4)]
for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs):
assert len(Cat(ch.o)) == len(conv)
self.sync.jesd += conv.eq(Cat(ch.o))
def __init__(self, platform, sys_crg, jesd_crg, dac):
self.submodules.jesd = jesd204_tools.UltrascaleTX(
platform, sys_crg, jesd_crg, dac)
self.coarse_ts = Signal(32)
self.sawgs = []
ftw = round(2**len(self.coarse_ts) * 9e6 / 600e6)
parallelism = 4
mul_1 = Signal.like(self.coarse_ts)
mul_2 = Signal.like(self.coarse_ts)
mul_3 = Signal.like(self.coarse_ts)
self.sync.rtio += [
mul_1.eq(self.coarse_ts * ftw * parallelism),
mul_2.eq(mul_1),
mul_3.eq(mul_2)
]
phases = [Signal.like(self.coarse_ts) for i in range(parallelism)]
self.sync.rtio += [
phases[i].eq(mul_3 + i * ftw) for i in range(parallelism)
]
resolution = 10
steps = 2**resolution
from math import pi, cos
data = [
(2**16 + round(cos(i / steps * 2 * pi) * ((1 << 15) - 1))) & 0xffff
for i in range(steps)
]
samples = [Signal(16) for i in range(4)]
for phase, sample in zip(phases, samples):
table = Memory(16, steps, init=data)
table_port = table.get_port(clock_domain="rtio")
self.specials += table, table_port
self.comb += [
table_port.adr.eq(phase >> (len(self.coarse_ts) - resolution)),
sample.eq(table_port.dat_r)
]
self.sync.rtio += [
sink.eq(Cat(samples)) for sink in self.jesd.core.sink.flatten()
]
def __init__(self, platform, sys_crg, jesd_crg, dac):
self.submodules.jesd = jesd204_tools.UltrascaleTX(
platform, sys_crg, jesd_crg, dac)
self.sawgs = []
ramp = Signal(4)
self.sync.rtio += ramp.eq(ramp + 1)
samples = [[Signal(16) for i in range(4)] for j in range(4)]
self.comb += [
a.eq(Cat(b))
for a, b in zip(self.jesd.core.sink.flatten(), samples)
]
# ch0: 16-step ramp with big carry toggles
for i in range(4):
self.comb += [
samples[0][i][-4:].eq(ramp),
samples[0][i][:-4].eq(0x7ff if i % 2 else 0x800)
]
# ch1: 50 MHz
from math import pi, cos
data = [
int(round(cos(i / 12 * 2 * pi) * ((1 << 15) - 1)))
for i in range(12)
]
k = Signal(2)
self.sync.rtio += If(k == 2, k.eq(0)).Else(k.eq(k + 1))
self.comb += [
Case(
k, {
i: [samples[1][j].eq(data[i * 4 + j]) for j in range(4)]
for i in range(3)
})
]
# ch2: ch0, ch3: ch1
self.comb += [
Cat(samples[2]).eq(Cat(samples[0])),
Cat(samples[3]).eq(Cat(samples[1]))
]
