def __init__(self):
platform = self.platform
platform.add_extension(nist_qc2.fmc_adapter_io)
rtio_channels = []
clock_generators = []
# All TTL channels are In+Out capable
for i in range(40):
phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
# CLK0, CLK1 are for clock generators, on backplane SMP connectors
for i in range(2):
phy = ttl_simple.ClockGen(platform.request("clkout", i))
self.submodules += phy
clock_generators.append(rtio.Channel.from_phy(phy))
# user SMA on KC705 board
phy = ttl_serdes_7series.InOut_8X(
platform.request("user_sma_gpio_n_33"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# AMS101 DAC on KC705 XADC header - optional
ams101_dac = self.platform.request("ams101_dac", 0)
phy = ttl_simple.Output(ams101_dac.ldac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# add clock generators after TTLs
rtio_channels += clock_generators
phy = spi2.SPIMaster(ams101_dac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for i in range(4):
phy = spi2.SPIMaster(self.platform.request("spi", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))
for backplane_offset in range(2):
phy = dds.AD9914(platform.request("dds", backplane_offset),
12,
onehot=True)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
def __init__(self, *args, **kwargs):
_MasterBase.__init__(self, *args, **kwargs)
platform = self.platform
platform.add_extension(_dio("eem0"))
rtio_channels = []
phy = ttl_simple.Output(platform.request("user_led", 0))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for sc in self.sfp_ctl:
phy = ttl_simple.Output(sc.led)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in range(8):
pads = platform.request("eem0", i)
phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
def __init__(self, **kwargs):
_StandaloneBase.__init__(self, **kwargs)
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = "125.0"
platform = self.platform
platform.add_extension(_urukul("eem1", "eem0"))
platform.add_extension(_dio("eem2"))
platform.add_extension(_dio("eem3"))
platform.add_extension(_dio("eem4"))
platform.add_extension(_dio("eem5"))
platform.add_extension(_dio("eem6"))
# EEM clock fan-out from Si5324, not MMCX
self.comb += platform.request("clk_sel").eq(1)
# EEM2-6: TTL
rtio_channels = []
for i in range(40):
eem_offset, port = divmod(i, 8)
pads = platform.request("eem{}".format(2 + eem_offset), port)
phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# EEM0, EEM1: Urukul
phy = spi2.SPIMaster(self.platform.request("eem1_spi_p"),
self.platform.request("eem1_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = platform.request("eem1_dds_reset")
self.specials += DifferentialOutput(0, pads.p, pads.n)
for signal in "io_update sw0 sw1 sw2 sw3".split():
pads = platform.request("eem1_{}".format(signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in (1, 2):
sfp_ctl = platform.request("sfp_ctl", i)
phy = ttl_simple.Output(sfp_ctl.led)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
def __init__(self, *args, **kwargs):
_SatelliteBase.__init__(self, *args, **kwargs)
platform = self.platform
platform.add_extension(_dio("eem0"))
rtio_channels = []
phy = ttl_simple.Output(platform.request("user_led", 0))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in range(1, 3):
phy = ttl_simple.Output(platform.request("sfp_ctl", i).led)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in range(8):
pads = platform.request("eem0", i)
phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.add_rtio(rtio_channels)
def __init__(self, **kwargs):
_StandaloneBase.__init__(self, **kwargs)
platform = self.platform
platform.add_extension(nist_clock.fmc_adapter_io)
rtio_channels = []
for i in range(16):
if i % 4 == 3:
phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
else:
phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in range(2):
phy = ttl_serdes_7series.InOut_8X(platform.request("pmt", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
ams101_dac = self.platform.request("ams101_dac", 0)
phy = ttl_simple.Output(ams101_dac.ldac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = ttl_simple.ClockGen(platform.request("la32_p"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = spi2.SPIMaster(ams101_dac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ififo_depth=4))
for i in range(3):
phy = spi2.SPIMaster(self.platform.request("spi", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ififo_depth=128))
phy = spi2.SPIMaster(platform.request("sdcard_spi_33"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ififo_depth=4))
phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
def __init__(self, **kwargs):
_StandaloneBase.__init__(self, **kwargs)
platform = self.platform
platform.add_extension(nist_clock.fmc_adapter_io)
rtio_channels = []
for i in range(16):
if i % 4 == 3:
phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(
rtio.Channel.from_phy(phy, ififo_depth=512))
else:
phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in range(2):
phy = ttl_serdes_7series.InOut_8X(platform.request("pmt", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
phy = ttl_serdes_7series.InOut_8X(
platform.request("user_sma_gpio_n_33"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
ams101_dac = self.platform.request("ams101_dac", 0)
phy = ttl_simple.Output(ams101_dac.ldac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = ttl_simple.ClockGen(platform.request("la32_p"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = spi2.SPIMaster(ams101_dac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for i in range(3):
phy = spi2.SPIMaster(self.platform.request("spi", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))
phy = spi2.SPIMaster(platform.request("sdcard_spi_33"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
fmcdio_dirctl = self.platform.request("fmcdio_dirctl")
for s in fmcdio_dirctl.clk, fmcdio_dirctl.ser, fmcdio_dirctl.latch:
phy = ttl_simple.Output(s)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sdac_phy = spi2.SPIMaster(self.platform.request("zotino_spi_p"),
self.platform.request("zotino_spi_n"))
self.submodules += sdac_phy
rtio_channels.append(rtio.Channel.from_phy(sdac_phy, ififo_depth=4))
pads = platform.request("zotino_ldac")
ldac_phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += ldac_phy
rtio_channels.append(rtio.Channel.from_phy(ldac_phy))
dac_monitor = ad53xx_monitor.AD53XXMonitor(sdac_phy.rtlink,
ldac_phy.rtlink)
self.submodules += dac_monitor
sdac_phy.probes.extend(dac_monitor.probes)
phy = spi2.SPIMaster(self.platform.request("urukul_spi_p"),
self.platform.request("urukul_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for signal in "io_update dds_reset sw0 sw1 sw2 sw3".split():
pads = platform.request("urukul_{}".format(signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
def add_std(cls,
target,
fmc,
iostd_single,
iostd_diff,
with_trig=False,
adc_daq_samples=1024,
tdc_daq_samples=1024):
cls.add_extension(target, fmc, iostd_single, iostd_diff)
# CFD DAC I2C
dac_i2c = target.platform.request(cls.signal_name("dac_i2c", fmc))
bus_id = target.add_i2c_bus(dac_i2c.scl, dac_i2c.sda,
f"FMC{fmc} DAC I2C")
target.submodules.i2c = gpio.GPIOTristate([dac_i2c.scl, dac_i2c.sda])
target.csr_devices.append("i2c")
for i, address in enumerate([0x48, 0x49]):
target.register_coredevice(device_id=f"fmc{fmc}_cfd_offset_dac{i}",
module="elhep_cores.coredevice.dac7578",
class_name="DAC7578",
arguments={
"busno": 0,
"address": address << 1
}) # FIXME: use valid bus id
# IOs
for i in range(4):
pads = target.platform.request(cls.signal_name("tdc_dis", fmc), i)
phy = Output(pads.p, pads.n)
target.submodules += phy
target.add_rtio_channels(channel=rtio.Channel.from_phy(phy),
device_id=f"fmc{fmc}_tdc_dis{i}",
module="artiq.coredevice.ttl",
class_name="TTLOut")
for sn in [
"idx_in", "adc_resetn", "adc_sync", "trig_term", "trig_dir",
"ref_sel", "idx_src_sel"
]:
pads = target.platform.request(cls.signal_name(sn, fmc), 0)
if hasattr(pads, "p"):
phy = Output(pads.p, pads.n)
else:
phy = Output(pads)
target.submodules += phy
target.add_rtio_channels(channel=rtio.Channel.from_phy(phy),
device_id=f"fmc{fmc}_{sn}",
module="artiq.coredevice.ttl",
class_name="TTLOut")
# SPI Configuration interfaces
tdc_spi = target.platform.request(cls.signal_name("tdc_spi", fmc), 0)
tdc_spi_pads = Signal()
tdc_spi_pads.clk = tdc_spi.sck
tdc_spi_pads.miso = tdc_spi.miso
tdc_spi_pads.mosi = tdc_spi.mosi
tdc_spi_pads.cs_n = Signal(5)
phy = SPIMaster(tdc_spi_pads)
target.submodules += phy
target.add_rtio_channels(channel=rtio.Channel.from_phy(phy),
device_id=f"fmc{fmc}_tdc_spi",
module="artiq.coredevice.spi2",
class_name="SPIMaster")
adc_spi = target.platform.request(cls.signal_name("adc_spi", fmc), 0)
adc_spi_pads = Signal()
adc_spi_pads.clk = adc_spi.sck
adc_spi_pads.miso = adc_spi.miso
adc_spi_pads.mosi = adc_spi.mosi
adc_spi_pads.cs_n = Signal(2)
phy = SPIMaster(adc_spi_pads)
target.submodules += phy
target.add_rtio_channels(channel=rtio.Channel.from_phy(phy),
device_id=f"fmc{fmc}_adc_spi",
module="artiq.coredevice.spi2",
class_name="SPIMaster")
csn_pads = [
*[
target.platform.request(cls.signal_name("tdc_spi_csn", fmc), i)
for i in range(5)
], *[
target.platform.request(cls.signal_name("adc_spi_csn", fmc), i)
for i in range(2)
]
]
for i, pad in enumerate(csn_pads):
phy = Output(pad)
target.submodules += phy
target.add_rtio_channels(channel=rtio.Channel.from_phy(phy),
device_id=f"fmc{fmc}_csn{i}",
module="artiq.coredevice.ttl",
class_name="TTLOut")
# Clocking
target.register_coredevice(device_id=f"fmc{fmc}_clock_dist",
module="elhep_cores.coredevice.ad9528",
class_name="AD9528",
arguments={
"spi_device": f"fmc{fmc}_tdc_spi",
"chip_select": f"fmc{fmc}_csn4"
})
# ADC
for adc_id in range(2):
dclk_name = "fmc{}_adc{}_dclk".format(fmc, adc_id)
adc_lclk = target.platform.request(
cls.signal_name("adc_out_lclk", fmc), adc_id)
phy = ADS5296A_XS7(adclk_i=target.platform.request(
cls.signal_name("adc_out_adclk", fmc), adc_id),
lclk_i=adc_lclk,
dat_i=[
target.platform.request(
cls.signal_name(
"adc_out_out{}".format(i), fmc),
adc_id) for i in range(8)
])
target.platform.add_period_constraint(adc_lclk.p, 2.)
target.platform.add_period_constraint(phy.cd_adclk_clkdiv.clk, 10.)
target.platform.add_period_constraint(phy.lclk_bufio, 2.)
target.platform.add_period_constraint(phy.lclk, 10.)
phy_renamed_cd = ClockDomainsRenamer({"adclk_clkdiv":
dclk_name})(phy)
setattr(target.submodules, "fmc{}_adc{}_phy".format(fmc, adc_id),
phy_renamed_cd)
target.add_rtio_channels(
channel=rtio.Channel.from_phy(phy.csr),
device_id=f"fmc{fmc}_adc{adc_id}_phycsr",
module="elhep_cores.coredevice.rtlink_csr",
class_name="RtlinkCsr",
arguments={"regs": phy.csr.regs})
target.register_coredevice(
device_id=f"fmc{fmc}_adc{adc_id}_control",
module="elhep_cores.coredevice.ads5296a",
class_name="ADS5296A",
arguments={
"spi_device": f"fmc{fmc}_adc_spi",
"phy_csr": f"fmc{fmc}_adc{adc_id}_phycsr",
"chip_select": f"fmc{fmc}_csn{adc_id+5}",
"spi_freq": 500_000
})
# TDC
for tdc_id in range(4):
dclk_name = "fmc{}_tdc{}_dclk".format(fmc, tdc_id)
fs = [
target.platform.request(
cls.signal_name("tdc_out_frame{}".format(i), fmc), tdc_id)
for i in range(4)
]
ds = [
target.platform.request(
cls.signal_name("tdc_out_sdo{}".format(i), fmc), tdc_id)
for i in range(4)
]
phy = TdcGpx2Phy(data_clk_i=target.platform.request(
cls.signal_name("tdc_out_lclkout", fmc), tdc_id),
frame_signals_i=fs,
data_signals_i=ds)
target.platform.add_period_constraint(phy.cd_dclk.clk, 4.)
phy_renamed_cd = ClockDomainsRenamer({"dclk": dclk_name})(phy)
setattr(target.submodules, "fmc{}_tdc{}_phy".format(fmc, tdc_id),
phy_renamed_cd)
for idx, channel in enumerate(phy.phy_channels):
target.add_rtio_channels(
channel=rtio.Channel.from_phy(channel.csr),
device_id=f"fmc{fmc}_tdc{tdc_id}_phycsr_{idx}",
module="elhep_cores.coredevice.rtlink_csr",
class_name="RtlinkCsr",
arguments={"regs": channel.csr.regs})
target.register_coredevice(
device_id=f"fmc{fmc}_tdc{tdc_id}_control",
module="elhep_cores.coredevice.tdc_gpx2",
class_name="TDCGPX2",
arguments={
"spi_device": f"fmc{fmc}_tdc_spi",
"phy_csr_prefix": f"fmc{fmc}_tdc{tdc_id}_phycsr_",
"chip_select": f"fmc{fmc}_csn{tdc_id+0}",
"spi_freq": 1_000_000
})
if with_trig:
pads = target.platform.request(cls.signal_name("trig", fmc))
phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n)
target.submodules += phy
target.add_rtio_channels(channel=rtio.Channel.from_phy(
phy, ififo_depth=64),
device_id=f"fmc{fmc}_trig",
module="artiq.coredevice.ttl",
class_name="TTLInOut")
# Frequency counters
clk0_m2c_pads = target.platform.request(f"fmc{fmc}_clk0_m2c")
phy_clk0_m2c = Input(clk0_m2c_pads.p, clk0_m2c_pads.n)
clk0_m2c_edge_counter = SimpleEdgeCounter(phy_clk0_m2c.input_state)
target.submodules += [phy_clk0_m2c, clk0_m2c_edge_counter]
target.add_rtio_channels(channel=rtio.Channel.from_phy(phy_clk0_m2c),
device_id=f"fmc{fmc}_clk0_m2c_ttl_input",
module="artiq.coredevice.ttl",
class_name="TTLInOut")
target.add_rtio_channels(
channel=rtio.Channel.from_phy(clk0_m2c_edge_counter),
device_id=f"fmc{fmc}_clk0_m2c_edge_counter",
module="artiq.coredevice.edge_counter",
class_name="EdgeCounter")
clk1_m2c_pads = target.platform.request(f"fmc{fmc}_clk1_m2c")
phy_clk1_m2c = Input(clk1_m2c_pads.p, clk1_m2c_pads.n)
clk1_m2c_edge_counter = SimpleEdgeCounter(phy_clk1_m2c.input_state)
target.submodules += [phy_clk1_m2c, clk1_m2c_edge_counter]
target.add_rtio_channels(channel=rtio.Channel.from_phy(phy_clk1_m2c),
device_id=f"fmc{fmc}_clk1_m2c_ttl_input",
module="artiq.coredevice.ttl",
class_name="TTLInOut")
target.add_rtio_channels(
channel=rtio.Channel.from_phy(clk1_m2c_edge_counter),
device_id=f"fmc{fmc}_clk1_m2c_edge_counter",
module="artiq.coredevice.edge_counter",
class_name="EdgeCounter")
# Debug counters
for adc_id in range(2):
adc_phy = getattr(target, f"fmc{fmc}_adc{adc_id}_phy")
phy_adc_lclk = Input(adc_phy.lclk)
phy_adc_lclk_counter = SimpleEdgeCounter(phy_adc_lclk.input_state)
target.submodules += [phy_adc_lclk, phy_adc_lclk_counter]
target.add_rtio_channels(
channel=rtio.Channel.from_phy(phy_adc_lclk),
device_id=f"fmc{fmc}_phy_adc{adc_id}_lclk_input",
module="artiq.coredevice.ttl",
class_name="TTLInOut")
target.add_rtio_channels(
channel=rtio.Channel.from_phy(phy_adc_lclk_counter),
device_id=f"fmc{fmc}_phy_adc{adc_id}_lclk_counter",
module="artiq.coredevice.edge_counter",
class_name="EdgeCounter")
# Register itself
target.register_coredevice(
device_id=f"fmc{fmc}",
module="elhep_cores.coredevice.fmc_adc100M_10b_tdc_16cha",
class_name="FmcAdc100M10bTdc16cha",
arguments={"prefix": "fmc1"})
def __init__(self, hw_rev=None, **kwargs):
if hw_rev is None:
hw_rev = "v1.1"
_StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = "125.0"
platform = self.platform
# TODO: grabber on eem0->eemB eem1->eemA
platform.add_extension(_urukul("eem3", "eem2"))
platform.add_extension(_dio("eem4"))
platform.add_extension(_zotino("eem5"))
platform.add_extension(_zotino("eem6"))
# EEM4: TTL
rtio_channels = []
for i in range(8):
pads = platform.request("eem4", i)
phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# EEM2, EEM3: Urukul
phy = spi2.SPIMaster(self.platform.request("eem3_spi_p"),
self.platform.request("eem3_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = platform.request("eem3_dds_reset")
self.specials += DifferentialOutput(0, pads.p, pads.n)
for signal in "io_update sw0 sw1 sw2 sw3".split():
pads = platform.request("eem3_{}".format(signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# EEM5, EEM6: Zotino
for i in (5, 6):
phy = spi2.SPIMaster(
self.platform.request("eem{}_spi_p".format(i)),
self.platform.request("eem{}_spi_n".format(i)))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
for signal in "ldac_n clr_n".split():
pads = platform.request("eem{}_{}".format(i, signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in (1, 2):
sfp_ctl = platform.request("sfp_ctl", i)
phy = ttl_simple.Output(sfp_ctl.led)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
def __init__(self, cpu_type="or1k", **kwargs):
MiniSoC.__init__(self,
cpu_type=cpu_type,
sdram_controller_type="minicon",
l2_size=128 * 1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
self.platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
])
platform = self.platform
platform.add_extension(ad9154_fmc_ebz)
self.submodules.leds = gpio.GPIOOut(
Cat(platform.request("user_led", 0),
platform.request("user_led", 1)))
self.csr_devices.append("leds")
i2c = platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
ad9154_spi = platform.request("ad9154_spi")
self.comb += ad9154_spi.en.eq(1)
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
self.csr_devices.append("converter_spi")
self.config["HAS_AD9516"] = None
self.config["CONVERTER_SPI_AD9516_CS"] = 1
self.config["CONVERTER_SPI_FIRST_AD9154_CS"] = 0
self.submodules.ad9154_0 = AD9154(platform)
self.csr_devices.append("ad9154_0")
self.config["HAS_AD9154"] = None
self.add_csr_group("ad9154", ["ad9154_0"])
rtio_channels = []
phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sysref_pads = platform.request("ad9154_sysref")
phy = ttl_serdes_7series.Input_8X(sysref_pads.p, sysref_pads.n)
self.submodules += phy
rtio_channels.append(
rtio.Channel.from_phy(phy, ififo_depth=32, ofifo_depth=2))
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(
rtio.Channel.from_phy(phy) for sawg in self.ad9154_0.sawgs
for phy in sawg.phys)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.submodules.rtio_crg = _PhaserCRG(platform,
self.ad9154_0.jesd.cd_jesd.clk)
self.csr_devices.append("rtio_crg")
self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri], [self.rtio_core.cri])
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = rtio.Analyzer(
self.rtio_core.cri, self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.rtio_crg.cd_rtio.clk)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ad9154_0.jesd.cd_jesd.clk)
for phy in self.ad9154_0.jesd.phys:
platform.add_false_path_constraints(self.crg.cd_sys.clk,
phy.transmitter.cd_tx.clk)
