def __init__(self, **kwargs): _SatelliteBase.__init__(self, **kwargs) self.rtio_channels = [] phy = ttl_serdes_7series.Output_8X( self.platform.request("allaki0_rfsw0")) self.submodules += phy self.rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_serdes_7series.Output_8X( self.platform.request("allaki0_rfsw1")) self.submodules += phy self.rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_rtio(self.rtio_channels)
def __init__(self, **kwargs): _StandaloneBase.__init__(self, **kwargs) platform = self.platform platform.add_extension(_dio("eem0")) platform.add_extension(_dio("eem1")) platform.add_extension(_dio("eem2")) # platform.add_extension(_urukul("eem3", "eem4")) # platform.add_extension(_novogorny("eem5")) # EEM clock fan-out from Si5324, not MMCX self.comb += platform.request("clk_sel").eq(1) rtio_channels = [] for eem in "eem0 eem1 eem2".split(): for i in range(8): phy = ttl_serdes_7series.Output_8X(platform.request(eem, i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in (1, 2): sfp_ctl = platform.request("sfp_ctl", i) phy = ttl_simple.Output(sfp_ctl.led) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels)
def __init__(self, **kwargs): _SatelliteBase.__init__(self, **kwargs) platform = self.platform rtio_channels = [] phy = ttl_serdes_7series.Output_8X(platform.request("allaki0_rfsw0")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_serdes_7series.Output_8X(platform.request("allaki0_rfsw1")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_rtio(rtio_channels) # HMC clock chip and DAC control self.comb += [ platform.request("ad9154_rst_n", 0).eq(1), platform.request("ad9154_rst_n", 1).eq(1) ] self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface( platform.request("hmc_spi"), platform.request("ad9154_spi", 0), platform.request("ad9154_spi", 1))) self.csr_devices.append("converter_spi") self.submodules.hmc7043_reset = gpio.GPIOOut( platform.request("hmc7043_reset"), reset_out=1) self.csr_devices.append("hmc7043_reset") self.submodules.hmc7043_gpo = gpio.GPIOIn( platform.request("hmc7043_gpo")) self.csr_devices.append("hmc7043_gpo") self.config["HAS_HMC830_7043"] = None self.config["HAS_AD9154"] = None self.config["AD9154_COUNT"] = 2 self.config["CONVERTER_SPI_HMC830_CS"] = 0 self.config["CONVERTER_SPI_HMC7043_CS"] = 1 self.config["CONVERTER_SPI_FIRST_AD9154_CS"] = 2 self.config["HMC830_REF"] = "150" # HMC workarounds self.comb += platform.request("hmc830_pwr_en").eq(1) self.submodules.hmc7043_out_en = gpio.GPIOOut( platform.request("hmc7043_out_en")) self.csr_devices.append("hmc7043_out_en")
def __init__(self, **kwargs): _StandaloneBase.__init__(self, **kwargs) self.config["SI5324_AS_SYNTHESIZER"] = None self.config["RTIO_FREQUENCY"] = "125.0" platform = self.platform platform.add_extension(_urukul("eem1", "eem0")) platform.add_extension(_dio("eem2")) platform.add_extension(_dio("eem3")) platform.add_extension(_dio("eem4")) platform.add_extension(_dio("eem5")) platform.add_extension(_dio("eem6")) # EEM clock fan-out from Si5324, not MMCX self.comb += platform.request("clk_sel").eq(1) # EEM2-6: TTL rtio_channels = [] for i in range(40): eem_offset, port = divmod(i, 8) pads = platform.request("eem{}".format(2 + eem_offset), port) phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) # EEM0, EEM1: Urukul phy = spi2.SPIMaster(self.platform.request("eem1_spi_p"), self.platform.request("eem1_spi_n")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) pads = platform.request("eem1_dds_reset") self.specials += DifferentialOutput(0, pads.p, pads.n) for signal in "io_update sw0 sw1 sw2 sw3".split(): pads = platform.request("eem1_{}".format(signal)) phy = ttl_serdes_7series.Output_8X(pads.p, pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in (1, 2): sfp_ctl = platform.request("sfp_ctl", i) phy = ttl_simple.Output(sfp_ctl.led) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels)
def __init__(self, cpu_type="or1k", **kwargs): _NIST_Ions.__init__(self, cpu_type, **kwargs) platform = self.platform platform.add_extension(nist_qc1.fmc_adapter_io) self.comb += [ platform.request("ttl_l_tx_en").eq(1), platform.request("ttl_h_tx_en").eq(1) ] rtio_channels = [] for i in range(2): phy = ttl_serdes_7series.Inout_8X(platform.request("pmt", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) for i in range(15): phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) phy = ttl_simple.Output(platform.request("user_led", 2)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) phy = ttl_simple.ClockGen(platform.request("ttl", 15)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels) self.config["RTIO_DDS_COUNT"] = 1 self.config["DDS_CHANNELS_PER_BUS"] = 8 self.config["DDS_AD9858"] = True phy = dds.AD9858(platform.request("dds"), 8) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=512, ififo_depth=4)) self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels) assert self.rtio.fine_ts_width <= 3 self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width
def __init__(self, platform, cpu_type="or1k", **kwargs): _NIST_QCx.__init__(self, platform, cpu_type, **kwargs) platform.add_extension(nist_qc2.fmc_adapter_io) rtio_channels = [] for i in range(16): if i == 14: # TTL14 is for the clock generator continue if i % 4 == 3: phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) else: phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.Inout(platform.request("user_sma_gpio_n")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.Output(platform.request("user_led", 2)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_constant("RTIO_REGULAR_TTL_COUNT", len(rtio_channels)) phy = ttl_simple.ClockGen(platform.request("ttl", 14)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels)) self.add_constant("DDS_CHANNEL_COUNT", 11) self.add_constant("DDS_AD9914") self.add_constant("DDS_ONEHOT_SEL") phy = dds.AD9914(platform.request("dds"), 11, onehot=True) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=512, ififo_depth=4)) self.add_rtio(rtio_channels)
def __init__(self, platform, cpu_type="or1k", **kwargs): _NIST_QCx.__init__(self, platform, cpu_type, **kwargs) platform.add_extension(nist_qc1.fmc_adapter_io) self.comb += [ platform.request("ttl_l_tx_en").eq(1), platform.request("ttl_h_tx_en").eq(1) ] rtio_channels = [] for i in range(2): phy = ttl_serdes_7series.Inout_8X(platform.request("pmt", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) for i in range(15): phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.Inout(platform.request("user_sma_gpio_n")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.Output(platform.request("user_led", 2)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_constant("RTIO_REGULAR_TTL_COUNT", len(rtio_channels)) phy = ttl_simple.ClockGen(platform.request("ttl", 15)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels)) self.add_constant("DDS_CHANNEL_COUNT", 8) self.add_constant("DDS_AD9858") phy = dds.AD9858(platform.request("dds"), 8) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=512, ififo_depth=4)) self.add_rtio(rtio_channels)
def __init__(self, **kwargs): _StandaloneBase.__init__(self, **kwargs) platform = self.platform platform.add_extension(nist_clock.fmc_adapter_io) rtio_channels = [] for i in range(16): if i % 4 == 3: phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) else: phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in range(2): phy = ttl_serdes_7series.InOut_8X(platform.request("pmt", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) phy = ttl_simple.Output(platform.request("user_led", 2)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) ams101_dac = self.platform.request("ams101_dac", 0) phy = ttl_simple.Output(ams101_dac.ldac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.ClockGen(platform.request("la32_p")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = spi2.SPIMaster(ams101_dac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( phy, ififo_depth=4)) for i in range(3): phy = spi2.SPIMaster(self.platform.request("spi", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( phy, ififo_depth=128)) phy = spi2.SPIMaster(platform.request("sdcard_spi_33")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( phy, ififo_depth=4)) phy = dds.AD9914(platform.request("dds"), 11, onehot=True) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels)
def __init__(self, **kwargs): _SatelliteBase.__init__(self, **kwargs) platform = self.platform rtio_channels = [] for bm in range(2): print("BaseMod{} RF switches starting at RTIO channel 0x{:06x}" .format(bm, len(rtio_channels))) for i in range(4): phy = ttl_serdes_7series.Output_8X(platform.request("basemod{}_rfsw".format(bm), i), invert=True) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) print("BaseMod{} attenuator starting at RTIO channel 0x{:06x}" .format(bm, len(rtio_channels))) basemod_att = platform.request("basemod{}_att".format(bm)) for name in "rst_n clk le".split(): signal = getattr(basemod_att, name) for i in range(len(signal)): phy = ttl_simple.Output(signal[i]) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.Output(basemod_att.mosi[0]) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in range(3): self.comb += basemod_att.mosi[i+1].eq(basemod_att.miso[i]) phy = ttl_simple.InOut(basemod_att.miso[3]) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_rtio(rtio_channels) self.comb += platform.request("clk_src_ext_sel").eq(0) # HMC clock chip and DAC control self.comb += [ platform.request("ad9154_rst_n", 0).eq(1), platform.request("ad9154_rst_n", 1).eq(1) ] self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface( platform.request("hmc_spi"), platform.request("ad9154_spi", 0), platform.request("ad9154_spi", 1))) self.csr_devices.append("converter_spi") self.submodules.hmc7043_reset = gpio.GPIOOut( platform.request("hmc7043_reset"), reset_out=1) self.csr_devices.append("hmc7043_reset") self.submodules.hmc7043_gpo = gpio.GPIOIn( platform.request("hmc7043_gpo")) self.csr_devices.append("hmc7043_gpo") self.config["HAS_HMC830_7043"] = None self.config["HAS_AD9154"] = None self.config["AD9154_COUNT"] = 2 self.config["CONVERTER_SPI_HMC830_CS"] = 0 self.config["CONVERTER_SPI_HMC7043_CS"] = 1 self.config["CONVERTER_SPI_FIRST_AD9154_CS"] = 2 self.config["HMC830_REF"] = str(int(self.rtio_clk_freq/1e6)) # HMC workarounds self.comb += platform.request("hmc830_pwr_en").eq(1) self.submodules.hmc7043_out_en = gpio.GPIOOut( platform.request("hmc7043_out_en")) self.csr_devices.append("hmc7043_out_en") # DDMTD sysref_pads = platform.request("rtm_fpga_sysref", 0) self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(sysref_pads, self.rtio_clk_freq) self.csr_devices.append("sysref_ddmtd") platform.add_false_path_constraints( self.sysref_ddmtd.cd_helper.clk, self.drtio_transceiver.gtps[0].txoutclk) platform.add_false_path_constraints( self.sysref_ddmtd.cd_helper.clk, self.crg.cd_sys.clk)
def __init__(self, **kwargs): _StandaloneBase.__init__(self, **kwargs) platform = self.platform platform.add_extension(nist_clock.fmc_adapter_io) rtio_channels = [] for i in range(16): if i % 4 == 3: phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append( rtio.Channel.from_phy(phy, ififo_depth=512)) else: phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in range(2): phy = ttl_serdes_7series.InOut_8X(platform.request("pmt", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) phy = ttl_serdes_7series.InOut_8X( platform.request("user_sma_gpio_n_33")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) phy = ttl_simple.Output(platform.request("user_led", 2)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) ams101_dac = self.platform.request("ams101_dac", 0) phy = ttl_simple.Output(ams101_dac.ldac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.ClockGen(platform.request("la32_p")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = spi2.SPIMaster(ams101_dac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) for i in range(3): phy = spi2.SPIMaster(self.platform.request("spi", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128)) phy = spi2.SPIMaster(platform.request("sdcard_spi_33")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) fmcdio_dirctl = self.platform.request("fmcdio_dirctl") for s in fmcdio_dirctl.clk, fmcdio_dirctl.ser, fmcdio_dirctl.latch: phy = ttl_simple.Output(s) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) sdac_phy = spi2.SPIMaster(self.platform.request("zotino_spi_p"), self.platform.request("zotino_spi_n")) self.submodules += sdac_phy rtio_channels.append(rtio.Channel.from_phy(sdac_phy, ififo_depth=4)) pads = platform.request("zotino_ldac") ldac_phy = ttl_serdes_7series.Output_8X(pads.p, pads.n) self.submodules += ldac_phy rtio_channels.append(rtio.Channel.from_phy(ldac_phy)) dac_monitor = ad53xx_monitor.AD53XXMonitor(sdac_phy.rtlink, ldac_phy.rtlink) self.submodules += dac_monitor sdac_phy.probes.extend(dac_monitor.probes) phy = spi2.SPIMaster(self.platform.request("urukul_spi_p"), self.platform.request("urukul_spi_n")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) for signal in "io_update dds_reset sw0 sw1 sw2 sw3".split(): pads = platform.request("urukul_{}".format(signal)) phy = ttl_serdes_7series.Output_8X(pads.p, pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = dds.AD9914(platform.request("dds"), 11, onehot=True) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels)
def __init__(self, **kwargs): _StandaloneBase.__init__(self, **kwargs) self.config["SI5324_AS_SYNTHESIZER"] = None # self.config["SI5324_EXT_REF"] = None self.config["RTIO_FREQUENCY"] = "125.0" platform = self.platform platform.add_extension(_dio("eem0")) platform.add_extension(_dio("eem1")) platform.add_extension(_dio("eem2")) platform.add_extension(_novogorny("eem3")) platform.add_extension(_urukul("eem5", "eem4")) platform.add_extension(_urukul("eem6")) platform.add_extension(_zotino("eem7")) # EEM clock fan-out from Si5324, not MMCX try: self.comb += platform.request("clk_sel").eq(1) except ConstraintError: pass rtio_channels = [] for i in range(24): eem, port = divmod(i, 8) pads = platform.request("eem{}".format(eem), port) if i < 4: cls = ttl_serdes_7series.InOut_8X else: cls = ttl_serdes_7series.Output_8X phy = cls(pads.p, pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) # EEM3: Novogorny phy = spi2.SPIMaster(self.platform.request("eem3_spi_p"), self.platform.request("eem3_spi_n")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=16)) for signal in "conv".split(): pads = platform.request("eem3_{}".format(signal)) phy = ttl_serdes_7series.Output_8X(pads.p, pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) # EEM5 + EEM4: Urukul phy = spi2.SPIMaster(self.platform.request("eem5_spi_p"), self.platform.request("eem5_spi_n")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) pads = platform.request("eem5_dds_reset") self.specials += DifferentialOutput(0, pads.p, pads.n) for signal in "io_update sw0 sw1 sw2 sw3".split(): pads = platform.request("eem5_{}".format(signal)) phy = ttl_serdes_7series.Output_8X(pads.p, pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in (1, 2): sfp_ctl = platform.request("sfp_ctl", i) phy = ttl_simple.Output(sfp_ctl.led) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) # EEM6: Urukul phy = spi2.SPIMaster(self.platform.request("eem6_spi_p"), self.platform.request("eem6_spi_n")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) for signal in "io_update".split(): pads = platform.request("eem6_{}".format(signal)) phy = ttl_serdes_7series.Output_8X(pads.p, pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) pads = platform.request("eem6_dds_reset") self.specials += DifferentialOutput(0, pads.p, pads.n) # EEM7: Zotino phy = spi2.SPIMaster(self.platform.request("eem7_spi_p"), self.platform.request("eem7_spi_n")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) for signal in "ldac_n clr_n".split(): pads = platform.request("eem7_{}".format(signal)) phy = ttl_serdes_7series.Output_8X(pads.p, pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels)
def __init__(self, cpu_type="or1k", **kwargs): _NIST_Ions.__init__(self, cpu_type, **kwargs) platform = self.platform platform.add_extension(nist_clock.fmc_adapter_io) rtio_channels = [] for i in range(16): if i % 4 == 3: phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append( rtio.Channel.from_phy(phy, ififo_depth=512)) else: phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in range(2): phy = ttl_serdes_7series.Inout_8X(platform.request("pmt", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) phy = ttl_serdes_7series.Inout_8X( platform.request("user_sma_gpio_n_33")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) phy = ttl_simple.Output(platform.request("user_led", 2)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) ams101_dac = self.platform.request("ams101_dac", 0) phy = ttl_simple.Output(ams101_dac.ldac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) phy = ttl_simple.ClockGen(platform.request("la32_p")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = spi.SPIMaster(ams101_dac) self.submodules += phy self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels) rtio_channels.append( rtio.Channel.from_phy(phy, ofifo_depth=4, ififo_depth=4)) for i in range(3): phy = spi.SPIMaster(self.platform.request("spi", i)) self.submodules += phy rtio_channels.append( rtio.Channel.from_phy(phy, ofifo_depth=128, ififo_depth=128)) self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels) self.config["RTIO_DDS_COUNT"] = 1 self.config["DDS_CHANNELS_PER_BUS"] = 11 phy = dds.AD9914(platform.request("dds"), 11, onehot=True) self.submodules += phy rtio_channels.append( rtio.Channel.from_phy(phy, ofifo_depth=512, ififo_depth=4)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels)
def __init__(self, hw_rev=None, **kwargs): if hw_rev is None: hw_rev = "v1.1" _StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs) self.config["SI5324_AS_SYNTHESIZER"] = None self.config["RTIO_FREQUENCY"] = "125.0" platform = self.platform # TODO: grabber on eem0->eemB eem1->eemA platform.add_extension(_urukul("eem3", "eem2")) platform.add_extension(_dio("eem4")) platform.add_extension(_zotino("eem5")) platform.add_extension(_zotino("eem6")) # EEM4: TTL rtio_channels = [] for i in range(8): pads = platform.request("eem4", i) phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) # EEM2, EEM3: Urukul phy = spi2.SPIMaster(self.platform.request("eem3_spi_p"), self.platform.request("eem3_spi_n")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) pads = platform.request("eem3_dds_reset") self.specials += DifferentialOutput(0, pads.p, pads.n) for signal in "io_update sw0 sw1 sw2 sw3".split(): pads = platform.request("eem3_{}".format(signal)) phy = ttl_serdes_7series.Output_8X(pads.p, pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) # EEM5, EEM6: Zotino for i in (5, 6): phy = spi2.SPIMaster( self.platform.request("eem{}_spi_p".format(i)), self.platform.request("eem{}_spi_n".format(i))) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) for signal in "ldac_n clr_n".split(): pads = platform.request("eem{}_{}".format(i, signal)) phy = ttl_serdes_7series.Output_8X(pads.p, pads.n) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in (1, 2): sfp_ctl = platform.request("sfp_ctl", i) phy = ttl_simple.Output(sfp_ctl.led) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) self.add_rtio(rtio_channels)
def __init__(self, **kwargs): _SatelliteBase.__init__(self, **kwargs) platform = self.platform rtio_channels = [] for bm in range(2): print("BaseMod{} RF switches starting at RTIO channel 0x{:06x}". format(bm, len(rtio_channels))) for i in range(4): phy = ttl_serdes_7series.Output_8X(platform.request( "basemod{}_rfsw".format(bm), i), invert=True) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) print("BaseMod{} attenuator starting at RTIO channel 0x{:06x}". format(bm, len(rtio_channels))) basemod_att = platform.request("basemod{}_att".format(bm)) for name in "rst_n clk le".split(): signal = getattr(basemod_att, name) for i in range(len(signal)): phy = ttl_simple.Output(signal[i]) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.Output(basemod_att.mosi[0]) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) for i in range(3): self.comb += basemod_att.mosi[i + 1].eq(basemod_att.miso[i]) phy = ttl_simple.InOut(basemod_att.miso[3]) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.add_rtio(rtio_channels) self.comb += platform.request("clk_src_ext_sel").eq(0) # HMC clock chip and DAC control self.comb += [ platform.request("ad9154_rst_n", 0).eq(1), platform.request("ad9154_rst_n", 1).eq(1) ] self.submodules.converter_spi = spi2.SPIMaster( spi2.SPIInterface(platform.request("hmc_spi"), platform.request("ad9154_spi", 0), platform.request("ad9154_spi", 1))) csr_devices.append("converter_spi") self.comb += platform.request("hmc7043_reset").eq(0) # AMC/RTM serwb serwb_pads = platform.request("amc_rtm_serwb") platform.add_period_constraint(serwb_pads.clk_p, 10.) serwb_phy_rtm = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="slave", phy_width=4) self.submodules.serwb_phy_rtm = serwb_phy_rtm self.comb += self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.refclk) csr_devices.append("serwb_phy_rtm") serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master", with_scrambling=True) self.submodules += serwb_core # process CSR devices and connect them to serwb self.csr_regions = [] wb_slaves = WishboneSlaveManager(0x10000000) for i, name in enumerate(csr_devices): origin = i * CSR_RANGE_SIZE module = getattr(self, name) csrs = module.get_csrs() bank = wishbone.CSRBank(csrs) self.submodules += bank wb_slaves.add(origin, CSR_RANGE_SIZE, bank.bus) self.csr_regions.append((name, origin, 32, csrs)) self.submodules += wishbone.Decoder( serwb_core.etherbone.wishbone.bus, wb_slaves.get_interconnect_slaves(), register=True)