def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
module.add_local_interface_template(AXIMasterExternal())
toplevel_file = "hardware/hdl/vhdl/AXI/AXI_Master.vhd"
module.files = []
module.dependencies = []
module.show_in_browser = True
module.dev_status = AsModule.DevStatus.STABLE
module.module_type = AsModule.ModuleTypes.HARDWARE
module.module_category = "IO Infrastructure"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
internal_memory = module.get_interface("out")
internal_memory.to_external = False
internal_memory.instantiate_in_top = None
module.get_generic("C_M_AXI_DATA_WIDTH").set_value(None)
module.get_generic("C_M_AXI_ADDR_WIDTH").set_value(None)
module.brief_description = "AXI Master interface. Usually automatically inserted by Automatics. Contains Xilinx-specific HDL code!"
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
module.add_local_interface_template(AXISlaveExternal())
toplevel_file = "hardware/hdl/vhdl/AXI/AXI_Slave.vhd"
module.files = []
module.dependencies = ["fifo_fwft", "helpers"]
module.show_in_browser = True
module.dev_status = AsModule.DevStatus.STABLE
module.module_type = AsModule.ModuleTypes.HARDWARE
module.module_category = "IO Infrastructure"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
module.get_generic("C_S_AXI_DATA_WIDTH").set_value(None)
module.get_generic("C_S_AXI_ADDR_WIDTH").set_value(None)
module.brief_description = (
"AXI Slave interface. Usually automatically inserted by Automatics.")
return module
