def print_instructions(): print("") ase_functions.begin_green_fontcolor() print("NOTES TO USER => ") print("* This script assumes File Extensions: ") print(" * VHDL : .vhd") print(" * V/SV : .sv .vs .v") print(" * If you use arbitrary extensions, please edit this script to reflect them, and re-run the script") print("* See ase_sources.mk and check for correctness") print("* See if DUT_INCDIR has all the locations mentioned") print(" * If a directory is missing, append it separated by '+' symbol") ase_functions.end_green_fontcolor() print("")
def auto_find_sources(fd): # Prepare list of candidate directories print("Valid directories supplied => ") valid_dirlist = filter(lambda p: os.path.exists(p), args.dirlist) str_dirlist = " ".join(valid_dirlist) if len(valid_dirlist) == 0: # This line should never be reached since the directory list was # already checked after argument parsing. errorExit("No source directories specifield") # Check if VHDL files exist, populate if any print("") print("Finding VHDL files ... ") str = "" vhdl_filepaths = "" for extn in VHD_EXTENSIONS: for dir in valid_dirlist: for file in search_file("*" + extn, dir): str = str + file + '\n' if len(str) != 0: str = str + "\n" if len(str.strip()) != 0: open(VHDL_FILE_LIST, "w").write(str) vhdl_filepaths = str print("DUT_VHD_SRC_LIST = " + VHDL_FILE_LIST) fd.write("DUT_VHD_SRC_LIST = " + VHDL_FILE_LIST + " \n\n") else: print("No VHDL files were found !") # Check if V/SV files exist, populate if any print("") print("Finding {System}Verilog files ... ") str = "" pkgfiles = [] vlog_filepaths = "" cmd = "" for extn in VLOG_EXTENSIONS: for dir in valid_dirlist: pkgfiles = search_file("*pkg*" + extn, dir) for file in pkgfiles: str = str + file + '\n' for extn in VLOG_EXTENSIONS: for dir in valid_dirlist: for file in search_file("*" + extn, dir): if file not in pkgfiles: str = str + file + '\n' if len(str) != 0: open(VLOG_FILE_LIST, "w").write(str) vlog_filepaths = str print("DUT_VLOG_SRC_LIST = " + VLOG_FILE_LIST) fd.write("DUT_VLOG_SRC_LIST = " + VLOG_FILE_LIST + " \n\n") else: print("No {System}Verilog files were found !") vlog_filepaths = remove_dups(VLOG_FILE_LIST, args.exclude) # Recursively find and add directory locations for VH print("") print("Finding include directories ... ") # use absolute path names in DUT_INCDIR to keep Questa happy str = "" for dir in valid_dirlist: for file in search_dir("*", dir): str = str + file + '\n' str = str.replace("\n", "+") if len(str) != 0: print("DUT_INCDIR = " + str) fd.write("DUT_INCDIR = " + str + "\n\n") # Module repetition check vhdl_filepaths = vhdl_filepaths.replace("\n", " ").split() vlog_filepaths = vlog_filepaths.replace("\n", " ").split() all_filepaths = vhdl_filepaths + vlog_filepaths module_namelist = [] module_files = defaultdict(list) for filepath in all_filepaths: file_content = open(filepath).readlines() for line in file_content: strip_line = line.strip() if strip_line.startswith("//"): continue elif strip_line.startswith("module"): words = strip_line.split() modname = words[1] module_files[modname].append(filepath) module_namelist.append(modname) if (has_duplicates(module_files)): ase_functions.begin_red_fontcolor() print("\n") print("Duplicate module names were found in the RTL file lists.") print("Please remove them manually as RTL compilation is expected " + "to FAIL !") ase_functions.end_red_fontcolor() # Search for a JSON file describing the AFU json_file = None str = "" for dir in valid_dirlist: for file in search_file("*.json", dir): str = file if (len(str)): for js in str.split('\n'): try: with open(js, 'r') as f: db = json.load(f) f.close() afu_image = db['afu-image'] # If we get this far without an exception the JSON file looks # like an AFU descriptor. json_file = js break except ValueError: ase_functions.begin_red_fontcolor() sys.stderr.write("Error: reading JSON file {0}".format(js)) ase_functions.end_red_fontcolor() raise except KeyError: # Ignore key error -- maybe the file isn't an AFU descriptor None # Print auto-find instructions print("") ase_functions.begin_green_fontcolor() print("NOTES TO USER => ") print("* This script assumes File Extensions: ") print(" * VHDL : .vhd") print(" * V/SV : .sv .vs .v") print(' * If you use arbitrary extensions, please edit this script to ' 'reflect them, and re-run the script') print("* See ase_sources.mk and check for correctness") print("* See if DUT_INCDIR has all the locations mentioned") print(" * If a directory is missing, append it separated by '+' symbol") ase_functions.end_green_fontcolor() print("") return json_file
def config_sources(fd, filelist): # Get all the sources. rtl_src_config will emit all relevant source # files, one per line. try: srcs = commands_list_getoutput( "rtl_src_config --sim --abs".split(" ") + [filelist]) except Exception: errorExit("failed to read sources from {0}".format(filelist)) vlog_srcs = [] vhdl_srcs = [] json_srcs = [] # Separate boolean tracking for whether vlog/vhdl are found since # simulator commands (e.g. +define+) wind up in both. vlog_found = False vhdl_found = False srcs = srcs.split('\n') for s in srcs: if (len(s) == 0): None elif (s[0] == '+'): # + simulator commands go only in Verilog. VHDL simulation # doesn't support these. vlog_srcs.append(s) elif (s[0] == '-'): # For now assume - is an include directive and used only for # Verilog. Escape all but the first space, which likely # follows a simulator command. spl = s.split(' ') if (len(spl) > 1): s = spl[0] + ' ' + '\\ '.join(spl[1:]) vlog_srcs.append(s) vlog_found = True else: # Convert extensions to lower case for comparison sl = s.lower() # Escape spaces in pathnames s = s.replace(' ', '\\ ') # Verilog or SystemVerilog? for ext in VLOG_EXTENSIONS: if (sl.endswith(ext)): vlog_srcs.append(s) vlog_found = True break # VHDL? for ext in VHD_EXTENSIONS: if (sl.endswith(ext)): vhdl_srcs.append(s) vhdl_found = True break if (sl.endswith('.json')): json_srcs.append(s) qsys_sim_files = config_qsys_sources(filelist, vlog_srcs) # List Verilog & SystemVerilog sources in a file if (vlog_found or qsys_sim_files): fd.write("DUT_VLOG_SRC_LIST = " + VLOG_FILE_LIST + " \n\n") with open(VLOG_FILE_LIST, "w") as f: for s in vlog_srcs: f.write(s + "\n") if (qsys_sim_files): f.write("-F " + qsys_sim_files + "\n") # List VHDL sources in a file if (vhdl_found): fd.write("DUT_VHD_SRC_LIST = " + VHDL_FILE_LIST + " \n\n") with open(VHDL_FILE_LIST, "w") as f: for s in vhdl_srcs: f.write(s + "\n") # Is there a JSON file describing the AFU? json_file = None if (len(json_srcs)): # Yes, JSON specified in file list json_file = json_srcs[0] else: # Is there a JSON file in the same directory as the file list? dir = os.path.dirname(filelist) files = fnmatch.filter(os.listdir(dir), "*.json") for file in files: json_file = file if (json_file is not None): # Use the discovered JSON file, but complain that it should # have been named explicitly. ase_functions.begin_green_fontcolor() json_basename = os.path.basename(json_file) print(" *** JSON file {0} should be included in {1} ***".format( json_basename, os.path.abspath(filelist))) print(" The afu-image:afu-top-interface key in " + json_basename + " will be used") print(" to specify the AFU's top level interface.") ase_functions.end_green_fontcolor() return json_file
def auto_find_sources(fd): # Prepare list of candidate directories print("Valid directories supplied => ") valid_dirlist = filter(lambda p: os.path.exists(p), args.dirlist) str_dirlist = " ".join(valid_dirlist) if len(valid_dirlist) == 0: # This line should never be reached since the directory list was # already checked after argument parsing. errorExit("No source directories specifield") # Check if VHDL files exist, populate if any print("") print("Finding VHDL files ... ") str = "" vhdl_filepaths = "" for extn in VHD_EXTENSIONS: for dir in valid_dirlist: for file in search_file("*"+extn, dir): str = str + file + '\n' if len(str) != 0: str = str + "\n" if len(str.strip()) != 0: open(VHDL_FILE_LIST, "w").write(str) vhdl_filepaths = str print("DUT_VHD_SRC_LIST = " + VHDL_FILE_LIST) fd.write("DUT_VHD_SRC_LIST = " + VHDL_FILE_LIST + " \n\n") else: print("No VHDL files were found !") # Check if V/SV files exist, populate if any print("") print("Finding {System}Verilog files ... ") str = "" pkgfiles = [] vlog_filepaths = "" cmd = "" for extn in VLOG_EXTENSIONS: for dir in valid_dirlist: pkgfiles = search_file("*pkg*" + extn, dir) for file in pkgfiles: str = str + file + '\n' for extn in VLOG_EXTENSIONS: for dir in valid_dirlist: for file in search_file("*"+extn, dir): if file not in pkgfiles: str = str + file + '\n' if len(str) != 0: open(VLOG_FILE_LIST, "w").write(str) vlog_filepaths = str print("DUT_VLOG_SRC_LIST = " + VLOG_FILE_LIST) fd.write("DUT_VLOG_SRC_LIST = " + VLOG_FILE_LIST + " \n\n") else: print("No {System}Verilog files were found !") vlog_filepaths = remove_dups(VLOG_FILE_LIST, args.exclude) # Recursively find and add directory locations for VH print("") print("Finding include directories ... ") # use absolute path names in DUT_INCDIR to keep Questa happy str = "" for dir in valid_dirlist: for file in search_dir("*", dir): str = str + file + '\n' str = str.replace("\n", "+") if len(str) != 0: print("DUT_INCDIR = " + str) fd.write("DUT_INCDIR = " + str + "\n\n") # Module repetition check vhdl_filepaths = vhdl_filepaths.replace("\n", " ").split() vlog_filepaths = vlog_filepaths.replace("\n", " ").split() all_filepaths = vhdl_filepaths + vlog_filepaths module_namelist = [] module_files = defaultdict(list) for filepath in all_filepaths: file_content = open(filepath).readlines() for line in file_content: strip_line = line.strip() if strip_line.startswith("//"): continue elif strip_line.startswith("module"): words = strip_line.split() modname = words[1] module_files[modname].append(filepath) module_namelist.append(modname) if (has_duplicates(module_files)): ase_functions.begin_red_fontcolor() print("\n") print("Duplicate module names were found in the RTL file lists.") print("Please remove them manually as RTL compilation is expected " + "to FAIL !") ase_functions.end_red_fontcolor() # Search for a JSON file describing the AFU json_file = None str = "" for dir in valid_dirlist: for file in search_file("*.json", dir): str = file if (len(str)): for js in str.split('\n'): try: with open(js, 'r') as f: db = json.load(f) f.close() afu_image = db['afu-image'] # If we get this far without an exception the JSON file looks # like an AFU descriptor. json_file = js break except ValueError: ase_functions.begin_red_fontcolor() sys.stderr.write("Error: reading JSON file {0}".format(js)) ase_functions.end_red_fontcolor() raise except KeyError: # Ignore key error -- maybe the file isn't an AFU descriptor None # Print auto-find instructions print("") ase_functions.begin_green_fontcolor() print("NOTES TO USER => ") print("* This script assumes File Extensions: ") print(" * VHDL : .vhd") print(" * V/SV : .sv .vs .v") print(' * If you use arbitrary extensions, please edit this script to ' 'reflect them, and re-run the script') print("* See ase_sources.mk and check for correctness") print("* See if DUT_INCDIR has all the locations mentioned") print(" * If a directory is missing, append it separated by '+' symbol") ase_functions.end_green_fontcolor() print("") return json_file
def config_sources(fd, filelist): # Get all the sources. rtl_src_config will emit all relevant source # files, one per line. try: srcs = commands_list_getoutput( "rtl_src_config --sim --abs".split(" ") + [filelist]) except Exception: errorExit("failed to read sources from {0}".format(filelist)) vlog_srcs = [] vhdl_srcs = [] json_srcs = [] # Separate boolean tracking for whether vlog/vhdl are found since # simulator commands (e.g. +define+) wind up in both. vlog_found = False vhdl_found = False srcs = srcs.split('\n') for s in srcs: if (len(s) == 0): None elif (s[0] == '+'): # + simulator commands go in both Verilog and VHDL vlog_srcs.append(s) # Unfortuantely, vhdlan (VCS VHDL simulator) doesn't support # the same directives as the Verilog simulator. if (tool_brand != 'VCS'): vhdl_srcs.append(s) elif (s[0] == '-'): # For now assume - is an include directive and used only for # Verilog. Escape all but the first space, which likely # follows a simulator command. spl = s.split(' ') if (len(spl) > 1): s = spl[0] + ' ' + '\ '.join(spl[1:]) vlog_srcs.append(s) vlog_found = True else: # Convert extensions to lower case for comparison sl = s.lower() # Escape spaces in pathnames s = s.replace(' ', '\ ') # Verilog or SystemVerilog? for ext in VLOG_EXTENSIONS: if (sl[-len(ext):] == ext): vlog_srcs.append(s) vlog_found = True break # VHDL? for ext in VHD_EXTENSIONS: if (sl[-len(ext):] == ext): vhdl_srcs.append(s) vhdl_found = True break if (sl[-5:] == '.json'): json_srcs.append(s) # List Verilog & SystemVerilog sources in a file if (vlog_found): fd.write("DUT_VLOG_SRC_LIST = " + VLOG_FILE_LIST + " \n\n") with open(VLOG_FILE_LIST, "w") as f: for s in vlog_srcs: f.write(s + "\n") # List VHDL sources in a file if (vhdl_found): fd.write("DUT_VHD_SRC_LIST = " + VHDL_FILE_LIST + " \n\n") with open(VHDL_FILE_LIST, "w") as f: for s in vhdl_srcs: f.write(s + "\n") # Is there a JSON file describing the AFU? json_file = None if (len(json_srcs)): # Yes, JSON specified in file list json_file = json_srcs[0] else: # Is there a JSON file in the same directory as the file list? dir = os.path.dirname(filelist) files = fnmatch.filter(os.listdir(dir), "*.json") for file in files: json_file = file if (json_file is not None): # Use the discovered JSON file, but complain that it should # have been named explicitly. ase_functions.begin_green_fontcolor() json_basename = os.path.basename(json_file) print( " *** JSON file {0} should be included in {1} ***".format( json_basename, os.path.abspath(filelist))) print( " The afu-image:afu-top-interface key in " + json_basename + " will be used") print(" to specify the AFU's top level interface.") ase_functions.end_green_fontcolor() return json_file