Пример #1
0
def test_compat():
    ASM.set_compat(True)
    asm = EQ_Operation(compat=True).resolve()
    Assembler(compat=True).assemble(str(asm))

    try:
        ASM.set_compat(False)
        asm = EQ_Operation().resolve()
        Assembler(compat=True).assemble(str(asm))
    except:
        pass
    else:
        assert False, 'Should have failed'
Пример #2
0
    def __init__(self,
                 input_vm=None,
                 compat=False,
                 annotate=False,
                 no_init=False,
                 ram_specs=None,
                 LCL=None,
                 ARG=None,
                 THIS=None,
                 THAT=None):
        self._input_vm = input_vm
        self._compat = compat
        self._annotate = annotate
        self._known_symbols = dict(VM2ASM.PREDEFINED_CONSTANTS)
        self._operations = None

        ASM.set_compat(self._compat)

        self.asm_output = []
        if annotate:
            self.asm_output.append(f'// SOURCE FILE={input_vm}')

        if not no_init:

            def set_ram(addr, value):
                asm = ASM(f'''
            // setup {addr}
            @{value}
            D=A
            @{addr}
            M=D
            ''')
                self.asm_output += asm.to_list(indent=4)

            self.asm_output.append('// INIT BEGIN')

            set_ram('SP', VM2ASM.STACK_BASE_ADDRESS)

            if not self._compat:
                asm = ASM('''
            // setup the W register as SP replacement
            @{VM2ASM.STACK_BASE_ADDRESS}
            W=A
            ''')
                self.asm_output += asm.to_list(indent=4)

            # if any of the runtime segment base address were given we set them. This is
            # needed to run the test programs supplied by the course
            if LCL:
                set_ram('LCL', LCL)

            if ARG:
                set_ram('ARG', ARG)

            if THIS:
                set_ram('THIS', THIS)

            if THAT:
                set_ram('THAT', THAT)

            if ram_specs and len(ram_specs):
                for spec in ram_specs:
                    addr, val = spec.split('=')
                    addr = int(addr)
                    val = int(val)
                    set_ram(addr, val)

            # set all temp variables to 0
            set_ram('T0', 0)
            set_ram('T1', 0)
            set_ram('T2', 0)

            if annotate:
                self.asm_output.append('// INIT END')