def CrossInit(): global Asm, Flags assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { # create a dictionary of all mnemonics here. # In the from of: # 'NOP': (function, (tupple of opcodes), (tupple of instruction times), # or # 'NOP': (function, opcode, instruction time), # The part before : holds the name mnemonic (may only appear once in # the dictionary). # The part behind : holds a tupple holding the handling function # reference and # either a tupple of opcodes and a tupple of # instuction times, # or a single opcode and a single instruction time. # Opcodes are usually given in hex, in which case you can use a # simple hex string like 'AB' and let the handle function translate # it to a number, or use int('AB',16) translate it directly in the # dictionary. # Instruction times are usually a simple string holding the # instruction time, possibly with two or more values if the # instruction time depends on conditions being true or false. # Be sure to set the maximum string length of the instruction times # in dec.Asm.Timing_Length, otherwise the columns generated in the # listfile won't be aligned properly. } dec.Asm.Timing_Length = 0 # Get actual value in case timing details # given dec.Asm.Memory = 0 # Select code memory as default if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = dec.MAX16 # Set actual value for code address space dec.Asm.PP_TA_Factor = 1 # Set the actual factor between PP and TA dec.Flags.BigEndian = False # Set actual value return
def CrossInit(): global Asm, Flags, Error_List assem.CheckVersions(crossversion, minversion) crlib = cr8048 # Declare the tuples for the MOV instruction seperately, otherwise the # line gets sooooooo long movparams = ('A,R0', 'A,R1', 'A,R2', 'A,R3', 'A,R4', 'A,R5', 'A,R6', 'A,R7', 'A,@R0', 'A,@R1', 'R0,A', 'R1,A', 'R2,A', 'R3,A', 'R4,A', 'R5,A', 'R6,A', 'R7,A', '@R0,A', '@R1,A', 'A,#', 'R0,#', 'R1,#', 'R2,#', 'R3,#', 'R4,#', 'R5,#', 'R6,#', 'R7,#', '@R0,#', '@R1,#', 'A,T', 'T,A') movopcodes = (0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, 0xF0, 0xF1, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xA0, 0xA1, 0x23, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, 0xB0, 0xB1, 0x42, 0x62) movtimes = ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '2', '2', '2', '2', '2', '2', '2', '2', '2', '2', '2', '1', '1') dec.Asm.Instructions = { 'JC': (crlib.Branch, 0xF6, '2'), 'JNC': (crlib.Branch, 0xE6, '2'), 'JNT0': (crlib.Branch, 0x26, '2'), 'JNT1': (crlib.Branch, 0x46, '2'), 'JNZ': (crlib.Branch, 0x96, '2'), 'JTF': (crlib.Branch, 0x16, '2'), 'JT0': (crlib.Branch, 0x36, '2'), 'JT1': (crlib.Branch, 0x56, '2'), 'JZ': (crlib.Branch, 0xC6, '2'), 'JNIBF': (crlib.Branch, 0xD6, '2'), 'JOBF': (crlib.Branch, 0x86, '2'), 'CLR': (crlib.Singles, ('A', 'C'), (0x27, 0x97), ('1', '1')), 'CPL': (crlib.Singles, ('A', 'C'), (0x37, 0xA7), ('1', '1')), 'DA': (crlib.Singles, ('A', ), (0x57, ), ('1', )), 'DEC': (crlib.Singles, ('A', ), (0x07, ), ('1', )), 'INC': (crlib.Singles, ('A', 'R0', 'R1', 'R2', 'R3', 'R4', 'R5', 'R6', 'R7', '@R0', '@R1'), (0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x10, 0x11), ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1')), 'RL': (crlib.Singles, ('A', ), (0xE7, ), ('1', )), 'RLC': (crlib.Singles, ('A', ), (0xF7, ), ('1', )), 'RR': (crlib.Singles, ('A', ), (0x77, ), ('1', )), 'RRC': (crlib.Singles, ('A', ), (0x67, ), ('1', )), 'SWAP': (crlib.Singles, ('A', ), (0x47, ), ('1', )), 'DIS': (crlib.Singles, ('I', 'TCNTI'), (0x15, 0x35), ('1', '1')), 'EN': (crlib.Singles, ('I', 'TCNTI'), (0x05, 0x25), ('1', '1')), 'JMPP': (crlib.Singles, ('@A', ), (0xB3, ), ('2', )), 'SEL': (crlib.Singles, ('AN0', 'AN1'), (0x85, 0x95), ('1', '1')), 'STOP': (crlib.Singles, ('TCNT', ), (0x65, ), ('1', )), 'STRT': (crlib.Singles, ('T', 'CNT'), (0x55, 0x45), ('1', '1')), 'ADD': (crlib.Pairs, ('A,R0', 'A,R1', 'A,R2', 'A,R3', 'A,R4', 'A,R5', 'A,R6', 'A,R7', 'A,@R0', 'A,@R1', 'A,#'), (0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x60, 0x61, 0x03), ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '2')), 'ADDC': (crlib.Pairs, ('A,R0', 'A,R1', 'A,R2', 'A,R3', 'A,R4', 'A,R5', 'A,R6', 'A,R7', 'A,@R0', 'A,@R1', 'A,#'), (0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, 0x70, 0x71, 0x13), ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '2')), 'ANL': (crlib.Pairs, ('A,R0', 'A,R1', 'A,R2', 'A,R3', 'A,R4', 'A,R5', 'A,R6', 'A,R7', 'A,@R0', 'A,@R1', 'A,#'), (0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, 0x50, 0x51, 0x53), ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '2')), 'ORL': (crlib.Pairs, ('A,R0', 'A,R1', 'A,R2', 'A,R3', 'A,R4', 'A,R5', 'A,R6', 'A,R7', 'A,@R0', 'A,@R1', 'A,#'), (0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x40, 0x41, 0x43), ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '2')), 'XCH': (crlib.Pairs, ('A,R0', 'A,R1', 'A,R2', 'A,R3', 'A,R4', 'A,R5', 'A,R6', 'A,R7', 'A,@R0', 'A,@R1'), (0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x20, 0x21), ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1')), 'XCHD': (crlib.Pairs, ('A,@R0', 'A,@R1'), (0x30, 0x31), ('1', '1')), 'XRL': (crlib.Pairs, ('A,R0', 'A,R1', 'A,R2', 'A,R3', 'A,R4', 'A,R5', 'A,R6', 'A,R7', 'A,@R0', 'A,@R1', 'A,#'), (0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, 0xD0, 0xD1, 0xD3), ('1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '2')), 'MOV': (crlib.Pairs, movparams, movopcodes, movtimes), 'ANLD': (crlib.Pairs, ('P4,A', 'P5,A', 'P6,A', 'P7,A'), (0x9C, 0x9D, 0x9E, 0x9F), ('2', '2', '2', '2')), 'IN': (crlib.Pairs, ('A,DBB', 'A,P0', 'A,P1', 'A,P2'), (0x22, 0x08, 0x09, 0x0A), ('1', '2', '2', '2')), 'MOVP': (crlib.Pairs, ('A,@A', ), (0xA3, ), ('2', )), 'ORLD': (crlib.Pairs, ('P4,A', 'P5,A', 'P6,A', 'P7,A'), (0x8C, 0x8D, 0x8E, 0x8F), ('1', '1', '1', '1')), 'OUTL': (crlib.Pairs, ('DBB,A', 'P0,A', 'P1,A', 'P2,A'), (0x02, 0x90, 0x39, 0x3A), ('2', '2', '2', '2')), 'MOVD': (crlib.Pairs, ('A,P4', 'A,P5', 'A,P6', 'A,P7', 'P4,A', 'P5,A', 'P6,A', 'P7,A'), (0x0C, 0x0D, 0x0E, 0x0F, 0x3C, 0x3D, 0x3E, 0x3F), ('2', '2', '2', '2', '2', '2', '2', '2')), 'NOP': (crlib.Implied, 0x00, '1'), 'RET': (crlib.Implied, 0x83, '2'), 'RETI': (crlib.Implied, 0x93, '2'), 'RAD': (crlib.Implied, 0x80, '2'), 'CALL': (crlib.Absolute, 0x14, '2'), 'JMP': (crlib.Absolute, 0x04, '2'), 'DJNZ': (crlib.Djnz, (0xE8, 0x00), '2') } dec.Asm.Timing_Length = 1 errors.Error_List[dec.Cross.Name + 'tcrossed'] =\ 'Table crossed page boundary' dec.Asm.Memory = 0 if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = (1 << 11) - 1 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = False dec.Asm.Table8048 = -1 return
def CrossInit(): global Asm, Flags, Cross assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { 'ADDLW': (Immediate, 0x0F00, '1'), 'ANDLW': (Immediate, 0x0B00, '1'), 'IORLW': (Immediate, 0x0900, '1'), 'MOVLB': (Immediate, 0x0100, '1'), 'MOVLW': (Immediate, 0x0E00, '1'), 'MULLW': (Immediate, 0x0D00, '1'), 'RETLW': (Immediate, 0x0C00, '2'), 'SUBLW': (Immediate, 0x0800, '1'), 'XORLW': (Immediate, 0x0A00, '1'), 'BANKSEL': (Immediate, 0x0100, '1'), 'CLRWDT': (Implied, 0x0004, '1'), 'DAW': (Implied, 0x0007, '1'), 'SLEEP': (Implied, 0x0003, '1'), 'NOP': (Implied, 0x0000, '1'), 'POP': (Implied, 0x0006, '1'), 'PUSH': (Implied, 0x0005, '1'), 'RESET': (Implied, 0x00FF, '1'), 'CLRC': (Implied, 0x90D8, '1'), 'CLRDC': (Implied, 0x92D8, '1'), 'CLRZ': (Implied, 0x94D8, '1'), 'CLROV': (Implied, 0x96D8, '1'), 'CLRN': (Implied, 0x98D8, '1'), 'SETC': (Implied, 0x80D8, '1'), 'SETDC': (Implied, 0x82D8, '1'), 'SETZ': (Implied, 0x84D8, '1'), 'SETOV': (Implied, 0x86D8, '1'), 'SETN': (Implied, 0x88D8, '1'), 'SKPC': (Implied, 0xA0D8, '1'), 'SKPDC': (Implied, 0xA2D8, '1'), 'SKPZ': (Implied, 0xA4D8, '1'), 'SKPOV': (Implied, 0xA6D8, '1'), 'SKPN': (Implied, 0xA8D8, '1'), 'SKPNC': (Implied, 0xB0D8, '1'), 'SKPNDC': (Implied, 0xB2D8, '1'), 'SKPNZ': (Implied, 0xB4D8, '1'), 'SKPNOV': (Implied, 0xB6D8, '1'), 'SKPNN': (Implied, 0xB8D8, '1'), 'CLRF': (FileOnly, 0x6A00, '1'), 'CPFSEQ': (FileOnly, 0x6200, '1-3'), 'CPFSGT': (FileOnly, 0x6400, '1-3'), 'CPFSLT': (FileOnly, 0x6000, '1-3'), 'MOVWF': (FileOnly, 0x6E00, '1'), 'MULWF': (FileOnly, 0x0200, '1'), 'NEGF': (FileOnly, 0x6C00, '1'), 'SETF': (FileOnly, 0x6800, '1'), 'TSTFSZ': (FileOnly, 0x6600, '1-3'), 'ADDWF': (FileW, 0x2400, '1'), 'ADDWFC': (FileW, 0x2000, '1'), 'ANDWF': (FileW, 0x1400, '1'), 'COMF': (FileW, 0x1C00, '1'), 'DECF': (FileW, 0x0400, '1'), 'DECFSZ': (FileW, 0x2C00, '1-3'), 'DCFSNZ': (FileW, 0x4C00, '1-3'), 'INCF': (FileW, 0x2800, '1'), 'INCFSZ': (FileW, 0x3C00, '1-3'), 'INFSNZ': (FileW, 0x4800, '1-3'), 'IORWF': (FileW, 0x1000, '1'), 'MOVF': (FileW, 0x5000, '1'), 'RLCF': (FileW, 0x3400, '1'), 'RLNCF': (FileW, 0x4400, '1'), 'RRCF': (FileW, 0x3000, '1'), 'RRNCF': (FileW, 0x4000, '1'), 'SUBFWB': (FileW, 0x5400, '1'), 'SUBWF': (FileW, 0x5C00, '1'), 'SUBWFB': (FileW, 0x5800, '1'), 'SWAPF': (FileW, 0x3800, '1'), 'XORWF': (FileW, 0x1800, '1'), 'MOVFF': (FileFile, 0xC000, '2'), 'CALL': (CallGoto, 0xEC00, '2'), 'GOTO': (CallGoto, 0xEF00, '2'), 'RETFIE': (Returns, 0x0010, '2'), 'RETURN': (Returns, 0x0012, '2'), 'LFSR': (Lfsr, 0xEE00, '2'), 'TBLRD': (TableRW, 0x0008, '2'), 'TBLWR': (TableRW, 0x000C, '2'), 'BCF': (FileBit, 0x9000, '1'), 'BSF': (FileBit, 0x8000, '1'), 'BTFSC': (FileBit, 0xB000, '1-3'), 'BTFSS': (FileBit, 0xA000, '1-3'), 'BTG': (FileBit, 0x7000, '1'), 'BC': (Branches, 0xE200, '1-2'), 'BN': (Branches, 0xE600, '1-2'), 'BNC': (Branches, 0xE300, '1-2'), 'BNN': (Branches, 0xE700, '1-2'), 'BNOV': (Branches, 0xE500, '1-2'), 'BNZ': (Branches, 0xE100, '1-2'), 'BOV': (Branches, 0xE400, '1-2'), 'BRA': (Branches, 0xD000, '2'), 'BZ': (Branches, 0XE000, '1-2'), 'RCALL': (Branches, 0xD800, '2') } dec.Asm.Timing_Length = 3 dec.Asm.Memory = 0 # Select code memory as default if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = 0x0800 - 1 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = False dec.Asm.TablePic18 = -1 # Used by .OT and .CT directives dec.Asm.AccessBank18 = 0x60 # Devision line for Access Bank errors.Error_List[dec.Cross.Name + 'tcrossed'] =\ 'Table crossed page boundary'
def CrossInit(): global Asm, Flags, Cross assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { 'ADDLW': (Immediate, 0x3E00, '1'), 'ANDLW': (Immediate, 0x3900, '1'), 'CALL': (Immediate, 0x2000, '2'), 'GOTO': (Immediate, 0x2800, '2'), 'IORLW': (Immediate, 0x3800, '1'), 'MOVLB': (Immediate, 0x0020, '1'), 'MOVLP': (Immediate, 0x3180, '1'), 'MOVLW': (Immediate, 0x3000, '1'), 'RETLW': (Immediate, 0x3400, '2'), 'SUBLW': (Immediate, 0x3C00, '1'), 'XORLW': (Immediate, 0x3A00, '1'), 'B': (Immediate, 0x2800, '2'), 'BANKSEL': (Immediate, 0x0020, '1'), 'BRW': (Implied, 0x000B, '2'), 'CALLW': (Implied, 0x000A, '2'), 'CLRWDT': (Implied, 0x0064, '1'), 'OPTION': (Implied, 0x0062, '1'), 'RESET': (Implied, 0x0001, '1'), 'RETFIE': (Implied, 0x0009, '2'), 'RETURN': (Implied, 0x0008, '2'), 'SLEEP': (Implied, 0x0063, '1'), 'CLRW': (Implied, 0x0100, '1'), 'NOP': (Implied, 0x0000, '1'), 'CLRC': (Implied, 0x1003, '1'), 'CLRDC': (Implied, 0x1083, '1'), 'CLRZ': (Implied, 0x1103, '1'), 'SETC': (Implied, 0x1403, '1'), 'SETDC': (Implied, 0x1483, '1'), 'SETZ': (Implied, 0x1503, '1'), 'SKPC': (Implied, 0x1C03, '1-2'), 'SKPDC': (Implied, 0x1C83, '1-2'), 'SKPNC': (Implied, 0x1803, '1-2'), 'SKPNDC': (Implied, 0x1883, '1-2'), 'SKPNZ': (Implied, 0x1903, '1-2'), 'SKPZ': (Implied, 0x1D03, '1-2'), 'BRA': (Relative, 0x3200, '2'), 'CLRF': (FileOnly, 0x0180, '1'), 'MOVWF': (FileOnly, 0x0080, '1'), 'TRIS': (FileOnly, 0x0060, '1'), 'MOVFW': (FileOnly, 0x0800, '1'), 'TSTF': (FileOnly, 0x0880, '1'), 'ADDWF': (FileW, 0x0700, '1'), 'ADDWFC': (FileW, 0x3D00, '1'), 'ANDWF': (FileW, 0x0500, '1'), 'ASRF': (FileW, 0x3700, '1'), 'LSLF': (FileW, 0x3500, '1'), 'LSRF': (FileW, 0x3600, '1'), 'COMF': (FileW, 0x0900, '1'), 'DECF': (FileW, 0x0300, '1'), 'DECFSZ': (FileW, 0x0B00, '1-2'), 'INCF': (FileW, 0x0A00, '1'), 'INCFSZ': (FileW, 0x0F00, '1-2'), 'IORWF': (FileW, 0x0400, '1'), 'MOVF': (FileW, 0x0800, '1'), 'RLF': (FileW, 0x0D00, '1'), 'RRF': (FileW, 0x0C00, '1'), 'SUBWF': (FileW, 0x0200, '1'), 'SUBWFB': (FileW, 0x3B00, '1'), 'SWAPF': (FileW, 0x0E00, '1'), 'XORWF': (FileW, 0x0600, '1'), 'BCF': (FileBit, 0x1000, '1'), 'BSF': (FileBit, 0x1400, '1'), 'BTFSC': (FileBit, 0x1800, '1-2'), 'BTFSS': (FileBit, 0x1C00, '1-2'), 'ADDFSR': (Compiler, (0x3100, 0x3100), '1'), 'MOVIW': (Compiler, (0x0010, 0x3F00), '1'), 'MOVWI': (Compiler, (0x0018, 0x3F80), '1'), 'BC': (Branches, 0x1803, '2-3'), 'BDC': (Branches, 0x1883, '2-3'), 'BNC': (Branches, 0x1C03, '2-3'), 'BNDC': (Branches, 0x1C83, '2-3'), 'BNZ': (Branches, 0x1D03, '2-3'), 'BZ': (Branches, 0x1903, '2-3'), 'ADDCF': (Pseudo, 0x1803, 0x0A00, '2'), 'ADDDCF': (Pseudo, 0x1883, 0x0A00, '2'), 'NEGF': (Pseudo, 0x0980, 0x0A00, '2'), 'SUBCF': (Pseudo, 0x1803, 0x0300, '2'), 'SUBDCF': (Pseudo, 0x1883, 0x0300, '2'), 'LCALL': (Long, 0x2000), 'LGOTO': (Long, 0x2800) } dec.Asm.Timing_Length = 3 dec.Asm.Memory = 0 # Select code memory as default if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = 0x0400 - 1 dec.Flags.BigEndian = False # Change target factor to 2 if dec.Asm.PP_TA_Factor != 2: if dec.Asm.PP_Address != dec.Asm.TA_Address or dec.Asm.PP_Address !=\ dec.Asm.PH_Address: # Oops, this is complicated. Let's warn the programmer errors.DoWarning('taconfusion', True) # Set the instruction size and double the target address dec.Asm.PP_TA_Factor = 2 dec.Asm.TA_Address *= 2 dec.Asm.TablePic14 = -1 errors.Error_List[dec.Cross.Name + 'tcrossed'] =\ 'Table crossed page boundary' errors.Error_List[dec.Cross.Name + 'codemem'] =\ 'Directive only allowed within Code memory' errors.Error_List[dec.Cross.Name + 'progmem'] =\ 'Directive only allowed beyond program memory' dec.Cross.SaveByte = eval('SaveByte')
def CrossInit(): global Asm, Flags, avrdirlist assem.CheckVersions(crossversion, minversion) # Tupple consists of these fields: # - Function to be called # - 8=Xmega, 4=Mega, 2=AVR, 1=Tiny # - 128=XMEGA, 64=Enhanced 4M, 32=Enhanced 128k, 16=Enhanced 8k, # 8-Classic 128k, 4=Classic 8k, 2=Minimal, 1=Reduced # - Opcode # - Tiniming dec.Asm.Instructions = { 'ADC': (RegReg, 0b00001111, 0b01111111, 0x1C00, '1'), 'ADD': (RegReg, 0b00001111, 0b01111111, 0x0C00, '1'), 'AND': (RegReg, 0b00001111, 0b01111111, 0x2000, '1'), 'CP': (RegReg, 0b00001111, 0b01111111, 0x1400, '1'), 'CPC': (RegReg, 0b00001111, 0b01111111, 0x0400, '1'), 'CPSE': (RegReg, 0b00001111, 0b01111111, 0x1000, '1/2/3'), 'EOR': (RegReg, 0b00001111, 0b01111111, 0x2400, '1'), 'FMUL': (RegReg, 0b00001100, 0b01110000, 0x0308, '2'), 'FMULS': (RegReg, 0b00001100, 0b01110000, 0x0380, '2'), 'FMULSU': (RegReg, 0b00001100, 0b01110000, 0x0388, '2'), 'MOV': (RegReg, 0b00001111, 0b01111111, 0x2C00, '1'), 'MOVW': (RegReg, 0b00001100, 0b01110000, 0x0100, '1'), 'MUL': (RegReg, 0b00001100, 0b01110000, 0x9C00, '1'), 'MULS': (RegReg, 0b00001100, 0b01110000, 0x0200, '1'), 'MULSU': (RegReg, 0b00001100, 0b01110000, 0x0300, '1'), 'OR': (RegReg, 0b00001111, 0b01111111, 0x2800, '1'), 'SBC': (RegReg, 0b00001111, 0b01111111, 0x0800, '1'), 'SUB': (RegReg, 0b00001111, 0b01111111, 0x1800, '1'), 'ADIW': (RegImm, 0b00001110, 0b01111100, 0x9600, '1'), 'ANDI': (RegImm, 0b00001111, 0b01111111, 0x7000, '1'), 'CBR': (RegImm, 0b00001111, 0b01111111, 0x7000, '1'), 'CPI': (RegImm, 0b00001111, 0b01111111, 0x3000, '1'), 'LDI': (RegImm, 0b00001111, 0b01111111, 0xE000, '1'), 'ORI': (RegImm, 0b00001111, 0b01111111, 0x6000, '1'), 'SBCI': (RegImm, 0b00001111, 0b01111111, 0x4000, '1'), 'SBIW': (RegImm, 0b00001110, 0b01111100, 0x9700, '2'), 'SBR': (RegImm, 0b00001111, 0b01111111, 0x6000, '1'), 'SUBI': (RegImm, 0b00001111, 0b01111111, 0x5000, '1'), 'ASR': (RegOnly, 0b00001111, 0b01111111, 0x9405, '1'), 'CLR': (RegOnly, 0b00001111, 0b01111111, 0x2400, '1'), 'COM': (RegOnly, 0b00001111, 0b01111111, 0x9400, '1'), 'DEC': (RegOnly, 0b00001111, 0b01111111, 0x940A, '1'), 'INC': (RegOnly, 0b00001111, 0b01111111, 0x9403, '1'), 'LAC': (RegOnly, 0b00001000, 0b00000000, 0x9206, '2'), 'LAS': (RegOnly, 0b00001000, 0b00000000, 0x9205, '2'), 'LAT': (RegOnly, 0b00001000, 0b00000000, 0x9207, '2'), 'LSL': (RegOnly, 0b00001111, 0b01111111, 0x0C00, '1'), 'LSR': (RegOnly, 0b00001111, 0b01111111, 0x9406, '1'), 'NEG': (RegOnly, 0b00001111, 0b01111111, 0x9401, '1'), 'POP': (RegOnly, 0b00001111, 0b01111101, 0x900F, '2'), 'PUSH': (RegOnly, 0b00001111, 0b01111101, 0x920F, '1/2'), 'ROL': (RegOnly, 0b00001111, 0b01111111, 0x1C00, '1'), 'ROR': (RegOnly, 0b00001111, 0b01111111, 0x9407, '1'), 'SER': (RegOnly, 0b00001111, 0b01111111, 0xEF0F, '1'), 'SWAP': (RegOnly, 0b00001111, 0b01111111, 0x9402, '1'), 'TST': (RegOnly, 0b00001111, 0b01111111, 0x2000, '1'), 'XCH': (RegOnly, 0b00001000, 0b00000000, 0x9204, '2'), 'BRBC': (RelJmp, 0b00001111, 0b01111111, 0xF400, '1/2'), 'BRBS': (RelJmp, 0b00001111, 0b01111111, 0xF000, '1/2'), 'BRCC': (RelJmp, 0b00001111, 0b01111111, 0xF400, '1/2'), 'BRCS': (RelJmp, 0b00001111, 0b01111111, 0xF000, '1/2'), 'BREQ': (RelJmp, 0b00001111, 0b01111111, 0xF001, '1/2'), 'BRGE': (RelJmp, 0b00001111, 0b01111111, 0xF404, '1/2'), 'BRHC': (RelJmp, 0b00001111, 0b01111111, 0xF405, '1/2'), 'BRHS': (RelJmp, 0b00001111, 0b01111111, 0xF005, '1/2'), 'BRID': (RelJmp, 0b00001111, 0b01111111, 0xF407, '1/2'), 'BRIE': (RelJmp, 0b00001111, 0b01111111, 0xF007, '1/2'), 'BRLO': (RelJmp, 0b00001111, 0b01111111, 0xF000, '1/2'), 'BRLT': (RelJmp, 0b00001111, 0b01111111, 0xF004, '1/2'), 'BRMI': (RelJmp, 0b00001111, 0b01111111, 0xF002, '1/2'), 'BRNE': (RelJmp, 0b00001111, 0b01111111, 0xF401, '1/2'), 'BRPL': (RelJmp, 0b00001111, 0b01111111, 0xF402, '1/2'), 'BRSH': (RelJmp, 0b00001111, 0b01111111, 0xF400, '1/2'), 'BRTC': (RelJmp, 0b00001111, 0b01111111, 0xF406, '1/2'), 'BRTS': (RelJmp, 0b00001111, 0b01111111, 0xF006, '1/2'), 'BRVC': (RelJmp, 0b00001111, 0b01111111, 0xF403, '1/2'), 'BRVS': (RelJmp, 0b00001111, 0b01111111, 0xF003, '1/2'), 'RCALL': (RelJmp, 0b00001111, 0b01111111, 0xD000, '2/3/4'), 'RJMP': (RelJmp, 0b00001111, 0b01111111, 0xC000, '2'), 'CALL': (CallJmp, 0b00001110, 0b01111000, 0x940E, '3/4/5'), 'JMP': (CallJmp, 0b00001110, 0b01111000, 0x940C, '3'), 'BLD': (BitInst, 0b00001111, 0b01111111, 0xF800, '1'), 'BST': (BitInst, 0b00001111, 0b01111111, 0xFA00, '1'), 'SBRC': (BitInst, 0b00001111, 0b01111111, 0xFC00, '1/2/3'), 'SBRS': (BitInst, 0b00001111, 0b01111111, 0xFE00, '1/2/3'), 'CBI': (IOBits, 0b00001111, 0b01111111, 0x9800, '1/2'), 'SBI': (IOBits, 0b00001111, 0b01111111, 0x9A00, '1/2'), 'SBIC': (IOBits, 0b00001111, 0b01111111, 0x9900, '2/3/4*'), 'SBIS': (IOBits, 0b00001111, 0b01111111, 0x9B00, '2/3/4*'), # reduced LD has less addressing modes 'LD': (LDIndexed, 0b00001111, 0b01111111, 1, '1/2/3'), 'LDD': (LDIndexed, 0b00001110, 0b01111100, 0, '1/2/3'), # reduced ST has less addressing modes 'ST': (STIndexed, 0b00001111, 0b01111111, 1, '1/2'), 'STD': (STIndexed, 0b00001110, 0b01111100, 0, '1/2'), # tiny & reduced LDS and STS have different bit pattern 'LDS': (LdsSts, 0b00001111, 0b01111101, 0x9000, '2/3'), 'STS': (LdsSts, 0b00001111, 0b01111101, 0x9200, '2'), 'ELPM': (ELpm, 0b00001110, 0b01111000, 0x95D8, '3'), 'LPM': (ELpm, 0b00001110, 0b01110110, 0x95C8, '3'), 'SPM': (Spm, 0b00001100, 0b01110000, 0x95E8, '*'), 'IN': (InOut, 0b00001111, 0b01111111, 0xB000, '1'), 'OUT': (InOut, 0b00001111, 0b01111111, 0xB800, '1'), 'BCLR': (Sreg, 0b00001111, 0b01111111, 0x9488, '1'), 'BSET': (Sreg, 0b00001111, 0b01111111, 0x9408, '1'), 'DES': (Des, 0b00001000, 0b00000000, 0x940B, '1/2'), 'BREAK': (Inherent, 0b00001101, 0b01100001, 0x9598, '1'), 'CLC': (Inherent, 0b00001111, 0b01111111, 0x9488, '1'), 'CLH': (Inherent, 0b00001111, 0b01111111, 0x94D8, '1'), 'CLI': (Inherent, 0b00001111, 0b01111111, 0x94F8, '1'), 'CLN': (Inherent, 0b00001111, 0b01111111, 0x94A8, '1'), 'CLS': (Inherent, 0b00001111, 0b01111111, 0x94C8, '1'), 'CLT': (Inherent, 0b00001111, 0b01111111, 0x94E8, '1'), 'CLV': (Inherent, 0b00001111, 0b01111111, 0x94B8, '1'), 'CLZ': (Inherent, 0b00001111, 0b01111111, 0x9498, '1'), 'EICALL': (Inherent, 0b00001100, 0b01000000, 0x9519, '3/4*'), 'EIJMP': (Inherent, 0b00001100, 0b01000000, 0x9419, '2'), 'ICALL': (Inherent, 0b00001111, 0b01111100, 0x9509, '2/3/4*'), 'IJMP': (Inherent, 0b00001111, 0b01111100, 0x9409, '2'), 'NOP': (Inherent, 0b00001111, 0b01111111, 0x0000, '1'), 'RET': (Inherent, 0b00001111, 0b01111111, 0x9508, '4/5*'), 'RETI': (Inherent, 0b00001111, 0b01111111, 0x9518, '4/5*'), 'SEC': (Inherent, 0b00001111, 0b01111111, 0x9408, '1'), 'SEH': (Inherent, 0b00001111, 0b01111111, 0x9458, '1'), 'SEI': (Inherent, 0b00001111, 0b01111111, 0x9478, '1'), 'SEN': (Inherent, 0b00001111, 0b01111111, 0x9428, '1'), 'SES': (Inherent, 0b00001111, 0b01111111, 0x9448, '1'), 'SET': (Inherent, 0b00001111, 0b01111111, 0x9468, '1'), 'SEV': (Inherent, 0b00001111, 0b01111111, 0x9438, '1'), 'SEZ': (Inherent, 0b00001111, 0b01111111, 0x9418, '1'), 'SLEEP': (Inherent, 0b00001111, 0b01111111, 0x9588, '1'), 'WDR': (Inherent, 0b00001111, 0b01111111, 0x95A8, '1') } length = 0 for i in dec.Asm.Instructions: if len(dec.Asm.Instructions[i][4]) > length: length = len(dec.Asm.Instructions[i][4]) dec.Asm.Timing_Length = length dec.Asm.Memory = 0 if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = (1 << 22) - 1 # Change target factor to 2 if dec.Asm.PP_TA_Factor != 2: if dec.Asm.PP_Address != dec.Asm.TA_Address or\ dec.Asm.PP_Address != dec.Asm.PH_Address: # Oops, this is complicated. Let's warn the programmer errors.DoWarning('taconfusion', True) # Set the instruction size and double the target address dec.Asm.PP_TA_Factor = 2 dec.Asm.TA_Address *= 2 dec.Flags.BigEndian = False dec.Asm.AVR_Family = 0 errors.Error_List[dec.Cross.Name + 'nofamily'] =\ 'AVR Family not set. Assuming XMega family.' # Fill dictionary with all available directive handlers for i in dir(cravr): if len(i) == 5 and i[:3] == 'Dir': avrdirlist[i[-2:]] = eval(i) return
def CrossInit(): global Asm, Flags assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { # Inherent operand instructions 'HALT': (Inherent, 0x8E, '2'), 'IRET': (Inherent, 0x80, '9'), 'NOP': (Inherent, 0x9D, '2'), 'RCF': (Inherent, 0x98, '2'), 'RET': (Inherent, 0x81, '6'), 'RIM': (Inherent, 0x9A, '2'), 'RSP': (Inherent, 0x9C, '2'), 'SCF': (Inherent, 0x99, '2'), 'SIM': (Inherent, 0x9B, '2'), 'TRAP': (Inherent, 0x83, '10'), 'WFI': (Inherent, 0x8F, '2'), # 0=# 1=short 2=long 3=(X) # 4=(short,X) 5=(long,X) 6=(Y) 7=(short,Y) # 8=(long,Y) 9=[short] 10=[long.w] 11=([short],X) # 12=([long.w],X) 13=([short],Y) 14=([long.w],Y) 15=A # 16=X 17=Y 18=S 'ADC': (Accu, (0x00A9, 0x00B9, 0x00C9, 0x00F9, 0x00E9, 0x00D9, 0x90F9, 0x90E9, 0x90D9, 0x92B9, 0x92C9, 0x92E9, 0x92D9, 0x91E9, 0x91D9), ('2', '3', '4', '3', '4', '5', '4', '5', '6', '5', '6', '6', '7', '6', '7')), 'ADD': (Accu, (0x00AB, 0x00BB, 0x00CB, 0x00FB, 0x00EB, 0x00DB, 0x90FB, 0x90EB, 0x90DB, 0x92BB, 0x92CB, 0x92EB, 0x92DB, 0x91EB, 0x91DB), ('2', '3', '4', '3', '4', '5', '4', '5', '6', '5', '6', '6', '7', '6', '7')), 'AND': (Accu, (0x00A4, 0x00B4, 0x00C4, 0x00F4, 0x00E4, 0x00D4, 0x90F4, 0x90E4, 0x90D4, 0x92B4, 0x92C4, 0x92E4, 0x92D4, 0x91E4, 0x91D4), ('2', '3', '4', '3', '4', '5', '4', '5', '6', '5', '6', '6', '7', '6', '7')), 'BCP': (Accu, (0x00A5, 0x00B5, 0x00C5, 0x00F5, 0x00E5, 0x00D5, 0x90F5, 0x90E5, 0x90D5, 0x92B5, 0x92C5, 0x92E5, 0x92D5, 0x91E5, 0x91D5), ('2', '3', '4', '3', '4', '5', '4', '5', '6', '5', '6', '6', '7', '6', '7')), 'OR': (Accu, (0x00AA, 0x00BA, 0x00CA, 0x00FA, 0x00EA, 0x00DA, 0x90FA, 0x90EA, 0x90DA, 0x92BA, 0x92CA, 0x92EA, 0x92DA, 0x91EA, 0x91DA), ('2', '3', '4', '3', '4', '5', '4', '5', '6', '5', '6', '6', '7', '6', '7')), 'SBC': (Accu, (0x00A2, 0x00B2, 0x00C2, 0x00F2, 0x00E2, 0x00D2, 0x90F2, 0x90E2, 0x90D2, 0x92B2, 0x92C2, 0x92E2, 0x92D2, 0x91E2, 0x91D2), ('2', '3', '4', '3', '4', '5', '4', '5', '6', '5', '6', '6', '7', '6', '7')), 'SUB': (Accu, (0x00A0, 0x00B0, 0x00C0, 0x00F0, 0x00E0, 0x00D0, 0x90F0, 0x90E0, 0x90D0, 0x92B0, 0x92C0, 0x92E0, 0x92D0, 0x91E0, 0x91D0), ('2', '3', '4', '3', '4', '5', '4', '5', '6', '5', '6', '6', '7', '6', '7')), 'XOR': (Accu, (0x00A8, 0x00B8, 0x00C8, 0x00F8, 0x00E8, 0x00D8, 0x90F8, 0x90E8, 0x90D8, 0x92B8, 0x92C8, 0x92E8, 0x92D8, 0x91E8, 0x91D8), ('2', '3', '4', '3', '4', '5', '4', '5', '6', '5', '6', '6', '7', '6', '7')), 'CALL': (Single, (0x0000, 0x00BD, 0x00CD, 0x00FD, 0x00ED, 0x00DD, 0x90FD, 0x90ED, 0x90DD, 0x92BD, 0x92CD, 0x92ED, 0x92DD, 0x91ED, 0x91DD, 0x0000, 0x0000, 0x0000), ('0', '5', '6', '5', '6', '7', '6', '7', '8', '7', '8', '8', '9', '8', '9', '0', '0', '0')), 'CLR': (Single, (0x0000, 0x003F, 0x00FF, 0x007F, 0x006F, 0x00FF, 0x907F, 0x906F, 0x00FF, 0x923F, 0x00FF, 0x926F, 0x00FF, 0x916F, 0x00FF, 0x004F, 0x005F, 0x905F), ('0', '5', '0', '5', '6', '0', '6', '7', '0', '7', '0', '8', '0', '8', '0', '3', '3', '4')), 'CPL': (Single, (0x0000, 0x0033, 0x00FF, 0x0073, 0x0063, 0x00FF, 0x9073, 0x9063, 0x00FF, 0x9233, 0x00FF, 0x9263, 0x00FF, 0x9163, 0x00FF, 0x0043, 0x0053, 0x9053), ('0', '5', '0', '5', '6', '0', '6', '7', '0', '7', '0', '8', '0', '8', '0', '3', '3', '4')), 'DEC': (Single, (0x0000, 0x003A, 0x00FF, 0x007A, 0x006A, 0x00FF, 0x907A, 0x906A, 0x00FF, 0x923A, 0x00FF, 0x926A, 0x00FF, 0x916A, 0x00FF, 0x004A, 0x005A, 0x905A), ('0', '5', '0', '5', '6', '0', '6', '7', '0', '7', '0', '8', '0', '8', '0', '3', '3', '4')), 'INC': (Single, (0x0000, 0x003C, 0x00FF, 0x007C, 0x006C, 0x00FF, 0x907C, 0x906C, 0x00FF, 0x923C, 0x00FF, 0x926C, 0x00FF, 0x916C, 0x00FF, 0x004C, 0x005C, 0x905C), ('0', '5', '0', '5', '6', '0', '6', '7', '0', '7', '0', '8', '0', '8', '0', '3', '3', '4')), 'JP': (Single, (0x0000, 0x00BC, 0x00CC, 0x00FC, 0x00EC, 0x00DC, 0x90FC, 0x90EC, 0x90DC, 0x92BC, 0x92CC, 0x92EC, 0x92DC, 0x91EC, 0x91DC, 0x0000, 0x0000, 0x0000), ('0', '2', '3', '2', '3', '4', '3', '4', '5', '4', '5', '5', '6', '5', '6', '0', '0', '0')), 'NEG': (Single, (0x0000, 0x0030, 0x00FF, 0x0070, 0x0060, 0x00FF, 0x9070, 0x9060, 0x00FF, 0x9230, 0x00FF, 0x9260, 0x00FF, 0x9160, 0x00FF, 0x0040, 0x0050, 0x9050), ('0', '5', '0', '5', '6', '0', '6', '7', '0', '7', '0', '8', '0', '8', '0', '3', '3', '4')), 'RLC': (Single, (0x0000, 0x0039, 0x00FF, 0x0079, 0x0069, 0x00FF, 0x9079, 0x9069, 0x00FF, 0x9239, 0x00FF, 0x9269, 0x00FF, 0x9169, 0x00FF, 0x0049, 0x0059, 0x9059), ('0', '5', '0', '5', '6', '0', '6', '7', '0', '7', '0', '8', '0', '8', '0', '3', '3', '4')), 'RRC': (Single, (0x0000, 0x0036, 0x00FF, 0x0076, 0x0066, 0x00FF, 0x9076, 0x9066, 0x00FF, 0x9236, 0x00FF, 0x9266, 0x00FF, 0x9166, 0x00FF, 0x0046, 0x0056, 0x9056), ('0', '5', '0', '5', '6', '0', '6', '7', '0', '7', '0', '8', '0', '8', '0', '3', '3', '4')), 'SLA': (Single, (0x0000, 0x0038, 0x00FF, 0x0078, 0x0068, 0x00FF, 0x9078, 0x9068, 0x00FF, 0x9238, 0x00FF, 0x9268, 0x00FF, 0x9168, 0x00FF, 0x0048, 0x0058, 0x9058), ('0', '5', '0', '5', '6', '0', '6', '7', '0', '7', '0', '8', '0', '8', '0', '3', '3', '4')), 'SLL': (Single, (0x0000, 0x0038, 0x00FF, 0x0078, 0x0068, 0x00FF, 0x9078, 0x9068, 0x00FF, 0x9238, 0x00FF, 0x9268, 0x00FF, 0x9168, 0x00FF, 0x0048, 0x0058, 0x9058), ('0', '5', '0', '5', '6', '0', '6', '7', '0', '7', '0', '8', '0', '8', '0', '3', '3', '4')), 'SRA': (Single, (0x0000, 0x0037, 0x00FF, 0x0077, 0x0067, 0x00FF, 0x9077, 0x9067, 0x00FF, 0x9237, 0x00FF, 0x9267, 0x00FF, 0x9167, 0x00FF, 0x0047, 0x0057, 0x9057), ('0', '5', '0', '5', '6', '0', '6', '7', '0', '7', '0', '8', '0', '8', '0', '3', '3', '4')), 'SRL': (Single, (0x0000, 0x0034, 0x00FF, 0x0074, 0x0064, 0x00FF, 0x9074, 0x9064, 0x00FF, 0x9234, 0x00FF, 0x9264, 0x00FF, 0x9164, 0x00FF, 0x0044, 0x0054, 0x9054), ('0', '5', '0', '5', '6', '0', '6', '7', '0', '7', '0', '8', '0', '8', '0', '3', '3', '4')), 'SWAP': (Single, (0x0000, 0x003E, 0x00FF, 0x007E, 0x006E, 0x00FF, 0x907E, 0x906E, 0x00FF, 0x923E, 0x00FF, 0x926E, 0x00FF, 0x916E, 0x00FF, 0x004E, 0x005E, 0x905E), ('0', '5', '0', '5', '6', '0', '6', '7', '0', '7', '0', '8', '0', '8', '0', '3', '3', '4')), 'TNZ': (Single, (0x0000, 0x003D, 0x00FF, 0x007D, 0x006D, 0x00FF, 0x907D, 0x906D, 0x00FF, 0x923D, 0x00FF, 0x926D, 0x00FF, 0x916D, 0x00FF, 0x004D, 0x005D, 0x905D), ('0', '4', '0', '4', '5', '0', '5', '6', '0', '6', '0', '7', '0', '7', '0', '3', '3', '4')), 'LD': (LdInst, 0), 'CP': (CpInst, 0), 'BRES': (BitInst, (0x0011, 0x9211), ('5', '7')), 'BSET': (BitInst, (0x0010, 0x9210), ('5', '7')), 'BTJF': (BitInst, (0x0001, 0x9201), ('5', '7')), 'BTJT': (BitInst, (0x0000, 0x9200), ('5', '7')), 'CALLR': (Branch, (0x00AD, 0x92AD), ('6', '8')), 'JRA': (Branch, (0x0020, 0x9220), ('3', '5')), 'JRC': (Branch, (0x0025, 0x9225), ('3', '5')), 'JREQ': (Branch, (0x0027, 0x9227), ('3', '5')), 'JRF': (Branch, (0x0021, 0x9221), ('3', '5')), 'JRH': (Branch, (0x0029, 0x9229), ('3', '5')), 'JRIH': (Branch, (0x002F, 0x922F), ('3', '5')), 'JRIL': (Branch, (0x002E, 0x922E), ('3', '5')), 'JRM': (Branch, (0x002D, 0x922D), ('3', '5')), 'JRMI': (Branch, (0x002B, 0x922B), ('3', '5')), 'JRNC': (Branch, (0x0024, 0x9224), ('3', '5')), 'JRNE': (Branch, (0x0026, 0x9226), ('3', '5')), 'JRNH': (Branch, (0x0028, 0x9228), ('3', '5')), 'JRNM': (Branch, (0x002C, 0x922C), ('3', '5')), 'JRPL': (Branch, (0x002A, 0x922A), ('3', '5')), 'JRT': (Branch, (0x0020, 0x9220), ('3', '5')), 'JRUGE': (Branch, (0x0024, 0x9224), ('3', '5')), 'JRUGT': (Branch, (0x0022, 0x9222), ('3', '5')), 'JRULE': (Branch, (0x0023, 0x9223), ('3', '5')), 'JRULT': (Branch, (0x0025, 0x9225), ('3', '5')), 'POP': (Stack, (0x0084, 0x0085, 0x9085, 0x0086), ('4', '4', '5', '4')), 'PUSH': (Stack, (0x0088, 0x0089, 0x9089, 0x008A), ('3', '3', '4', '3')), 'MUL': (Multiply, (0x0042, 0x9042), ('11', '12')) } dec.Asm.Timing_Length = 2 dec.Asm.Memory = 0 if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = dec.MAX16 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = True return
def CrossInit(): """ Initialize this cross overlay. """ global Asm, Flags assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { 'ASLA': (Implied, 0x48, '3'), 'ASLX': (Implied, 0x58, '3'), 'ASRA': (Implied, 0x47, '3'), 'ASRX': (Implied, 0x57, '3'), 'CLC': (Implied, 0x98, '2'), 'CLI': (Implied, 0x9A, '2'), 'CLRA': (Implied, 0x4F, '3'), 'CLRX': (Implied, 0x5F, '3'), 'COMA': (Implied, 0x43, '3'), 'COMX': (Implied, 0x53, '3'), 'DECA': (Implied, 0x4A, '3'), 'DECX': (Implied, 0x5A, '3'), 'DEX': (Implied, 0x5A, '3'), 'INCA': (Implied, 0x4C, '3'), 'INCX': (Implied, 0x5C, '3'), 'INX': (Implied, 0x5C, '3'), 'LSLA': (Implied, 0x48, '3'), 'LSLX': (Implied, 0x58, '3'), 'LSRA': (Implied, 0x44, '3'), 'LSRX': (Implied, 0x54, '3'), 'MUL': (Implied, 0x42, '11'), 'NEGA': (Implied, 0x40, '3'), 'NEGX': (Implied, 0x50, '3'), 'NOP': (Implied, 0x9D, '2'), 'ROLA': (Implied, 0x49, '3'), 'ROLX': (Implied, 0x59, '3'), 'RORA': (Implied, 0x46, '3'), 'RORX': (Implied, 0x56, '3'), 'RSP': (Implied, 0x9C, '2'), 'RTI': (Implied, 0x80, '9'), 'RTS': (Implied, 0x81, '6'), 'SEC': (Implied, 0x99, '2'), 'SEI': (Implied, 0x9B, '2'), 'STOP': (Implied, 0x8E, '2'), 'SWI': (Implied, 0x83, '10'), 'TAX': (Implied, 0x97, '2'), 'TSTA': (Implied, 0x4D, '3'), 'TSTX': (Implied, 0x5D, '3'), 'TXA': (Implied, 0x9F, '2'), 'WAIT': (Implied, 0x8F, '2'), 'BCC': (Branch, 0x24, '3'), 'BCS': (Branch, 0x25, '3'), 'BEQ': (Branch, 0x27, '3'), 'BHCC': (Branch, 0x28, '3'), 'BHCS': (Branch, 0x29, '3'), 'BHI': (Branch, 0x22, '3'), 'BHS': (Branch, 0x24, '3'), 'BIH': (Branch, 0x2F, '3'), 'BIL': (Branch, 0x2E, '3'), 'BLO': (Branch, 0x25, '3'), 'BLS': (Branch, 0x23, '3'), 'BMC': (Branch, 0x2C, '3'), 'BMI': (Branch, 0x2B, '3'), 'BMS': (Branch, 0x2D, '3'), 'BNE': (Branch, 0x26, '3'), 'BPL': (Branch, 0x2A, '3'), 'BRA': (Branch, 0x20, '3'), 'BRN': (Branch, 0x21, '3'), 'BSR': (Branch, 0xAD, '6'), 'ADC': (Multi, (0xA9, 0xB9, 0xC9, 0xF9, 0xE9, 0xD9), ('2', '3', '4', '3', '4', '5')), 'ADD': (Multi, (0xAB, 0xBB, 0xCB, 0xFB, 0xEB, 0xDB), ('2', '3', '4', '3', '4', '5')), 'AND': (Multi, (0xA4, 0xB4, 0xC4, 0xF4, 0xE4, 0xD4), ('2', '3', '4', '3', '4', '5')), 'ASL': (Multi, (0x00, 0x38, 0x00, 0x78, 0x68, 0x00), ('', '5', '', '5', '6', '')), 'ASR': (Multi, (0x00, 0x37, 0x00, 0x77, 0x67, 0x00), ('', '5', '', '5', '6', '')), 'BIT': (Multi, (0xA5, 0xB5, 0xC5, 0xF5, 0xE5, 0xD5), ('2', '3', '4', '3', '4', '5')), 'CLR': (Multi, (0x00, 0x3F, 0x00, 0x7F, 0x6F, 0x00), ('', '5', '', '5', '6', '')), 'CMP': (Multi, (0xA1, 0xB1, 0xC1, 0xF1, 0xE1, 0xD1), ('2', '3', '4', '3', '4', '5')), 'COM': (Multi, (0x00, 0x33, 0x00, 0x73, 0x63, 0x00), ('', '5', '', '5', '6', '')), 'CPX': (Multi, (0xA3, 0xB3, 0xC3, 0xF3, 0xE3, 0xD3), ('2', '3', '4', '3', '4', '5')), 'DEC': (Multi, (0x00, 0x3A, 0x00, 0x7A, 0x6A, 0x00), ('', '5', '', '5', '6', '')), 'EOR': (Multi, (0xA8, 0xB8, 0xC8, 0xF8, 0xE8, 0xD8), ('2', '3', '4', '3', '4', '5')), 'INC': (Multi, (0x00, 0x3C, 0x00, 0x7C, 0x6C, 0x00), ('', '5', '', '5', '6', '')), 'JMP': (Multi, (0x00, 0xBC, 0xCC, 0xFC, 0xEC, 0xDC), ('', '2', '3', '2', '3', '4')), 'JSR': (Multi, (0x00, 0xBD, 0xCD, 0xFD, 0xED, 0xDD), ('', '5', '6', '5', '6', '7')), 'LDA': (Multi, (0xA6, 0xB6, 0xC6, 0xF6, 0xE6, 0xD6), ('2', '3', '4', '3', '4', '5')), 'LDX': (Multi, (0xAE, 0xBE, 0xCE, 0xFE, 0xEE, 0xDE), ('2', '3', '4', '3', '4', '5')), 'LSL': (Multi, (0x00, 0x38, 0x00, 0x78, 0x68, 0x00), ('', '5', '', '5', '6', '')), 'LSR': (Multi, (0x00, 0x34, 0x00, 0x74, 0x64, 0x00), ('', '5', '', '5', '6', '')), 'NEG': (Multi, (0x00, 0x30, 0x00, 0x70, 0x60, 0x00), ('', '5', '', '5', '6', '')), 'ORA': (Multi, (0xAA, 0xBA, 0xCA, 0xFA, 0xEA, 0xDA), ('2', '3', '4', '3', '4', '5')), 'ROL': (Multi, (0x00, 0x39, 0x00, 0x79, 0x69, 0x00), ('', '5', '', '5', '6', '')), 'ROR': (Multi, (0x00, 0x36, 0x00, 0x76, 0x66, 0x00), ('', '5', '', '5', '6', '')), 'SBC': (Multi, (0xA2, 0xB2, 0xC2, 0xF2, 0xE2, 0xD2), ('2', '3', '4', '3', '4', '5')), 'STA': (Multi, (0x00, 0xB7, 0xC7, 0xF7, 0xE7, 0xD7), ('', '4', '5', '4', '5', '6')), 'STX': (Multi, (0x00, 0xBF, 0xCF, 0xFF, 0xEF, 0xDF), ('', '4', '5', '4', '5', '6')), 'SUB': (Multi, (0xA0, 0xB0, 0xC0, 0xF0, 0xE0, 0xD0), ('2', '3', '4', '3', '4', '5')), 'TST': (Multi, (0x00, 0x3D, 0x00, 0x7D, 0x6D, 0x00), ('', '4', '', '4', '5', '')), 'BCLR': (Bits, 0x11, '5'), 'BSET': (Bits, 0x10, '5'), 'BRCLR': (Bits, 0x01, '5'), 'BRSET': (Bits, 0x00, '5') } dec.Asm.Timing_Length = 2 dec.Asm.Memory = 0 if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = (1 << 13) - 1 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = True return
def CrossInit(): global Asm, Flags assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { 'CCF': (crz80.Inherent, 0x3F, '3'), 'CPL': (crz80.Inherent, 0x2F, '3'), 'DAA': (crz80.Inherent, 0x27, '4'), 'DI': (crz80.Inherent, 0xF3, '3'), 'EI': (crz80.Inherent, 0xFB, '3'), 'EXX': (crz80.Inherent, 0xD9, '3'), 'HALT': (crz80.Inherent, 0x76, '3'), 'NOP': (crz80.Inherent, 0x00, '3'), 'RLA': (crz80.Inherent, 0x17, '3'), 'RLCA': (crz80.Inherent, 0x07, '3'), 'RRA': (crz80.Inherent, 0x1F, '3'), 'RRCA': (crz80.Inherent, 0x0F, '3'), 'SCF': (crz80.Inherent, 0x37, '3'), 'CPD': (crz80.Inherent, 0xEDA9, '12'), 'CPDR': (crz80.Inherent, 0xEDB9, '12+'), 'CPI': (crz80.Inherent, 0xEDA1, '12'), 'CPIR': (crz80.Inherent, 0xEDB1, '12+'), 'IND': (crz80.Inherent, 0xEDAA, '12'), 'INDR': (crz80.Inherent, 0xEDBA, '12+'), 'INI': (crz80.Inherent, 0xEDA2, '12'), 'INIR': (crz80.Inherent, 0xEDB2, '12+'), 'LDD': (crz80.Inherent, 0xEDA8, '12'), 'LDDR': (crz80.Inherent, 0xEDB8, '12+'), 'LDI': (crz80.Inherent, 0xEDA0, '12'), 'LDIR': (crz80.Inherent, 0xEDB0, '12+'), 'NEG': (crz80.Inherent, 0xED44, '6'), 'OTDR': (crz80.Inherent, 0xEDBB, '14+'), 'OTDM': (crz80.Inherent, 0xED8B, '14'), 'OTDMR': (crz80.Inherent, 0xED9B, '14+'), 'OTIR': (crz80.Inherent, 0xEDB3, '12+'), 'OTIM': (crz80.Inherent, 0xED83, '12'), 'OTIMR': (crz80.Inherent, 0xED93, '12+'), 'OUTD': (crz80.Inherent, 0xEDAB, '12'), 'OUTI': (crz80.Inherent, 0xEDA3, '12'), 'RCF': (crz80.Inherent, 0x373F, '6'), 'RETI': (crz80.Inherent, 0xED4D, '12+'), 'RETN': (crz80.Inherent, 0xED45, '12'), 'RLD': (crz80.Inherent, 0xED6F, '16'), 'RRD': (crz80.Inherent, 0xED67, '16'), 'SLP': (crz80.Inherent, 0xED76, '8'), 'IM0': (crz80.Inherent, 0xED46, '6'), 'IM1': (crz80.Inherent, 0xED56, '6'), 'IM2': (crz80.Inherent, 0xED5E, '6'), 'LD': (crz80.Load, ), 'LD.A': (('A', 'B', 'C', 'D', 'E', 'H', 'L', '(HL)', '#', '(IX)', '(IY)', '(BC)', '(DE)', '(M)', 'I', 'R'), (0x7F, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x3E, 0xDD7E, 0xFD7E, 0x0A, 0x1A, 0x3A, 0xED57, 0xED5F), ('4', '4', '4', '4', '4', '4', '4', '6', '6', '14', '14', '6', '6', '12', '6', '6'), (0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 2, 0, 0)), 'LD.B': (('A', 'B', 'C', 'D', 'E', 'H', 'L', '(HL)', '#', '(IX)', '(IY)'), (0x47, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x06, 0xDD46, 0xFD46), ('4', '4', '4', '4', '4', '4', '4', '6', '6', '14', '14'), (0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1)), 'LD.C': (('A', 'B', 'C', 'D', 'E', 'H', 'L', '(HL)', '#', '(IX)', '(IY)'), (0x4F, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x0E, 0xDD4E, 0xFD4E), ('4', '4', '4', '4', '4', '4', '4', '6', '6', '14', '14'), (0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1)), 'LD.D': (('A', 'B', 'C', 'D', 'E', 'H', 'L', '(HL)', '#', '(IX)', '(IY)'), (0x57, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x16, 0xDD56, 0xFD56), ('4', '4', '4', '4', '4', '4', '4', '6', '6', '14', '14'), (0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1)), 'LD.E': (('A', 'B', 'C', 'D', 'E', 'H', 'L', '(HL)', '#', '(IX)', '(IY)'), (0x5F, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x1E, 0xDD5E, 0xFD5E), ('4', '4', '4', '4', '4', '4', '4', '6', '6', '14', '14'), (0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1)), 'LD.H': (('A', 'B', 'C', 'D', 'E', 'H', 'L', '(HL)', '#', '(IX)', '(IY)'), (0x67, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x26, 0xDD66, 0xFD66), ('4', '4', '4', '4', '4', '4', '4', '6', '6', '14', '14'), (0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1)), 'LD.L': (('A', 'B', 'C', 'D', 'E', 'H', 'L', '(HL)', '#', '(IX)', '(IY)'), (0x6F, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x2E, 0xDD6E, 0xFD6E), ('4', '4', '4', '4', '4', '4', '4', '6', '6', '14', '14'), (0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1)), 'LD.I': (('A', ), (0xED47, ), ('6', ), (0, )), 'LD.R': (('A', ), (0xED4F, ), ('6', ), (0, )), 'LD.(HL)': (('#', 'A', 'B', 'C', 'D', 'E', 'H', 'L'), (0x36, 0x77, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75), ('9', '7', '7', '7', '7', '7', '7', '7'), (1, 0, 0, 0, 0, 0, 0, 0)), 'LD.(IX)': (('#', 'A', 'B', 'C', 'D', 'E', 'H', 'L'), (0xDD36, 0xDD77, 0xDD70, 0xDD71, 0xDD72, 0xDD73, 0xDD74, 0xDD75), ('15', '15', '15', '15', '15', '15', '15', '15'), (4, 3, 3, 3, 3, 3, 3, 3)), 'LD.(IY)': (('#', 'A', 'B', 'C', 'D', 'E', 'H', 'L'), (0xFD36, 0xFD77, 0xFD70, 0xFD71, 0xFD72, 0xFD73, 0xFD74, 0xFD75), ('15', '15', '15', '15', '15', '15', '15', '15'), (4, 3, 3, 3, 3, 3, 3, 3)), 'LD.(BC)': (('A', ), (0x02, ), ('7', ), (0, )), 'LD.(DE)': (('A', ), (0x12, ), ('7', ), (0, )), 'LD.(M)': (('A', 'BC', 'DE', 'HL', 'SP', 'IX', 'IY'), (0x32, 0xED43, 0xED53, 0x22, 0xED73, 0xDD22, 0xFD22), ('13', '20', '20', '20', '20', '20', '20'), (5, 5, 5, 5, 5, 5, 5)), 'LD.BC': (('#', '(M)'), (0x01, 0xED4B), ('9', '18'), (2, 2)), 'LD.DE': (('#', '(M)'), (0x11, 0xED5B), ('9', '18'), (2, 2)), 'LD.HL': (('#', '(M)'), (0x21, 0x2A), ('9', '15'), (2, 2)), 'LD.SP': (('#', '(M)', 'HL', 'IX', 'IY'), (0x31, 0xED7B, 0xF9, 0xDDF9, 0xFDF9), ('9', '18', '4', '7', '7'), (2, 2, 0, 0, 0)), 'LD.IX': (('#', '(M)'), (0xDD21, 0xDD2A), ('12', '18'), (2, 2)), 'LD.IY': (('#', '(M)'), (0xFD21, 0xFD2A), ('12', '18'), (2, 2)), 'POP': (crz80.Stack, 0xC1, ('9', '12')), 'PUSH': (crz80.Stack, 0xC5, ('11', '14')), 'MLT': (crz80.Mult, 0xED4C, '17'), 'ADC': (crz80.Math, (0x88, 0xDD8E, 0xFD8E, 0xCE, 0xED4A), ('4/6', '14', '14', '6', '10')), 'ADD': (crz80.Math, (0x80, 0xDD86, 0xFD86, 0xC6, 0x09, 0xDD09, 0xFD09), ('4/6', '14', '14', '6', '7', '10', '10')), 'AND': (crz80.Math, (0xA0, 0xDDA6, 0xFDA6, 0xE6), ('4/6', '14', '14', '6')), 'CP': (crz80.Math, (0xB8, 0xDDBE, 0xFDBE, 0xFE), ('4/6', '14', '14', '6')), 'OR': (crz80.Math, (0xB0, 0xDDB6, 0xFDB6, 0xF6), ('4/6', '14', '14', '6')), 'SBC': (crz80.Math, (0x98, 0xDD9E, 0xFD9E, 0xDE, 0xED42), ('4/6', '14', '14', '6', '10')), 'SUB': (crz80.Math, (0x90, 0xDD96, 0xFD96, 0xD6), ('4/6', '14', '14', '6')), 'XOR': (crz80.Math, (0xA8, 0xDDAE, 0xFDAE, 0xEE), ('4/6', '14', '14', '6')), 'TST': (crz80.Math, (0xED04, 0x00, 0x00, 0xED64), ('7/10', '0', '0', '9')), 'DEC': (crz80.IncDec, (0x05, 0x35, 0xDD35, 0xFD35, 0x0B, 0xDD2B, 0xFD2B), ('4', '10', '18', '18', '4', '7', '7')), 'INC': (crz80.IncDec, (0x04, 0x34, 0xDD34, 0xFD34, 0x03, 0xDD23, 0xFD23), ('4', '10', '18', '18', '4', '7', '7')), 'CALL': (crz80.Jumps, (0xCD, 0xC4), ('16', '6+')), 'JP': (crz80.Jumps, (0xC3, 0xC2, 0xE9, 0xDDE9, 0xFDE9), ('9', '6+', '3', '6', '6')), 'JR': (crz80.Branch, (0x18, 0x38, 0x30, 0x28, 0x20), ('8', '6+', '6+', '6+', '6+')), 'DJNZ': (crz80.Branch, (0x10, ), ('7+', )), 'RET': (crz80.Returns, (0xC9, 0xC0), ('9', '5+')), 'RLC': (crz80.Singles, (0xCB00, 0xCB06, 0x06), ('7', '13', '19')), 'RL': (crz80.Singles, (0xCB10, 0xCB16, 0x16), ('7', '13', '19')), 'RRC': (crz80.Singles, (0xCB08, 0xCB0E, 0x0E), ('7', '13', '19')), 'RR': (crz80.Singles, (0xCB18, 0xCB1E, 0x1E), ('7', '13', '19')), 'SLA': (crz80.Singles, (0xCB20, 0xCB26, 0x26), ('7', '13', '19')), 'SRA': (crz80.Singles, (0xCB28, 0xCB2E, 0x2E), ('7', '13', '19')), 'SRL': (crz80.Singles, (0xCB38, 0xCB3E, 0x3E), ('7', '13', '19')), 'BIT': (crz80.Bits, (0xCB40, 0xCB46, 0x46), ('6', '9', '15')), 'RES': (crz80.Bits, (0xCB80, 0xCB86, 0x86), ('7', '13', '19')), 'SET': (crz80.Bits, (0xCBC0, 0xCBC6, 0xC6), ('7', '13', '19')), 'IN': (crz80.InOut, (0xED40, 0xDB), ('9', '9')), 'OUT': (crz80.InOut, (0xED41, 0xD3), ('10', '10')), 'INO': (crz80.InOut, (0xED00, 0x00), ('12', '0')), 'OUTO': (crz80.InOut, (0xED01, 0x00), ('13', '0')), 'TSTIO': (crz80.InOut, (0xED74, 0x00), ('12', '0')), 'EX': (crz80.Exch, (0xEB, 0x08, 0xE3, 0xDDE3, 0xFDE3), ('3', '4', '16', '19', '19')), 'IM': (crz80.IM, (0xED46, 0xED56, 0xED5E), '6'), 'RST': (crz80.Restart, 0xC7, '11') } dec.Asm.Memory = 0 length = 0 dec.Asm.Timing_Length = 3 if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = dec.MAX16 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = False return
def CrossInit(): global Asm, Flags assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { 'ASLA': (Inherent, 0xFAFF, '4'), 'CLRA': (Inherent, 0xFBFF, ''), 'CLRX': (Inherent, 0xB08000, '4'), 'CLRY': (Inherent, 0xB08100, '4'), 'CLX': (Inherent, 0xB08000, '4'), 'CLY': (Inherent, 0xB08100, '4'), 'COMA': (Inherent, 0xB4, '4'), 'DECA': (Inherent, 0xFFFF, '4'), 'DECX': (Inherent, 0xB8, '4'), 'DECY': (Inherent, 0xB9, '4'), 'DEX': (Inherent, 0xB8, '4'), 'DEY': (Inherent, 0xB9, '4'), 'INCA': (Inherent, 0xFEFF, '4'), 'INCX': (Inherent, 0xA8, '4'), 'INCY': (Inherent, 0xA9, '4'), 'INX': (Inherent, 0xA8, '4'), 'INY': (Inherent, 0xA9, '4'), 'NOP': (Inherent, 0x20, '2'), 'ROLA': (Inherent, 0xB5, '4'), 'RTI': (Inherent, 0xB2, '2'), 'RTS': (Inherent, 0xB3, '2'), 'TAX': (Inherent, 0xBC, '1'), 'TAY': (Inherent, 0xBD, '1'), 'TXA': (Inherent, 0xAC, '1'), 'TYA': (Inherent, 0xAD, '1'), # HC spcecific instructions 'STOP': (Inherent, 0xB6, '2'), 'WAIT': (Inherent, 0xB7, '2'), 'BCC': (Branch, 0x40, '2'), 'BCS': (Branch, 0x60, '2'), 'BEQ': (Branch, 0x20, '2'), 'BNE': (Branch, 0x00, '2'), 'BHS': (Branch, 0x40, '2'), 'BLO': (Branch, 0x60, '2'), 'JMP': (Jumps, 0x90, '4'), 'JSR': (Jumps, 0x80, '4'), 'LDA': (Multiple, (0xE8, 0xAC, 0xF8, 0xE0), ('4', '4', '4', '4')), 'STA': (Multiple, (0x00, 0xBC, 0xF9, 0xE1), ('', '4', '4', '4')), 'ADD': (Multiple, (0xEA, 0x00, 0xFA, 0xE2), ('4', '', '4', '4')), 'SUB': (Multiple, (0xEB, 0x00, 0xFB, 0xE3), ('4', '', '4', '4')), 'CMP': (Multiple, (0xEC, 0x00, 0xFC, 0xE4), ('4', '', '4', '4')), 'AND': (Multiple, (0xED, 0x00, 0xFD, 0xE5), ('4', '', '4', '4')), 'INC': (Multiple, (0x00, 0xA8, 0xFE, 0xE6), ('', '4', '4', '4')), 'DEC': (Multiple, (0x00, 0xB8, 0xFF, 0xE7), ('', '4', '4', '4')), 'LDXI': (Multiple, (0xB080, 0x00, 0x00, 0x00), ('4', '', '', '')), 'LDYI': (Multiple, (0xB081, 0x00, 0x00, 0x00), ('4', '', '', '')), 'LDX': (Multiple, (0xB080, 0x00, 0x00, 0x00), ('4', '', '', '')), 'LDY': (Multiple, (0xB081, 0x00, 0x00, 0x00), ('4', '', '', '')), 'MVI': (Move, 0xB0, '4'), 'BCLR': (Bits, 0xD0, '4'), 'BSET': (Bits, 0xD8, '4'), 'BRCLR': (Bits, 0xC0, '5'), 'BRSET': (Bits, 0xC8, '5') } dec.Asm.Timing_Length = 1 dec.Asm.Memory = 0 # Select code memory as default if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = (1 << 12) - 1 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = True return
def CrossInit(): """ Define the instruction table. Select code memory. Big endian model. Clear memory bank select. """ global Asm, Flags assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { 'MOV': (MovInst, '0'), 'MOVC': (MovCInst, '0'), 'MOVX': (MovXInst, '0'), # A C BIT 'CLR': (BitInst, (0xE4, 0xC3, 0xC2), ('1', '1', '1')), 'CPL': (BitInst, (0xF4, 0xB3, 0xB2), ('1', '1', '1')), 'SETB': (BitInst, (0x00, 0xD3, 0xD2), ('0', '1', '1')), 'DA': (Specials, 0xD4, '1'), 'DIV': (Specials, 0x84, '4'), 'MUL': (Specials, 0xA4, '4'), 'NOP': (Specials, 0x00, '1'), 'RET': (Specials, 0x22, '2'), 'RETI': (Specials, 0x32, '2'), 'RL': (Specials, 0x23, '1'), 'RLC': (Specials, 0x33, '1'), 'RR': (Specials, 0x03, '1'), 'RRC': (Specials, 0x13, '1'), 'SWAP': (Specials, 0xC4, '1'), # DIR A R0..R7 @R0..@R1 DPTR 'DEC': (Singles, (0x15, 0x14, 0x18, 0x16, 0x00), ('1', '1', '1', '1', '0')), 'INC': (Singles, (0x05, 0x04, 0x08, 0x06, 0xA3), ('1', '1', '1', '1', '2')), 'POP': (Singles, (0xD0, 0x00, 0x00, 0x00, 0x00), ('2', '0', '0', '0', '0')), 'PUSH': (Singles, (0xC0, 0x00, 0x00, 0x00, 0x00), ('2', '0', '0', '0', '0')), 'ACALL': (Jumps, 0x11, '2'), 'AJMP': (Jumps, 0x01, '2'), 'LCALL': (Jumps, 0x12, '2'), 'LJMP': (Jumps, 0x02, '2'), 'CALL': (Jumps, 0x91, '0'), 'JMP': (Jumps, 0x81, '0'), # A,Rn A,DIR A,@Ri A,# DIR,A DIR,# C,BIT C,/BIT 'ADD': (Math, (0x28, 0x25, 0x26, 0x24, 0x00, 0x00, 0x00, 0x00), ('1', '1', '1', '1', '0', '0', '0', '0')), 'ADDC': (Math, (0x38, 0x35, 0x36, 0x34, 0x00, 0x00, 0x00, 0x00), ('1', '1', '1', '1', '0', '0', '0', '0')), 'ANL': (Math, (0x58, 0x55, 0x56, 0x54, 0x52, 0x53, 0x82, 0xB0), ('1', '1', '1', '1', '1', '2', '2', '2')), 'ORL': (Math, (0x48, 0x45, 0x46, 0x44, 0x42, 0x43, 0x72, 0xA0), ('1', '1', '1', '1', '1', '2', '2', '2')), 'SUBB': (Math, (0x98, 0x95, 0x96, 0x94, 0x00, 0x00, 0x00, 0x00), ('1', '1', '1', '1', '0', '0', '0', '0')), 'XCH': (Math, (0xC8, 0xC5, 0xC6, 0x00, 0x00, 0x00, 0x00, 0x00), ('1', '1', '1', '0', '0', '0', '0', '0')), 'XRL': (Math, (0x68, 0x65, 0x66, 0x64, 0x62, 0x63, 0x00, 0x00), ('1', '1', '1', '1', '1', '2', '0', '0')), # A,DIR,REL A,#,REL Rn,#,REL @Ri,#,REL 'CJNE': (BranchTest, 0xB5, 0xB4, 0xB8, 0xB6), # Rn,REL DIR,REL 'DJNZ': (BranchLoop, 0xD8, 0xD5), 'JB': (BranchBit, 0x20, '2'), 'JBC': (BranchBit, 0x10, '2'), 'JC': (Branch, 0x40, '2'), 'JNB': (BranchBit, 0x30, '2'), 'JNC': (Branch, 0x50, '2'), 'JNZ': (Branch, 0x70, '2'), 'JZ': (Branch, 0x60, '2'), 'SJMP': (Branch, 0x80, '2'), 'XCHD': (XchdInst, 0xD6) } dec.Asm.Timing_Length = 1 dec.Asm.Memory = 0 if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = dec.MAX16 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = True dec.Asm.RB8051 = 0 return
def CrossInit(): global Asm, Flags, Error_List assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { # Instructions which don't require an operand and are 1 byte long 'HALT': (Implied, 0x00, '8'), 'XAE': (Implied, 0x01, '7'), 'CCL': (Implied, 0x02, '5'), 'SCL': (Implied, 0x03, '5'), 'DINT': (Implied, 0x04, '6'), 'IEN': (Implied, 0x05, '6'), 'CSA': (Implied, 0x06, '5'), 'CAS': (Implied, 0x07, '6'), 'NOP': (Implied, 0x08, '5'), 'SIO': (Implied, 0x19, '5'), 'SR': (Implied, 0x1C, '5'), 'SRL': (Implied, 0x1D, '5'), 'RR': (Implied, 0x1E, '5'), 'RRL': (Implied, 0x1F, '5'), 'LDE': (Implied, 0x40, '6'), 'ANE': (Implied, 0x50, '6'), 'ORE': (Implied, 0x58, '6'), 'XRE': (Implied, 0x60, '6'), 'DAE': (Implied, 0x68, '11'), 'ADE': (Implied, 0x70, '7'), 'CAE': (Implied, 0x78, '8'), # Instructions which require a ptr as operand are one byte long 'XPAL': (SinglePtr, 0x30, '8'), 'XPAH': (SinglePtr, 0x34, '8'), 'XPPC': (SinglePtr, 0x3C, '7'), 'RET': (SinglePtr, 0x3C, '7'), # Instructions which expect a single byte as data # THese are 2 bytes long 'DLY': (Immediate, 0x8F, '13+'), 'LDI': (Immediate, 0xC4, '10'), 'ANI': (Immediate, 0xD4, '10'), 'ORI': (Immediate, 0xDC, '10'), 'XRI': (Immediate, 0xE4, '10'), 'DAI': (Immediate, 0xEC, '15'), 'ADI': (Immediate, 0xF4, '11'), 'CAI': (Immediate, 0xFC, '12'), # Instructions which expect a displacement and a pointer # These are 2 bytes long 'JMP': (Transfer, 0x90, '11'), 'JP': (Transfer, 0x94, '9/11'), 'JZ': (Transfer, 0x98, '9/11'), 'JNZ': (Transfer, 0x9C, '9/11'), 'ILD': (Transfer, 0xA8, '22'), 'DLD': (Transfer, 0xB8, '22'), # Instructions which expect a displacement or an indirect displacement # and a ptr. These are also 2 bytes long. 'LD': (MemRef, 0xC0, '18'), 'ST': (MemRef, 0xC8, '18'), 'AND': (MemRef, 0xD0, '18'), 'OR': (MemRef, 0xD8, '18'), 'XOR': (MemRef, 0xE0, '18'), 'DAD': (MemRef, 0xE8, '23'), 'ADD': (MemRef, 0xF0, '19'), 'CAD': (MemRef, 0xF8, '20'), # There's one Pseudo instructions which is the Jump to Subroutine # instruction. It is translated into 5 real instructions, simulating # one non existent instruction. 'JS': (Pseudo, 0, '43') } errors.Error_List[dec.Cross.Name + 'pagex']\ = 'Instruction crossed a page boundary' errors.Error_List[dec.Cross.Name + 'pagebeg']\ = 'Instruction starts at page boundary' errors.Error_List[dec.Cross.Name + 'offset']\ = 'Offset is -128, E register conflict' dec.Asm.Timing_Length = 4 # Longest timing string dec.Asm.Memory = 0 # Select code memory as default if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = dec.MAX16 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = False # Arbitrary mode chosen return
def CrossInit(): global Asm, Flags, Cross assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { 'RETLW' : (Immediate, 0x800, '2'), 'CALL' : (Immediate, 0x900, '2'), 'GOTO' : (Immediate, 0xA00, '2'), 'B' : (Immediate, 0xA00, '2'), 'MOVLW' : (Immediate, 0xC00, '1'), 'IORLW' : (Immediate, 0xD00, '1'), 'ANDLW' : (Immediate, 0xE00, '1'), 'XORLW' : (Immediate, 0xF00, '1'), 'CLRW' : (Implied, 0x040, '1'), 'CLRWDT': (Implied, 0x004, '1'), 'NOP' : (Implied, 0x000, '1'), 'OPTION': (Implied, 0x002, '1'), 'SLEEP' : (Implied, 0x003, '1'), 'CLRC' : (Implied, 0x403, '1'), 'CLRDC' : (Implied, 0x423, '1'), 'CLRZ' : (Implied, 0x443, '1'), 'SETC' : (Implied, 0x503, '1'), 'SETDC' : (Implied, 0x523, '1'), 'SETZ' : (Implied, 0x543, '1'), 'SKPC' : (Implied, 0x703, '1-2'), 'SKPDC' : (Implied, 0x723, '1-2'), 'SKPNC' : (Implied, 0x603, '1-2'), 'SKPNDC': (Implied, 0x623, '1-2'), 'SKPNZ' : (Implied, 0x643, '1-2'), 'SKPZ' : (Implied, 0x743, '1-2'), 'CLRF' : (FileOnly, 0x060, '1'), 'MOVWF' : (FileOnly, 0x020, '1'), 'TRIS' : (FileOnly, 0x000, '1'), 'MOVFW' : (FileOnly, 0x200, '1'), 'TSTF' : (FileOnly, 0x220, '1'), 'ADDWF' : (FileW, 0x1C0, '1'), 'ANDWF' : (FileW, 0x140, '1'), 'COMF' : (FileW, 0x240, '1'), 'DECF' : (FileW, 0x0C0, '1'), 'DECFSZ': (FileW, 0x2C0, '1-2'), 'INCF' : (FileW, 0x280, '1'), 'INCFSZ': (FileW, 0x3C0, '1-2'), 'IORWF' : (FileW, 0x100, '1'), 'MOVF' : (FileW, 0x200, '1'), 'RLF' : (FileW, 0x340, '1'), 'RRF' : (FileW, 0x300, '1'), 'SUBWF' : (FileW, 0x080, '1'), 'SWAPF' : (FileW, 0x380, '1'), 'XORWF' : (FileW, 0x180, '1'), 'BCF' : (FileBit, 0x400 , '1'), 'BSF' : (FileBit, 0x500 , '1'), 'BTFSC' : (FileBit, 0x600 , '1-2'), 'BTFSS' : (FileBit, 0x700 , '1-2'), 'BC' : (Branches, 0x603, '2-3'), 'BDC' : (Branches, 0x623, '2-3'), 'BNC' : (Branches, 0x703, '2-3'), 'BNDC' : (Branches, 0x723, '2-3'), 'BNZ' : (Branches, 0x743, '2-3'), 'BZ' : (Branches, 0x643, '2-3'), 'ADDCF' : (Pseudo, 0x603, 0x280, '2'), 'ADDDCF': (Pseudo, 0x623, 0x280, '2'), 'NEGF' : (Pseudo, 0x260, 0x280, '2'), 'SUBCF' : (Pseudo, 0x603, 0x0C0, '2'), 'SUBDCF': (Pseudo, 0x623, 0x0C0, '2'), 'LCALL' : (Long, 0x900), 'LGOTO' : (Long, 0xA00) } dec.Asm.Timing_Length = 3 dec.Asm.Memory = 0 # Select code memory as default if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = 511 dec.Flags.BigEndian = False # Change target factor to 2 if dec.Asm.PP_TA_Factor != 2: if dec.Asm.PP_Address != dec.Asm.TA_Address or dec.Asm.PP_Address !=\ dec.Asm.PH_Address: # Oops, this is complicated. Let's warn the programmer errors.DoWarning('taconfusion', True) # Set the instruction size and double the target address dec.Asm.PP_TA_Factor = 2 dec.Asm.TA_Address *= 2 dec.Asm.TablePic12 = -1 errors.Error_List[dec.Cross.Name + 'tcrossed'] =\ 'Table crossed page boundary' errors.Error_List[dec.Cross.Name + 'codemem'] =\ 'Directive only allowed within Code memory' errors.Error_List[dec.Cross.Name + 'progmem'] =\ 'Directive only allowed beyond program memory' dec.Cross.SaveByte = eval('SaveByte')
def CrossInit(): """ Initialize this cross overlay. """ global Asm, Flags assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { 'ABX': (Implied, 0x3A, '3'), 'ASLA': (Implied, 0x48, '2'), 'ASLB': (Implied, 0x58, '2'), 'ASRA': (Implied, 0x47, '2'), 'ASRB': (Implied, 0x57, '2'), 'CLRA': (Implied, 0x4F, '2'), 'CLRB': (Implied, 0x5F, '2'), 'COMA': (Implied, 0x43, '2'), 'COMB': (Implied, 0x53, '2'), 'DAA': (Implied, 0x19, '2'), 'DECA': (Implied, 0x4A, '2'), 'DECB': (Implied, 0x5A, '2'), 'INCA': (Implied, 0x4C, '2'), 'INCB': (Implied, 0x5C, '2'), 'LSLA': (Implied, 0x48, '2'), 'LSLB': (Implied, 0x58, '2'), 'LSRA': (Implied, 0x44, '2'), 'LSRB': (Implied, 0x54, '2'), 'MUL': (Implied, 0x3D, '11'), 'NEGA': (Implied, 0x40, '2'), 'NEGB': (Implied, 0x50, '2'), 'NOP': (Implied, 0x12, '2'), 'ROLA': (Implied, 0x49, '2'), 'ROLB': (Implied, 0x59, '2'), 'RORA': (Implied, 0x46, '2'), 'RORB': (Implied, 0x56, '2'), 'RTI': (Implied, 0x3B, '15'), 'RTS': (Implied, 0x39, '5'), 'SEX': (Implied, 0x1D, '2'), 'SWI': (Implied, 0x3F, '19'), 'SWI2': (Implied, 0x103F, '20'), 'SWI3': (Implied, 0x113F, '20'), 'SYNC': (Implied, 0x13, '2'), 'TSTA': (Implied, 0x4D, '2'), 'TSTB': (Implied, 0x5D, '2'), 'ABA': (Implied, 0x3404ABE0, '12'), 'ASLD': (Implied, 0x5849, '4'), 'ASRD': (Implied, 0x4756, '4'), 'CBA': (Implied, 0x3404A1E0, '12'), 'CLC': (Implied, 0x1CFE, '3'), 'CLF': (Implied, 0x1CBF, '3'), 'CLI': (Implied, 0x1CEF, '3'), 'CLIF': (Implied, 0x1CAF, '3'), 'CLRD': (Implied, 0x4F5F, '4'), 'CLV': (Implied, 0x1CFD, '3'), 'COMD': (Implied, 0x4353, '4'), 'DES': (Implied, 0x327F, '5'), 'DEX': (Implied, 0x301F, '5'), 'DEY': (Implied, 0x313F, '5'), 'DEU': (Implied, 0x335F, '5'), 'INS': (Implied, 0x3261, '5'), 'INU': (Implied, 0x3341, '5'), 'INX': (Implied, 0x3001, '5'), 'INY': (Implied, 0x3121, '5'), 'LSLD': (Implied, 0x5849, '4'), 'LSRD': (Implied, 0x4456, '4'), 'PSHA': (Implied, 0x3402, '6'), 'PSHB': (Implied, 0x3404, '6'), 'PSHCC': (Implied, 0x3401, '6'), 'PSHD': (Implied, 0x3406, '7'), 'PSHDP': (Implied, 0x3408, '6'), 'PSHPC': (Implied, 0x3480, '6'), 'PSHX': (Implied, 0x3410, '6'), 'PSHY': (Implied, 0x3420, '6'), 'PULA': (Implied, 0x3502, '6'), 'PULB': (Implied, 0x3504, '6'), 'PULCC': (Implied, 0x3501, '6'), 'PULD': (Implied, 0x3506, '7'), 'PULDP': (Implied, 0x3508, '6'), 'PULPC': (Implied, 0x3580, '6'), 'PULX': (Implied, 0x3510, '6'), 'PULY': (Implied, 0x3520, '6'), 'ROLD': (Implied, 0x5949, '4'), 'RORD': (Implied, 0x4656, '4'), 'SBA': (Implied, 0x3404A0E0, '12'), 'SEC': (Implied, 0x1A01, '3'), 'SEF': (Implied, 0x1A40, '3'), 'SEI': (Implied, 0x1A10, '3'), 'SEIF': (Implied, 0x1A50, '3'), 'SEV': (Implied, 0x1A02, '3'), 'TAB': (Implied, 0x1F894D, '9'), 'TAP': (Implied, 0x1F8A, '7'), 'TBA': (Implied, 0x1F984D, '9'), 'TPA': (Implied, 0x1FA8, '7'), 'TSX': (Implied, 0x1F41, '7'), 'TXS': (Implied, 0x1F14, '7'), 'WAI': (Implied, 0x3CFF, '20'), 'BCC': (Branch, 0x24, '3'), 'BCS': (Branch, 0x25, '3'), 'BEQ': (Branch, 0x27, '3'), 'BGE': (Branch, 0x2C, '3'), 'BGT': (Branch, 0x2E, '3'), 'BHI': (Branch, 0x22, '3'), 'BHS': (Branch, 0x24, '3'), 'BLE': (Branch, 0x2F, '3'), 'BLO': (Branch, 0x25, '3'), 'BLS': (Branch, 0x23, '3'), 'BLT': (Branch, 0x2D, '3'), 'BMI': (Branch, 0x2B, '3'), 'BNE': (Branch, 0x26, '3'), 'BPL': (Branch, 0x2A, '3'), 'BRA': (Branch, 0x20, '3'), 'BRN': (Branch, 0x21, '3'), 'BSR': (Branch, 0x8D, '7'), 'BVC': (Branch, 0x28, '3'), 'BVS': (Branch, 0x29, '3'), 'LBCC': (LBranch, 0x1024, '5+'), 'LBCS': (LBranch, 0x1025, '5+'), 'LBEQ': (LBranch, 0x1027, '5+'), 'LBGE': (LBranch, 0x102C, '5+'), 'LBGT': (LBranch, 0x102E, '5+'), 'LBHI': (LBranch, 0x1022, '5+'), 'LBHS': (LBranch, 0x1024, '5+'), 'LBLE': (LBranch, 0x102F, '5+'), 'LBLO': (LBranch, 0x1025, '5+'), 'LBLS': (LBranch, 0x1023, '5+'), 'LBLT': (LBranch, 0x102D, '5+'), 'LBMI': (LBranch, 0x102B, '5+'), 'LBNE': (LBranch, 0x1026, '5+'), 'LBPL': (LBranch, 0x102A, '5+'), 'LBRA': (LBranch, 0x16, '55'), 'LBRN': (LBranch, 0x1021, '5+'), 'LBSR': (LBranch, 0x17, '9'), 'LBVC': (LBranch, 0x1028, '5+'), 'LBVS': (LBranch, 0x1029, '5+'), 'ADCA': (Multi, (0x89, 0x99, 0xA9, 0xB9), ('2', '4', '4', '5'), False), 'ADCB': (Multi, (0xC9, 0xD9, 0xE9, 0xF9), ('2', '4', '4', '5'), False), 'ADDA': (Multi, (0x8B, 0x9B, 0xAB, 0xBB), ('2', '4', '4', '5'), False), 'ADDB': (Multi, (0xCB, 0xDB, 0xEB, 0xFB), ('2', '4', '4', '5'), False), 'ADDD': (Multi, (0xC3, 0xD3, 0xE3, 0xF3), ('4', '6', '6', '7'), True), 'ANDA': (Multi, (0x84, 0x94, 0xA4, 0xB4), ('2', '4', '4', '5'), False), 'ANDB': (Multi, (0xC4, 0xD4, 0xE4, 0xF4), ('2', '4', '4', '5'), False), 'ANDCC': (Multi, (0x1C, 0x00, 0x00, 0x00), ('3', '0', '0', '0'), False), 'ASL': (Multi, (0x00, 0x08, 0x68, 0x78), ('0', '6', '6', '7'), False), 'ASR': (Multi, (0x00, 0x07, 0x67, 0x77), ('0', '6', '6', '7'), False), 'BITA': (Multi, (0x85, 0x95, 0xA5, 0xB5), ('2', '4', '4', '5'), False), 'BITB': (Multi, (0xC5, 0xD5, 0xE5, 0xF5), ('2', '4', '4', '5'), False), 'CLR': (Multi, (0x00, 0x0F, 0x6F, 0x7F), ('0', '6', '6', '7'), False), 'CMPA': (Multi, (0x81, 0x91, 0xA1, 0xB1), ('2', '4', '4', '5'), False), 'CMPB': (Multi, (0xC1, 0xD1, 0xE1, 0xF1), ('2', '4', '4', '5'), False), 'CMPD': (Multi, (0x1083, 0x1093, 0x10A3, 0x10B3), ('5', '7', '7', '8'), True), 'CMPS': (Multi, (0x118C, 0x119C, 0x11AC, 0x11BC), ('5', '7', '7', '8'), True), 'CMPU': (Multi, (0x1183, 0x1193, 0x11A3, 0x11B3), ('5', '7', '7', '8'), True), 'CMPX': (Multi, (0x8C, 0x9C, 0xAC, 0xBC), ('4', '6', '6', '7'), True), 'CMPY': (Multi, (0x108C, 0x109C, 0x10AC, 0x10BC), ('5', '7', '7', '8'), True), 'COM': (Multi, (0x00, 0x03, 0x63, 0x73), ('0', '6', '6', '7'), False), 'CWAI': (Multi, (0x3C, 0x00, 0x00, 0x00), ('20', '0', '0', '0'), False), 'DEC': (Multi, (0x00, 0x0A, 0x6A, 0x7A), ('0', '6', '6', '7'), False), 'EORA': (Multi, (0x88, 0x98, 0xA8, 0xB8), ('2', '4', '4', '5'), False), 'EORB': (Multi, (0xC8, 0xD8, 0xE8, 0xF8), ('2', '4', '4', '5'), False), 'INC': (Multi, (0x00, 0x0C, 0x6C, 0x7C), ('0', '6', '6', '7'), False), 'JMP': (Multi, (0x00, 0x0E, 0x6E, 0x7E), ('0', '3', '3', '4'), False), 'JSR': (Multi, (0x00, 0x9D, 0xAD, 0xBD), ('0', '7', '7', '8'), False), 'LDA': (Multi, (0x86, 0x96, 0xA6, 0xB6), ('2', '4', '4', '5'), False), 'LDAA': (Multi, (0x86, 0x96, 0xA6, 0xB6), ('2', '4', '4', '5'), False), 'LDB': (Multi, (0xC6, 0xD6, 0xE6, 0xF6), ('2', '4', '4', '5'), False), 'LDAB': (Multi, (0xC6, 0xD6, 0xE6, 0xF6), ('2', '4', '4', '5'), False), 'LDD': (Multi, (0xCC, 0xDC, 0xEC, 0xFC), ('3', '5', '5', '6'), True), 'LDAD': (Multi, (0xCC, 0xDC, 0xEC, 0xFC), ('3', '5', '5', '6'), True), 'LDS': (Multi, (0x10CE, 0x10DE, 0x10EE, 0x10FE), ('4', '6', '6', '7'), True), 'LDU': (Multi, (0xCE, 0xDE, 0xEE, 0xFE), ('3', '5', '5', '6'), True), 'LDX': (Multi, (0x8E, 0x9E, 0xAE, 0xBE), ('3', '5', '5', '6'), True), 'LDY': (Multi, (0x108E, 0x109E, 0x10AE, 0x10BE), ('4', '6', '6', '7'), True), 'LEAS': (Multi, (0x00, 0x00, 0x32, 0x00), ('0', '0', '4', '0'), False), 'LEAU': (Multi, (0x00, 0x00, 0x33, 0x00), ('0', '0', '4', '0'), False), 'LEAX': (Multi, (0x00, 0x00, 0x30, 0x00), ('0', '0', '4', '0'), False), 'LEAY': (Multi, (0x00, 0x00, 0x31, 0x00), ('0', '0', '4', '0'), False), 'LSL': (Multi, (0x00, 0x08, 0x68, 0x78), ('0', '6', '6', '7'), False), 'LSR': (Multi, (0x00, 0x04, 0x64, 0x74), ('0', '6', '6', '7'), False), 'NEG': (Multi, (0x00, 0xFF, 0x60, 0x70), ('0', '6', '6', '7'), False), 'ORA': (Multi, (0x8A, 0x9A, 0xAA, 0xBA), ('2', '4', '4', '5'), False), 'ORB': (Multi, (0xCA, 0xDA, 0xEA, 0xFA), ('2', '4', '4', '5'), False), 'ORCC': (Multi, (0x1A, 0x00, 0x00, 0x00), ('3', '0', '0', '0'), False), 'ROL': (Multi, (0x00, 0x09, 0x69, 0x79), ('0', '6', '6', '7'), False), 'ROR': (Multi, (0x00, 0x06, 0x66, 0x76), ('0', '6', '6', '7'), False), 'SBCA': (Multi, (0x82, 0x92, 0xA2, 0xB2), ('2', '4', '4', '5'), False), 'SBCB': (Multi, (0xC2, 0xD2, 0xE2, 0xF2), ('2', '4', '4', '5'), False), 'STA': (Multi, (0x00, 0x97, 0xA7, 0xB7), ('0', '4', '4', '5'), False), 'STAA': (Multi, (0x00, 0x97, 0xA7, 0xB7), ('0', '4', '4', '5'), False), 'STB': (Multi, (0x00, 0xD7, 0xE7, 0xF7), ('0', '4', '4', '5'), False), 'STAB': (Multi, (0x00, 0xD7, 0xE7, 0xF7), ('0', '4', '4', '5'), False), 'STD': (Multi, (0x00, 0xDD, 0xED, 0xFD), ('0', '5', '5', '6'), False), 'STAD': (Multi, (0x00, 0xDD, 0xED, 0xFD), ('0', '5', '5', '6'), False), 'STS': (Multi, (0x00, 0x10DF, 0x10EF, 0x10FF), ('0', '6', '6', '7'), False), 'STU': (Multi, (0x00, 0xDF, 0xEF, 0xFF), ('0', '5', '5', '6'), False), 'STX': (Multi, (0x00, 0x9F, 0xAF, 0xBF), ('0', '5', '5', '6'), False), 'STY': (Multi, (0x00, 0x109F, 0x10AF, 0x10BF), ('0', '6', '6', '7'), False), 'SUBA': (Multi, (0x80, 0x90, 0xA0, 0xB0), ('2', '4', '4', '5'), False), 'SUBB': (Multi, (0xC0, 0xD0, 0xE0, 0xF0), ('2', '4', '4', '5'), False), 'SUBD': (Multi, (0x83, 0x93, 0xA3, 0xB3), ('4', '6', '6', '7'), True), 'TST': (Multi, (0x00, 0x0D, 0x6D, 0x7D), ('0', '6', '6', '7'), False), 'PSHS': (Stack, 0x34, 5), 'PSHU': (Stack, 0x36, 5), 'PULS': (Stack, 0x35, 5), 'PULU': (Stack, 0x37, 5), 'EXG': (Exchange, 0x1E, '7'), 'TFR': (Exchange, 0x1F, '7') } errors.Error_List['6809double'] = 'Repeated register(s) ignored' dec.Asm.Timing_Length = 2 dec.Asm.Memory = 0 if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = dec.MAX16 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = True dec.Asm.DP6809 = 0 return
def CrossInit(): global Asm, Flags assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { # Inherent operand instructions 'LAA': (Inherent, 0xC0, '0'), 'LAB': (Inherent, 0xC1, '0'), 'LAC': (Inherent, 0xC2, '0'), 'LAD': (Inherent, 0xC3, '0'), 'LAE': (Inherent, 0xC4, '0'), 'LAH': (Inherent, 0xC5, '0'), 'LAL': (Inherent, 0xC6, '0'), 'LAM': (Inherent, 0xC7, '0'), 'LBA': (Inherent, 0xC8, '0'), 'LBB': (Inherent, 0xC9, '0'), # Not defined, probably NOP 'LBC': (Inherent, 0xCA, '0'), 'LBD': (Inherent, 0xCB, '0'), 'LBE': (Inherent, 0xCC, '0'), 'LBH': (Inherent, 0xCD, '0'), 'LBL': (Inherent, 0xCE, '0'), 'LBM': (Inherent, 0xCF, '0'), 'LCA': (Inherent, 0xD0, '0'), 'LCB': (Inherent, 0xD1, '0'), 'LCC': (Inherent, 0xD2, '0'), # Not defined, probably NOP 'LCD': (Inherent, 0xD3, '0'), 'LCE': (Inherent, 0xD4, '0'), 'LCH': (Inherent, 0xD5, '0'), 'LCL': (Inherent, 0xD6, '0'), 'LCM': (Inherent, 0xD7, '0'), 'LDA': (Inherent, 0xD8, '0'), 'LDB': (Inherent, 0xD9, '0'), 'LDC': (Inherent, 0xDA, '0'), 'LDD': (Inherent, 0xDB, '0'), # Not defined, probably NOP 'LDE': (Inherent, 0xDC, '0'), 'LDH': (Inherent, 0xDD, '0'), 'LDL': (Inherent, 0xDE, '0'), 'LDM': (Inherent, 0xDF, '0'), 'LEA': (Inherent, 0xE0, '0'), 'LEB': (Inherent, 0xE1, '0'), 'LEC': (Inherent, 0xE2, '0'), 'LED': (Inherent, 0xE3, '0'), 'LEE': (Inherent, 0xE4, '0'), # Not defined, probably NOP 'LEH': (Inherent, 0xE5, '0'), 'LEL': (Inherent, 0xE6, '0'), 'LEM': (Inherent, 0xE7, '0'), 'LHA': (Inherent, 0xE8, '0'), 'LHB': (Inherent, 0xE9, '0'), 'LHC': (Inherent, 0xEA, '0'), 'LHD': (Inherent, 0xEB, '0'), 'LHE': (Inherent, 0xEC, '0'), 'LHH': (Inherent, 0xED, '0'), # Not defined, probably NOP 'LHL': (Inherent, 0xEE, '0'), 'LHM': (Inherent, 0xEF, '0'), 'LLA': (Inherent, 0xF0, '0'), 'LLB': (Inherent, 0xF1, '0'), 'LLC': (Inherent, 0xF2, '0'), 'LLD': (Inherent, 0xF3, '0'), 'LLE': (Inherent, 0xF4, '0'), 'LLH': (Inherent, 0xF5, '0'), 'LLL': (Inherent, 0xF6, '0'), # Not defined, probably NOP 'LLM': (Inherent, 0xF7, '0'), 'LMA': (Inherent, 0xF8, '0'), 'LMB': (Inherent, 0xF9, '0'), 'LMC': (Inherent, 0xFA, '0'), 'LMD': (Inherent, 0xFB, '0'), 'LME': (Inherent, 0xFC, '0'), 'LMH': (Inherent, 0xFD, '0'), 'LML': (Inherent, 0xFE, '0'), 'ACA': (Inherent, 0x88, '0'), 'ACB': (Inherent, 0x89, '0'), 'ACC': (Inherent, 0x8A, '0'), 'ACD': (Inherent, 0x8B, '0'), 'ACE': (Inherent, 0x8C, '0'), 'ACH': (Inherent, 0x8D, '0'), 'ACL': (Inherent, 0x8E, '0'), 'ACM': (Inherent, 0x8F, '0'), 'ADA': (Inherent, 0x80, '0'), 'ADB': (Inherent, 0x81, '0'), 'ADC': (Inherent, 0x82, '0'), 'ADD': (Inherent, 0x83, '0'), 'ADE': (Inherent, 0x84, '0'), 'ADH': (Inherent, 0x85, '0'), 'ADL': (Inherent, 0x86, '0'), 'ADM': (Inherent, 0x87, '0'), 'SBA': (Inherent, 0x98, '0'), 'SBB': (Inherent, 0x99, '0'), 'SBC': (Inherent, 0x9A, '0'), 'SBD': (Inherent, 0x9B, '0'), 'SBE': (Inherent, 0x9C, '0'), 'SBH': (Inherent, 0x9D, '0'), 'SBL': (Inherent, 0x9E, '0'), 'SBM': (Inherent, 0x9F, '0'), 'SUA': (Inherent, 0x90, '0'), 'SUB': (Inherent, 0x91, '0'), 'SUC': (Inherent, 0x92, '0'), 'SUD': (Inherent, 0x93, '0'), 'SUE': (Inherent, 0x94, '0'), 'SUH': (Inherent, 0x95, '0'), 'SUL': (Inherent, 0x96, '0'), 'SUM': (Inherent, 0x97, '0'), 'NDA': (Inherent, 0xA0, '0'), 'NDB': (Inherent, 0xA1, '0'), 'NDC': (Inherent, 0xA2, '0'), 'NDD': (Inherent, 0xA3, '0'), 'NDE': (Inherent, 0xA4, '0'), 'NDH': (Inherent, 0xA5, '0'), 'NDL': (Inherent, 0xA6, '0'), 'NDM': (Inherent, 0xA7, '0'), 'XRA': (Inherent, 0xA8, '0'), 'XRB': (Inherent, 0xA9, '0'), 'XRC': (Inherent, 0xAA, '0'), 'XRD': (Inherent, 0xAB, '0'), 'XRE': (Inherent, 0xAC, '0'), 'XRH': (Inherent, 0xAD, '0'), 'XRL': (Inherent, 0xAE, '0'), 'XRM': (Inherent, 0xAF, '0'), 'ORA': (Inherent, 0xB0, '0'), 'ORB': (Inherent, 0xB1, '0'), 'ORC': (Inherent, 0xB2, '0'), 'ORD': (Inherent, 0xB3, '0'), 'ORE': (Inherent, 0xB4, '0'), 'ORH': (Inherent, 0xB5, '0'), 'ORL': (Inherent, 0xB6, '0'), 'ORM': (Inherent, 0xB7, '0'), 'CPA': (Inherent, 0xB8, '0'), 'CPB': (Inherent, 0xB9, '0'), 'CPC': (Inherent, 0xBA, '0'), 'CPD': (Inherent, 0xBB, '0'), 'CPE': (Inherent, 0xBC, '0'), 'CPH': (Inherent, 0xBD, '0'), 'CPL': (Inherent, 0xBE, '0'), 'CPM': (Inherent, 0xBF, '0'), 'NOP': (Inherent, 0xC0, '0'), 'SLC': (Inherent, 0x02, '0'), 'SRC': (Inherent, 0x0A, '0'), 'HALT': (Inherent, 0x00, '0'), 'RETURN': (Inherent, 0x07, '0'), 'RFC': (Inherent, 0x03, '0'), 'RFZ': (Inherent, 0x0B, '0'), 'RFS': (Inherent, 0x13, '0'), 'RFP': (Inherent, 0x1B, '0'), 'RTC': (Inherent, 0x23, '0'), 'RTZ': (Inherent, 0x2B, '0'), 'RTS': (Inherent, 0x33, '0'), 'RTP': (Inherent, 0x3B, '0'), 'INPUT': (Inherent, 0x41, '0'), 'ALPHA': (Inherent, 0x18, '0'), 'BETA': (Inherent, 0x10, '0'), 'PUSH': (Inherent, 0x38, '0'), 'POP': (Inherent, 0x30, '0'), 'DI': (Inherent, 0x20, '0'), 'EI': (Inherent, 0x28, '0'), # Immediate address instructions 'LA': (Immediate, 0x06, '0'), 'LB': (Immediate, 0x0E, '0'), 'LC': (Immediate, 0x16, '0'), 'LD': (Immediate, 0x1E, '0'), 'LE': (Immediate, 0x26, '0'), 'LH': (Immediate, 0x2E, '0'), 'LL': (Immediate, 0x36, '0'), 'AC': (Immediate, 0x0C, '0'), 'AD': (Immediate, 0x04, '0'), 'SB': (Immediate, 0x1C, '0'), 'SU': (Immediate, 0x14, '0'), 'ND': (Immediate, 0x24, '0'), 'XR': (Immediate, 0x2C, '0'), 'OR': (Immediate, 0x34, '0'), 'CP': (Immediate, 0x3C, '0'), # Jump instructions 'JMP': (Jumps, 0x44, '0'), 'JFC': (Jumps, 0x40, '0'), 'JFZ': (Jumps, 0x48, '0'), 'JFS': (Jumps, 0x50, '0'), 'JFP': (Jumps, 0x58, '0'), 'JTC': (Jumps, 0x60, '0'), 'JTZ': (Jumps, 0x68, '0'), 'JTS': (Jumps, 0x70, '0'), 'JTP': (Jumps, 0x78, '0'), 'CALL': (Jumps, 0x46, '0'), 'CFC': (Jumps, 0x42, '0'), 'CFZ': (Jumps, 0x4A, '0'), 'CFS': (Jumps, 0x52, '0'), 'CFP': (Jumps, 0x5A, '0'), 'CTC': (Jumps, 0x62, '0'), 'CTZ': (Jumps, 0x6A, '0'), 'CTS': (Jumps, 0x72, '0'), 'CTP': (Jumps, 0x7A, '0'), # Output instruction 'EX': (Output, 0x00, '0') } dec.Asm.Timing_Length = 0 # No timing information available. dec.Asm.Memory = 0 # Select code memory as default if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = (1 << 14) - 1 dec.Asm.PP_TA_Factor = 1 # Set the actual factor between PP and TA dec.Flags.BigEndian = False # Set actual value return
def CrossInit(): global Asm, Flags assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { # Implied addressing mode 'NOP': (Implied, 0x00, '8'), 'WRM': (Implied, 0xE0, '8'), 'WMP': (Implied, 0xE1, '8'), 'WRR': (Implied, 0xE2, '8'), 'WPM': (Implied, 0xE3, '8'), 'WR0': (Implied, 0xE4, '8'), 'WR1': (Implied, 0xE5, '8'), 'WR2': (Implied, 0xE6, '8'), 'WR3': (Implied, 0xE7, '8'), 'SBM': (Implied, 0xE8, '8'), 'RDM': (Implied, 0xE9, '8'), 'RDR': (Implied, 0xEA, '8'), 'ADM': (Implied, 0xEB, '8'), 'RD0': (Implied, 0xEC, '8'), 'RD1': (Implied, 0xED, '8'), 'RD2': (Implied, 0xEE, '8'), 'RD3': (Implied, 0xEF, '8'), 'CLB': (Implied, 0xF0, '8'), 'CLC': (Implied, 0xF1, '8'), 'IAC': (Implied, 0xF2, '8'), 'CMC': (Implied, 0xF3, '8'), 'CMA': (Implied, 0xF4, '8'), 'RAL': (Implied, 0xF5, '8'), 'RAR': (Implied, 0xF6, '8'), 'TCC': (Implied, 0xF7, '8'), 'DAC': (Implied, 0xF8, '8'), 'TCS': (Implied, 0xF9, '8'), 'STC': (Implied, 0xFA, '8'), 'DAA': (Implied, 0xFB, '8'), 'KBP': (Implied, 0xFC, '8'), 'DCL': (Implied, 0xFD, '8'), # 4040 only instructions 'HLT': (Implied, 0x01, '0'), 'BBS': (Implied, 0x02, '0'), 'LCR': (Implied, 0x03, '0'), 'OR4': (Implied, 0x04, '0'), 'OR5': (Implied, 0x05, '0'), 'AN6': (Implied, 0x06, '0'), 'AN7': (Implied, 0x07, '0'), 'DB0': (Implied, 0x08, '0'), 'DB1': (Implied, 0x09, '0'), 'SB0': (Implied, 0x0A, '0'), 'SB1': (Implied, 0x0B, '0'), 'EIN': (Implied, 0x0C, '0'), 'DIN': (Implied, 0x0D, '0'), 'RPM': (Implied, 0x0E, '0'), # Conditional jumps 'JCN': (Conditional, 0x10, '16'), 'ISZ': (Conditional, 0x70, '16'), # Pointer pair with data instructions 'FIM': (PointerData, 0x20, '16'), # Pointer pair instructions 'SRC': (Pointer, 0x21, '8'), 'FIN': (Pointer, 0x30, '8'), 'JIN': (Pointer, 0x31, '8'), # Absolute addressing 'JUN': (Absolute, 0x40, '16'), 'JMS': (Absolute, 0x50, '16'), # Register instructions 'INC': (Register, 0x60, '8'), 'ADD': (Register, 0x80, '8'), 'SUB': (Register, 0x90, '8'), 'LD': (Register, 0xA0, '8'), 'XCH': (Register, 0xB0, '8'), # Immediate nibble instructions 'BBL': (ImmediateNibl, 0xC0, '8'), 'LDM': (ImmediateNibl, 0xD0, '8'), # Alternative branch instructions 'JNT': (Branch, 0x11, '16'), 'JC': (Branch, 0x12, '16'), 'JZ': (Branch, 0x14, '16'), 'JT': (Branch, 0x19, '16'), 'JNC': (Branch, 0x1A, '16'), 'JNZ': (Branch, 0x1C, '16') } dec.Asm.Timing_Length = 2 dec.Asm.Memory = 0 # Select code memory as default if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = (1 << 12) - 1 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = False return
def CrossInit(): global Asm, Flags assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { 'IFC': (Inherent, 0x19, '1'), 'IFNC': (Inherent, 0x1F, '1'), 'INTR': (Inherent, 0x00, '5'), 'INVC': (Inherent, 0x12, '1'), 'NOP': (Inherent, 0x1C, '1'), 'RC': (Inherent, 0x1E, '1'), 'RET': (Inherent, 0x17, '5'), 'RETI': (Inherent, 0x18, '5'), 'SC': (Inherent, 0x1D, '1'), 'JP': (Relative, 0xC0, '1'), 'JMP': (Jumps, (0x24, 0x7E), ('4', '3')), 'JSR': (Jumps, (0x23, 0x7F), ('5', '3')), 'CLR': (Singles, (0x16, 0x0F, 0x7D), ('1', '1', '2')), 'DEC': (Singles, (0x1A, 0x0C, 0x7B), ('1', '1', '2')), 'INC': (Singles, (0x1B, 0x0D, 0x7C), ('1', '1', '2')), 'RLC': (Singles, (0x15, 0x00, 0x79), ('1', '', '2')), 'RRC': (Singles, (0x13, 0x00, 0x7A), ('1', '', '2')), 'ADC': (Multiple, (0x60, 0x42, 0x02, 0x70, 0x00, 0x00, 0x00), ('2', '2', '1', '3', '', '', '')), 'ADD': (Multiple, (0x66, 0x43, 0x03, 0x71, 0x00, 0x00, 0x00), ('2', '2', '1', '3', '', '', '')), 'AND': (Multiple, (0x61, 0x50, 0x04, 0x72, 0x00, 0x00, 0x00), ('2', '2', '1', '3', '', '', '')), 'IFEQ': (Multiple, (0x65, 0x56, 0x09, 0x76, 0x26, 0x20, 0x00), ('2', '2', '1', '2', '3', '3', '')), 'IFGT': (Multiple, (0x67, 0x55, 0x0A, 0x77, 0x27, 0x00, 0x00), ('2', '2', '1', '2', '3', '', '')), 'IFLT': (Multiple, (0x00, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00), ('', '', '', '', '3', '', '')), 'IFNE': (Multiple, (0x57, 0x54, 0x0B, 0x78, 0x00, 0x00, 0x00), ('2', '2', '1', '2', '', '', '')), 'LD': (Multiple, (0x51, 0x46, 0x0E, 0x52, 0x25, 0x21, 0x22), ('2', '2', '1', '3', '3', '3', '3')), 'OR': (Multiple, (0x62, 0x44, 0x05, 0x73, 0x00, 0x00, 0x00), ('2', '2', '1', '3', '', '', '')), 'ST': (Multiple, (0x00, 0x47, 0x11, 0x40, 0x00, 0x00, 0x00), ('', '2', '2', '3', '', '', '')), 'SUBC': (Multiple, (0x63, 0x53, 0x06, 0x74, 0x00, 0x00, 0x00), ('2', '2', '1', '3', '', '', '')), 'XOR': (Multiple, (0x64, 0x45, 0x07, 0x75, 0x00, 0x00, 0x00), ('2', '2', '1', '3', '', '', '')), 'IFBIT': (Bits, (0xA0, 0x58, 0x00), ('1', '2', '')), 'LDC': (Bits, (0x00, 0x80, 0x00), ('', '2', '')), 'RBIT': (Bits, (0x00, 0x68, 0xB8), ('', '2', '2')), 'SBIT': (Bits, (0x00, 0x48, 0xB0), ('', '2', '2')), 'STC': (Bits, (0x00, 0x88, 0x00), ('', '2', '')) } dec.Asm.Timing_Length = 1 dec.Asm.Memory = 0 # Select code memory as default if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = (1 << 12) - 1 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = False dec.Ace_Maxjmp = 0x0FFF dec.Ace_Minjmp = 0x0800 return
def CrossInit(): global Asm, Flags assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { 'LD' : (Load,), 'ADC' : (Math, (0x12, 0x13, 0x14, 0x15, 0x16, 0x17), ('6', '6', '10', '10', '10', '10')), 'ADD' : (Math, (0x02, 0x03, 0x04, 0x05, 0x06, 0x07), ('6', '6', '10', '10', '10', '10')), 'AND' : (Math, (0x52, 0x53, 0x54, 0x55, 0x56, 0x57), ('6', '6', '10', '10', '10', '10')), 'CP' : (Math, (0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7), ('6', '6', '10', '10', '10', '10')), 'SBC' : (Math, (0x32, 0x33, 0x34, 0x35, 0x36, 0x37), ('6', '6', '10', '10', '10', '10')), 'SUB' : (Math, (0x22, 0x23, 0x24, 0x25, 0x26, 0x27), ('6', '6', '10', '10', '10', '10')), 'TCM' : (Math, (0x62, 0x63, 0x64, 0x65, 0x66, 0x67), ('6', '6', '10', '10', '10', '10')), 'OR' : (Math, (0x42, 0x43, 0x44, 0x45, 0x46, 0x47), ('6', '6', '10', '10', '10', '10')), 'TM' : (Math, (0x72, 0x73, 0x74, 0x75, 0x76, 0x77), ('6', '6', '10', '10', '10', '10')), 'XOR' : (Math, (0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7), ('6', '6', '10', '10', '10', '10')), 'CLR' : (Single, (0xB0, 0xB1), ('6', '6')), 'COM' : (Single, (0x60, 0x61), ('6', '6')), 'DA' : (Single, (0x40, 0x41), ('8', '8')), 'DEC' : (Single, (0x00, 0x01), ('6', '6')), 'INC' : (Single, (0x20, 0x21), ('6', '6')), # One special opcode for r 'RL' : (Single, (0x90, 0x91), ('6', '6')), 'RLC' : (Single, (0x10, 0x11), ('6', '6')), 'RR' : (Single, (0xE0, 0xE1), ('6', '6')), 'RRC' : (Single, (0xC0, 0xC1), ('6', '6')), 'SRA' : (Single, (0xD0, 0xD1), ('6', '6')), 'SWAP': (Single, (0xF0, 0xF1), ('6', '6')), 'POP' : (Single, (0x50, 0x51), ('10', '10')), 'PUSH': (Single, (0x70, 0x71), ('10+', '10')), 'SRP' : (Single, (0x31,), ('6',)), 'DECW': (SingleW, (0x80, 0x81), ('10', '10')), 'INCW': (SingleW, (0xA0, 0xA1), ('10', '10')), 'CCF' : (Implied, 0xEF, '6'), 'DI' : (Implied, 0x8F, '6'), 'EI' : (Implied, 0x9F, '6'), 'HALT': (Implied, 0x7F, '6'), 'IRET': (Implied, 0xBF, '16'), 'NOP' : (Implied, 0xFF, '6'), 'RCF' : (Implied, 0xCF, '6'), 'RET' : (Implied, 0xAF, '14'), 'SCF' : (Implied, 0xDF, '6'), 'STOP': (Implied, 0x6F, '6'), 'WDH' : (Implied, 0x4F, '6'), 'WDT' : (Implied, 0x5F, '6'), 'DJNZ': (Branch, 10, '10+'), 'JR' : (Branch, 11, '10+'), 'CALL': (Jumps, (0xD6, 0xD4), ('20', '20')), 'JP' : (Jumps, (0x8D, 0x30), ('12', '8')), 'LDC' : (Memory, (0xC2, 0xD2), ('12', '12')), 'LDCI': (Memory, (0xC3, 0xD3), ('18', '18')), 'LDE' : (Memory, (0x82, 0x92), ('12', '12')), 'LDEI': (Memory, (0x83, 0x93), ('18,' '18')) } dec.Asm.Memory = 0 length = 0 dec.Asm.Timing_Length = 3 if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = dec.MAX16 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = True dec.Asm.Z8rp = 0 return
def CrossInit(): """ Initialize this cross overlay. Mainly create two dictionaries. One holding all 6502 instructions and one holding the Sweet16 instructions. Set default mode to 6502 instructions. Also add one extra warning for the 6502 JMP (IND) bug """ global Asm, Flags, Error_List, sweet16, Sweet16_Mnemonics, modelindex assem.CheckVersions(crossversion, minversion) sweet16 = False if dec.Cross.Name == 'cr6502': # Index to 6502 instruction times modelindex = 2 else: # Index to 65C02 and 65SC02 instruction times modelindex = 3 # The instructions directory contains a tuple with: # function which handles this opcode, # integer value of opcode, or a tupple with opcodes # string or tupple with 6502 cycle time(s) # string or tupple with 65C02 cycle time(s) # If the final cycle time is 0 that particular instruction # or addressing mode doesn't exist for the selected # processor. dec.Asm.Instructions = { 'BRK': (Implied, 0x00, '7', '7'), 'CLC': (Implied, 0x18, '2', '2'), 'CLD': (Implied, 0xD8, '2', '2'), 'CLI': (Implied, 0x58, '2', '2'), 'CLV': (Implied, 0xB8, '2', '2'), 'DEA': (Implied, 0x3A, '0', '2'), 'DEX': (Implied, 0xCA, '2', '2'), 'DEY': (Implied, 0x88, '2', '2'), 'INA': (Implied, 0x1A, '0', '2'), 'INX': (Implied, 0xE8, '2', '2'), 'INY': (Implied, 0xC8, '2', '2'), 'NOP': (Implied, 0xEA, '2', '2'), 'PHA': (Implied, 0x48, '3', '3'), 'PHP': (Implied, 0x08, '3', '3'), 'PHX': (Implied, 0xDA, '0', '3'), 'PHY': (Implied, 0x5A, '0', '3'), 'PLA': (Implied, 0x68, '4', '4'), 'PLP': (Implied, 0x28, '4', '4'), 'PLX': (Implied, 0xFA, '0', '4'), 'PLY': (Implied, 0x7A, '0', '4'), 'RTI': (Implied, 0x40, '6', '6'), 'RTS': (Implied, 0x60, '6', '6'), 'SEC': (Implied, 0x38, '2', '2'), 'SED': (Implied, 0xF8, '2', '2'), 'SEI': (Implied, 0x78, '2', '2'), 'STP': (Implied, 0xDB, '0', '3'), 'TAX': (Implied, 0xAA, '2', '2'), 'TAY': (Implied, 0xA8, '2', '2'), 'TSX': (Implied, 0xBA, '2', '2'), 'TXA': (Implied, 0x8A, '2', '2'), 'TXS': (Implied, 0x9A, '2', '2'), 'TYA': (Implied, 0x98, '2', '2'), 'WAI': (Implied, 0xCB, '0', '3'), 'BCC': (Branch, 0x90, '2**', '2**'), 'BCS': (Branch, 0xB0, '2**', '2**'), 'BEQ': (Branch, 0xF0, '2**', '2**'), 'BMI': (Branch, 0x30, '2**', '2**'), 'BNE': (Branch, 0xD0, '2**', '2**'), 'BPL': (Branch, 0x10, '2**', '2**'), 'BRA': (Branch, 0x80, '0', '2**'), 'BVC': (Branch, 0x50, '2**', '2**'), 'BVS': (Branch, 0x70, '2**', '2**'), # implied, imm, zp, abs, (zp,x) (zp),y, zp,x abs,x zp,y abs,y (zp) 'ADC': (Multi, (0x00, 0x69, 0x65, 0x6D, 0x61, 0x71, 0x75, 0x7D, 0x00, 0x79, 0x72), ('0', '2', '3', '4', '6', '5*', '4', '4*', '0', '4*', '0'), ('0', '2', '3', '4', '6', '5*', '4', '4*', '0', '4*', '5')), 'ADD': (Multi, (0x00, 0x69, 0x65, 0x6D, 0x61, 0x71, 0x75, 0x7D, 0x00, 0x79, 0x72), ('0', '4', '5', '6', '8', '5*', '6', '6*', '0', '6*', '0'), ('0', '4', '5', '6', '8', '5*', '6', '6*', '0', '6*', '5')), 'AND': (Multi, (0x00, 0x29, 0x25, 0x2D, 0x21, 0x31, 0x35, 0x3D, 0x00, 0x39, 0x32), ('0', '2', '3', '4', '6', '5*', '4', '4*', '0', '4*', '0'), ('0', '2', '3', '4', '6', '5*', '4', '4*', '0', '4*', '5')), 'ASL': (Multi, (0x0A, 0x00, 0x06, 0x0E, 0x00, 0x00, 0x16, 0x1E, 0x00, 0x00, 0x00), ('2', '0', '5', '6', '0', '0', '6', '7', '0', '0', '0'), ('2', '0', '5', '6', '0', '0', '6', '6*', '0', '0', '0')), 'BIT': (Multi, (0x00, 0x89, 0x24, 0x2C, 0x00, 0x00, 0x34, 0x3C, 0x00, 0x00, 0x00), ('0', '0', '3', '4', '0', '0', '0', '0', '0', '0', '0'), ('0', '2', '3', '4', '0', '0', '4', '4', '0', '0', '0')), 'CMP': (Multi, (0x00, 0xC9, 0xC5, 0xCD, 0xC1, 0xD1, 0xD5, 0xDD, 0x00, 0xD9, 0xD2), ('0', '2', '3', '4', '6', '5*', '4', '4*', '0', '4*', '0'), ('0', '2', '3', '4', '6', '5*', '4', '4*', '0', '4*', '5')), 'CPX': (Multi, (0x00, 0xE0, 0xE4, 0xEC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), ('0', '2', '3', '4', '0', '0', '0', '0', '0', '0', '0'), ('0', '2', '3', '4', '0', '0', '0', '0', '0', '0', '0')), 'CPY': (Multi, (0x00, 0xC0, 0xC4, 0xCC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), ('0', '2', '3', '4', '0', '0', '0', '0', '0', '0', '0'), ('0', '2', '3', '4', '0', '0', '0', '0', '0', '0', '0')), 'DEC': (Multi, (0x3A, 0x00, 0xC6, 0xCE, 0x00, 0x00, 0xD6, 0xDE, 0x00, 0x00, 0x00), ('0', '0', '5', '6', '0', '0', '6', '7', '0', '0', '0'), ('2', '0', '5', '6', '0', '0', '6', '7', '0', '0', '0')), 'EOR': (Multi, (0x00, 0x49, 0x45, 0x4D, 0x41, 0x51, 0x55, 0x5D, 0x00, 0x59, 0x52), ('0', '2', '3', '4', '6', '5*', '4', '4*', '0', '4*', '0'), ('0', '2', '3', '4', '6', '5*', '4', '4*', '0', '4*', '5')), 'INC': (Multi, (0x1A, 0x00, 0xE6, 0xEE, 0x00, 0x00, 0xF6, 0xFE, 0x00, 0x05, 0x00), ('0', '0', '5', '6', '0', '0', '6', '7', '0', '0', '0'), ('2', '0', '5', '6', '0', '0', '6', '7', '0', '0', '0')), 'JMP': (Multi, (0x00, 0x00, 0x00, 0x4C, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6C), ('0', '0', '0', '3', '0', '0', '0', '0', '0', '0', '5'), ('0', '0', '0', '3', '6', '0', '0', '0', '0', '0', '6')), 'JSR': (Multi, (0x00, 0x00, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), ('0', '0', '0', '6', '0', '0', '0', '0', '0', '0', '0'), ('0', '0', '0', '6', '0', '0', '0', '0', '0', '0', '0')), 'LDA': (Multi, (0x00, 0xA9, 0xA5, 0xAD, 0xA1, 0xB1, 0xB5, 0xBD, 0x00, 0xB9, 0xB2), ('0', '2', '3', '4', '6', '5*', '4', '4*', '0', '4*', '0'), ('0', '2', '3', '4', '6', '5*', '4', '4*', '0', '4*', '5')), 'LDX': (Multi, (0x00, 0xA2, 0xA6, 0xAE, 0x00, 0x09, 0x00, 0x00, 0xB6, 0xBE, 0x00), ('0', '2', '3', '4', '0', '0', '0', '0', '4', '4*', '0'), ('0', '2', '3', '4', '0', '0', '0', '0', '4', '4*', '0')), 'LDY': (Multi, (0x00, 0xA0, 0xA4, 0xAC, 0x00, 0x00, 0xB4, 0xBC, 0x00, 0x00, 0x00), ('0', '2', '3', '4', '0', '0', '4', '4*', '0', '0', '0'), ('0', '2', '3', '4', '0', '0', '4', '4*', '0', '0', '0')), 'LSR': (Multi, (0x4A, 0x00, 0x46, 0x4E, 0x00, 0x00, 0x56, 0x5E, 0x00, 0x00, 0x00), ('2', '0', '5', '6', '0', '0', '6', '7', '0', '0', '0'), ('2', '0', '5', '6', '0', '0', '6', '7', '0', '0', '0')), 'ORA': (Multi, (0x00, 0x09, 0x05, 0x0D, 0x01, 0x11, 0x15, 0x1D, 0x00, 0x19, 0x12), ('0', '2', '3', '4', '6', '5*', '4', '4*', '0', '4*', '0'), ('0', '2', ' 3', '4', '6', '5*', '4', '4*', '0', '4*', '5')), 'ROL': (Multi, (0x2A, 0x09, 0x26, 0x2E, 0x00, 0x00, 0x36, 0x3E, 0x00, 0x00, 0x00), ('2', '0', '5', '6', '0', '0', '6', '7', '0', '0', '0'), ('2', '0', '5', '6', '0', '0', '6', '7', '0', '0', '0')), 'ROR': (Multi, (0x6A, 0x00, 0x66, 0x6E, 0x00, 0x00, 0x76, 0x7E, 0x00, 0x00, 0x00), ('2', '0', '5', '6', '0', '0', '6', '7', '0', '0', '0'), ('2', '0', '5', '6', '0', '0', '6', '7', '0', '0', '0')), 'SBC': (Multi, (0x00, 0xE9, 0xE5, 0xED, 0xE1, 0xF1, 0xF5, 0xFD, 0x00, 0xF9, 0xF2), ('0', '2', '3', '4', '6', '5*', '4', '4*', '0', '4*', '0'), ('0', '2', '3', '4', '6', '5*', '4', '4*', '0', '4*', '5')), 'SUB': (Multi, (0x00, 0xE9, 0xE5, 0xED, 0xE1, 0xF1, 0xF5, 0xFD, 0x00, 0xF9, 0xF2), ('0', '4', '5', '6', '8', '7*', '6', '6*', '0', '6*', '0'), ('0', '4', '5', '6', '8', '7*', '6', '6*', '0', '6*', '5')), 'STA': (Multi, (0x00, 0x00, 0x85, 0x8D, 0x81, 0x91, 0x95, 0x9D, 0x00, 0x99, 0x92), ('0', '0', '2', '4', '6', '6', '4', '5', '0', '5', '0'), ('0', '0', '3', '4', '6', '6', '4', '5', '0', '5', '5')), 'STX': (Multi, (0x00, 0x00, 0x86, 0x8E, 0x00, 0x00, 0x00, 0x00, 0x96, 0x00, 0x00), ('0', '0', '3', '4', '0', '0', '0', '0', '4', '0', '0'), ('0', '0', '3', '4', '0', '0', '0', '0', '4', '0', '0')), 'STY': (Multi, (0x00, 0x00, 0x84, 0x8C, 0x00, 0x00, 0x94, 0x00, 0x00, 0x00, 0x00), ('0', '0', '3', '4', '0', '0', '4', '0', '0', '0', '0'), ('0', '0', '3', '4', '0', '0', '4', '0', '0', '0', '0')), 'STZ': (Multi, (0x00, 0x00, 0x64, 0x9C, 0x00, 0x00, 0x74, 0x9E, 0x00, 0x00, 0x00), ('0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0'), ('0', '0', '3', '4', '0', '0', '4', '5', '0', '0', '0')), 'TRB': (Multi, (0x00, 0x00, 0x14, 0x1C, 0x00, 0x00, 0x94, 0x00, 0x00, 0x00, 0x00), ('0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0'), ('0', '0', '5', '6', '0', '0', '4', '0', '0', '0', '0')), 'TSB': (Multi, (0x00, 0x00, 0x04, 0x0C, 0x00, 0x00, 0x94, 0x00, 0x00, 0x00, 0x00), ('0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0'), ('0', '0', '5', '6', '0', '0', '4', '0', '0', '0', '0')), 'BBR0': (BitMan, 0x0F, '5'), 'BBR1': (BitMan, 0x1F, '5'), 'BBR2': (BitMan, 0x2F, '5'), 'BBR3': (BitMan, 0x3F, '5'), 'BBR4': (BitMan, 0x4F, '5'), 'BBR5': (BitMan, 0x5F, '5'), 'BBR6': (BitMan, 0x6F, '5'), 'BBR7': (BitMan, 0x7F, '5'), 'BBR': (BitMan, 0x0F, '5'), 'BBS0': (BitMan, 0x8F, '5'), 'BBS1': (BitMan, 0x9F, '5'), 'BBS2': (BitMan, 0xAF, '5'), 'BBS3': (BitMan, 0xBF, '5'), 'BBS4': (BitMan, 0xCF, '5'), 'BBS5': (BitMan, 0xDF, '5'), 'BBS6': (BitMan, 0xEF, '5'), 'BBS7': (BitMan, 0xFF, '5'), 'BBS': (BitMan, 0x8F, '5'), 'RMB0': (BitMan, 0x07, '5'), 'RMB1': (BitMan, 0x17, '5'), 'RMB2': (BitMan, 0x27, '5'), 'RMB3': (BitMan, 0x37, '5'), 'RMB4': (BitMan, 0x47, '5'), 'RMB5': (BitMan, 0x57, '5'), 'RMB6': (BitMan, 0x67, '5'), 'RMB7': (BitMan, 0x77, '5'), 'RMB': (BitMan, 0x07, '5'), 'SMB0': (BitMan, 0x87, '5'), 'SMB1': (BitMan, 0x97, '5'), 'SMB2': (BitMan, 0xA7, '5'), 'SMB3': (BitMan, 0xB7, '5'), 'SMB4': (BitMan, 0xC7, '5'), 'SMB5': (BitMan, 0xD7, '5'), 'SMB6': (BitMan, 0xE7, '5'), 'SMB7': (BitMan, 0xF7, '5'), 'SMB': (BitMan, 0x87, '5') } Sweet16_Mnemonics = { 'BK': (Single16, 0x0A), 'RS': (Single16, 0x0B), 'RTN': (Single16, 0x00), 'BR': (Branch16, 0x01), 'BNC': (Branch16, 0x02), 'BC': (Branch16, 0x03), 'BP': (Branch16, 0x04), 'BM': (Branch16, 0x05), 'BZ': (Branch16, 0x06), 'BNZ': (Branch16, 0x07), 'BM1': (Branch16, 0x08), 'BNM1': (Branch16, 0x09), 'BS': (Branch16, 0x0C), 'SET': (Sweet16, 0x10, 0x00), 'LD': (Sweet16, 0x20, 0x40), 'ST': (Sweet16, 0x30, 0x50), 'LDD': (Sweet16, 0x00, 0x60), 'STD': (Sweet16, 0x00, 0x70), 'POP': (Sweet16, 0x00, 0x80), 'STP': (Sweet16, 0x00, 0x90), 'ADD': (Sweet16, 0xA0, 0x00), 'SUB': (Sweet16, 0xB0, 0x00), 'POPD': (Sweet16, 0x00, 0xC0), 'CPR': (Sweet16, 0xD0, 0x00), 'INR': (Sweet16, 0xE0, 0x00), 'DCR': (Sweet16, 0xF0, 0x00) } dec.Asm.Timing_Length = 3 # Maximum length of instruction time errors.Error_List['6502bug'] = '6502 JMP (IND) bug at $xxFF' dec.Asm.Memory = 0 if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) # Allow assembled output files > 64 KB (max 32 MB for ProDOS volume) # NOTE: This is the maximum output ADDRESS and not the max file SIZE # i.e. # dec.Asm.Max_Address = 0 # # .or $100 # .db 1 ; FAIL; address $0100 > $0000 # # .or $0 # .db 1 ; PASS; address $0000 <= $0000 #dec.Asm.Max_Address = dec.MAX16 dec.Asm.Max_Address = 0x1FFFFFF dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = False return
def CrossInit(): global Asm, Flags assem.CheckVersions(crossversion, minversion) # The instructions directory contains a tuple with: # function which handles this opcode, # integer value of opcode # string with cycle time(s) of this instruction on an 8085 dec.Asm.Instructions = { 'MOV': (MovInst, 0xC0, '5'), 'MVI': (MviInst, 0x06, '8'), 'INR': (IncDec, 0x08, '5'), 'DCR': (IncDec, 0x09, '5'), 'ADD': (Math, 0x80, '5'), 'ADC': (Math, 0x88, '5'), 'SUB': (Math, 0x90, '5'), 'SBB': (Math, 0x98, '5'), 'ANA': (Math, 0xA0, '5'), 'XRA': (Math, 0xA8, '5'), 'ORA': (Math, 0xB0, '5'), 'CMP': (Math, 0xB8, '5'), 'JMP': (Jumps, 0x44, '11'), 'JFC': (Jumps, 0x40, '9/11'), 'JNC': (Jumps, 0x40, '9/11'), 'JFZ': (Jumps, 0x48, '9/11'), 'JNZ': (Jumps, 0x48, '9/11'), 'JFS': (Jumps, 0x50, '9/11'), 'JP': (Jumps, 0x50, '9/11'), 'JFP': (Jumps, 0x58, '9/11'), 'JPO': (Jumps, 0x58, '9/11'), 'JTC': (Jumps, 0x60, '9/11'), 'JC': (Jumps, 0x60, '9/11'), 'JTZ': (Jumps, 0x68, '9/11'), 'JZ': (Jumps, 0x68, '9/11'), 'JTS': (Jumps, 0x70, '9/11'), 'JM': (Jumps, 0x70, '9/11'), 'JTP': (Jumps, 0x78, '9/11'), 'JPE': (Jumps, 0x78, '9/11'), 'CAL': (Jumps, 0x46, '11'), 'CALL': (Jumps, 0x46, '11'), 'CFC': (Jumps, 0x42, '9/11'), 'CNC': (Jumps, 0x42, '9/11'), 'CFZ': (Jumps, 0x4A, '9/11'), 'CNZ': (Jumps, 0x4A, '9/11'), 'CFS': (Jumps, 0x52, '9/11'), 'CP': (Jumps, 0x52, '9/11'), 'CFP': (Jumps, 0x5A, '9/11'), 'CPO': (Jumps, 0x5A, '9/11'), 'CTC': (Jumps, 0x62, '9/11'), 'CC': (Jumps, 0x62, '9/11'), 'CTZ': (Jumps, 0x6A, '9/11'), 'CZ': (Jumps, 0x6A, '9/11'), 'CTS': (Jumps, 0x72, '9/11'), 'CM': (Jumps, 0x72, '9/11'), 'CTP': (Jumps, 0x7A, '9/11'), 'CPE': (Jumps, 0x7A, '9/11'), 'LAA': (Inherent, 0xC0, '5'), 'LAB': (Inherent, 0xC1, '5'), 'LAC': (Inherent, 0xC2, '5'), 'LAD': (Inherent, 0xC3, '5'), 'LAE': (Inherent, 0xC4, '5'), 'LAH': (Inherent, 0xC5, '5'), 'LAL': (Inherent, 0xC6, '5'), 'LAM': (Inherent, 0xC7, '8'), 'LBA': (Inherent, 0xC8, '5'), 'LBB': (Inherent, 0xC9, '5'), 'LBC': (Inherent, 0xCA, '5'), 'LBD': (Inherent, 0xCB, '5'), 'LBE': (Inherent, 0xCC, '5'), 'LBH': (Inherent, 0xCD, '5'), 'LBL': (Inherent, 0xCE, '5'), 'LBM': (Inherent, 0xCF, '8'), 'LCA': (Inherent, 0xD0, '5'), 'LCB': (Inherent, 0xD1, '5'), 'LCC': (Inherent, 0xD2, '5'), 'LCD': (Inherent, 0xD3, '5'), 'LCE': (Inherent, 0xD4, '5'), 'LCH': (Inherent, 0xD5, '5'), 'LCL': (Inherent, 0xD6, '5'), 'LCM': (Inherent, 0xD7, '8'), 'LDA': (Inherent, 0xD8, '5'), 'LDB': (Inherent, 0xD9, '5'), 'LDC': (Inherent, 0xDA, '5'), 'LDD': (Inherent, 0xDB, '5'), 'LDE': (Inherent, 0xDC, '5'), 'LDH': (Inherent, 0xDD, '5'), 'LDL': (Inherent, 0xDE, '5'), 'LDM': (Inherent, 0xDF, '8'), 'LEA': (Inherent, 0xE0, '5'), 'LEB': (Inherent, 0xE1, '5'), 'LEC': (Inherent, 0xE2, '5'), 'LED': (Inherent, 0xE3, '5'), 'LEE': (Inherent, 0xE4, '5'), 'LEH': (Inherent, 0xE5, '5'), 'LEL': (Inherent, 0xE6, '5'), 'LEM': (Inherent, 0xE7, '8'), 'LHA': (Inherent, 0xE8, '5'), 'LHB': (Inherent, 0xE9, '5'), 'LHC': (Inherent, 0xEA, '5'), 'LHD': (Inherent, 0xEB, '5'), 'LHE': (Inherent, 0xEC, '5'), 'LHH': (Inherent, 0xED, '5'), 'LHL': (Inherent, 0xEE, '5'), 'LHM': (Inherent, 0xEF, '8'), 'LLA': (Inherent, 0xF0, '5'), 'LLB': (Inherent, 0xF1, '5'), 'LLC': (Inherent, 0xF2, '5'), 'LLD': (Inherent, 0xF3, '5'), 'LLE': (Inherent, 0xF4, '5'), 'LLH': (Inherent, 0xF5, '5'), 'LLL': (Inherent, 0xF6, '5'), 'LLM': (Inherent, 0xF7, '8'), 'LMA': (Inherent, 0xF8, '7'), 'LMB': (Inherent, 0xF9, '7'), 'LMC': (Inherent, 0xFA, '7'), 'LMD': (Inherent, 0xFB, '7'), 'LME': (Inherent, 0xFC, '7'), 'LMH': (Inherent, 0xFD, '7'), 'LML': (Inherent, 0xFE, '7'), 'INB': (Inherent, 0x08, '5'), 'INC': (Inherent, 0x10, '5'), 'IND': (Inherent, 0x18, '5'), 'INE': (Inherent, 0x20, '5'), 'INH': (Inherent, 0x28, '5'), 'INL': (Inherent, 0x30, '5'), 'DCB': (Inherent, 0x09, '5'), 'DCC': (Inherent, 0x11, '5'), 'DCD': (Inherent, 0x19, '5'), 'DCE': (Inherent, 0x21, '5'), 'DCH': (Inherent, 0x29, '5'), 'DCL': (Inherent, 0x31, '5'), 'ADA': (Inherent, 0x80, '5'), 'ADB': (Inherent, 0x81, '5'), # 'ADC' : (Inherent, 0x82, '5'), Conflicting syntax parsed separately # 'ADD' : (Inherent, 0x83, '5'), Conflicting syntax parsed separately 'ADE': (Inherent, 0x84, '5'), 'ADH': (Inherent, 0x85, '5'), 'ADL': (Inherent, 0x86, '5'), 'ADM': (Inherent, 0x87, '8'), 'ACA': (Inherent, 0x88, '5'), 'ACB': (Inherent, 0x89, '5'), 'ACC': (Inherent, 0x8A, '5'), 'ACD': (Inherent, 0x8B, '5'), 'ACE': (Inherent, 0x8C, '5'), 'ACH': (Inherent, 0x8D, '5'), 'ACL': (Inherent, 0x8E, '5'), 'ACM': (Inherent, 0x8F, '8'), 'SUA': (Inherent, 0x90, '5'), # 'SUB' : (Inherent, 0x91, '5'), Conflicting syntax parsed separately 'SUC': (Inherent, 0x92, '5'), 'SUD': (Inherent, 0x93, '5'), 'SUE': (Inherent, 0x94, '5'), 'SUH': (Inherent, 0x95, '5'), 'SUL': (Inherent, 0x96, '5'), 'SUM': (Inherent, 0x97, '8'), 'SBA': (Inherent, 0x98, '5'), # 'SBB' : (Inherent,0x99,'5'), Conflicting syntax parsed separately 'SBC': (Inherent, 0x9A, '5'), 'SBD': (Inherent, 0x9B, '5'), 'SBE': (Inherent, 0x9C, '5'), 'SBH': (Inherent, 0x9D, '5'), 'SBL': (Inherent, 0x9E, '5'), 'SBM': (Inherent, 0x9F, '8'), 'NDA': (Inherent, 0xA0, '5'), 'NDB': (Inherent, 0xA1, '5'), 'NDC': (Inherent, 0xA2, '5'), 'NDD': (Inherent, 0xA3, '5'), 'NDE': (Inherent, 0xA4, '5'), 'NDH': (Inherent, 0xA5, '5'), 'NDL': (Inherent, 0xA6, '5'), 'NDM': (Inherent, 0xA7, '8'), # 'XRA' : (Inherent, 0xA8, '5'), Conflicting syntax parsed separately 'XRB': (Inherent, 0xA9, '5'), 'XRC': (Inherent, 0xAA, '5'), 'XRD': (Inherent, 0xAB, '5'), 'XRE': (Inherent, 0xAC, '5'), 'XRH': (Inherent, 0xAD, '5'), 'XRL': (Inherent, 0xAE, '5'), 'XRM': (Inherent, 0xAF, '8'), # 'ORA' : (Inherent, 0xB0, '5'), Conflicting syntax parsed separately 'ORB': (Inherent, 0xB1, '5'), 'ORC': (Inherent, 0xB2, '5'), 'ORD': (Inherent, 0xB3, '5'), 'ORE': (Inherent, 0xB4, '5'), 'ORH': (Inherent, 0xB5, '5'), 'ORL': (Inherent, 0xB6, '5'), 'ORM': (Inherent, 0xB7, '8'), 'CPA': (Inherent, 0xB8, '5'), 'CPB': (Inherent, 0xB9, '5'), 'CPC': (Inherent, 0xBA, '5'), 'CPD': (Inherent, 0xBB, '5'), # 'CPE' : (Inherent, 0xBC, '5'), Conflicting syntax parsed separately 'CPH': (Inherent, 0xBD, '5'), 'CPL': (Inherent, 0xBE, '5'), 'CPM': (Inherent, 0xBF, '8'), 'RLC': (Inherent, 0x02, '5'), 'RRC': (Inherent, 0x0A, '5'), 'RAL': (Inherent, 0x12, '5'), 'RAR': (Inherent, 0x1A, '5'), 'HLT': (Inherent, 0x00, '4'), 'RET': (Inherent, 0x07, '5'), 'RFC': (Inherent, 0x03, '3/5'), 'RNC': (Inherent, 0x03, '3/5'), 'RFZ': (Inherent, 0x0B, '3/5'), 'RNZ': (Inherent, 0x0B, '3/5'), 'RFS': (Inherent, 0x13, '3/5'), 'RP': (Inherent, 0x13, '3/5'), 'RFP': (Inherent, 0x1B, '3/5'), 'RPO': (Inherent, 0x1B, '3/5'), 'RTC': (Inherent, 0x23, '3/5'), 'RC': (Inherent, 0x23, '3/5'), 'RTZ': (Inherent, 0x2B, '3/5'), 'RZ': (Inherent, 0x2B, '3/5'), 'RTS': (Inherent, 0x33, '3/5'), 'RM': (Inherent, 0x33, '3/5'), 'RTP': (Inherent, 0x3B, '3/5'), 'RPE': (Inherent, 0x3B, '3/5'), 'LAI': (Immediate, 0x06, '8'), 'LBI': (Immediate, 0x0E, '8'), 'LCI': (Immediate, 0x16, '8'), 'LDI': (Immediate, 0x1E, '8'), 'LEI': (Immediate, 0x26, '8'), 'LHI': (Immediate, 0x2E, '8'), 'LLI': (Immediate, 0x36, '8'), 'LMI': (Immediate, 0x3E, '9'), 'ADI': (Immediate, 0x04, '8'), 'ACI': (Immediate, 0x0C, '8'), 'SUI': (Immediate, 0x14, '8'), 'SBI': (Immediate, 0x1C, '8'), 'NDI': (Immediate, 0x24, '8'), 'ANI': (Immediate, 0x24, '8'), 'XRI': (Immediate, 0x2C, '8'), 'ORI': (Immediate, 0x34, '8'), 'CPI': (Immediate, 0x3C, '8'), 'IN': (InOut, 0x41, '8'), 'INP': (InOut, 0x41, '8'), 'OUT': (InOut, 0x41, '6'), 'RST': (Restart, 0x05, '5') } dec.Asm.Memory = 0 dec.Asm.Timing_Length = 4 if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = (1 << 14) - 1 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = False return
def CrossInit(): """ Initialize this cross overlay. """ global Asm, Flags assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { 'ASLA' : (Implied, 0x48, '1'), 'ASLX' : (Implied, 0x58, '1'), 'ASRA' : (Implied, 0x47, '1'), 'ASRX' : (Implied, 0x57, '1'), 'CLC' : (Implied, 0x98, '1'), 'CLI' : (Implied, 0x9A, '2'), 'CLRA' : (Implied, 0x4F, '1'), 'CLRX' : (Implied, 0x5F, '1'), 'CLRH' : (Implied, 0x8C, '1'), 'COMA' : (Implied, 0x43, '1'), 'COMX' : (Implied, 0x53, '1'), 'DAA' : (Implied, 0x72, '2'), 'DECA' : (Implied, 0x4A, '1'), 'DECX' : (Implied, 0x5A, '1'), 'DEX' : (Implied, 0x5A, '1'), 'DIV' : (Implied, 0x52, '7'), 'INCA' : (Implied, 0x4C, '1'), 'INCX' : (Implied, 0x5C, '1'), 'INX' : (Implied, 0x5C, '1'), 'LSLA' : (Implied, 0x48, '1'), 'LSLX' : (Implied, 0x58, '1'), 'LSRA' : (Implied, 0x44, '1'), 'LSRX' : (Implied, 0x54, '1'), 'MUL' : (Implied, 0x42, '5'), 'NEGA' : (Implied, 0x40, '1'), 'NEGX' : (Implied, 0x50, '1'), 'NOP' : (Implied, 0x9D, '1'), 'NSA' : (Implied, 0x62, '3'), 'PSHA' : (Implied, 0x87, '2'), 'PSHH' : (Implied, 0x8B, '2'), 'PSHX' : (Implied, 0x89, '2'), 'PULA' : (Implied, 0x86, '2'), 'PULH' : (Implied, 0x8A, '2'), 'PULX' : (Implied, 0x88, '2'), 'ROLA' : (Implied, 0x49, '1'), 'ROLX' : (Implied, 0x59, '1'), 'RORA' : (Implied, 0x46, '1'), 'RORX' : (Implied, 0x56, '1'), 'RSP' : (Implied, 0x9C, '1'), 'RTI' : (Implied, 0x80, '7'), 'RTS' : (Implied, 0x81, '4'), 'SEC' : (Implied, 0x99, '1'), 'SEI' : (Implied, 0x9B, '2'), 'STOP' : (Implied, 0x8E, '1'), 'SWI' : (Implied, 0x83, '9'), 'TAP' : (Implied, 0x84, '2'), 'TAX' : (Implied, 0x97, '1'), 'TPA' : (Implied, 0x85, '1'), 'TSTA' : (Implied, 0x4D, '1'), 'TSTX' : (Implied, 0x5D, '1'), 'TSX' : (Implied, 0x95, '2'), 'TXA' : (Implied, 0x9F, '1'), 'TXS' : (Implied, 0x94, '2'), 'WAIT' : (Implied, 0x8F, '1'), 'BCC' : (Branch, 0x24, '3'), 'BCS' : (Branch, 0x25, '3'), 'BEQ' : (Branch, 0x27, '3'), 'BGE' : (Branch, 0x90, '3'), 'BGT' : (Branch, 0x92, '3'), 'BHCC' : (Branch, 0x28, '3'), 'BHCS' : (Branch, 0x29, '3'), 'BHI' : (Branch, 0x22, '3'), 'BHS' : (Branch, 0x24, '3'), 'BIH' : (Branch, 0x2F, '3'), 'BIL' : (Branch, 0x2E, '3'), 'BLE' : (Branch, 0x93, '3'), 'BLO' : (Branch, 0x25, '3'), 'BLS' : (Branch, 0x23, '3'), 'BLT' : (Branch, 0x91, '3'), 'BMC' : (Branch, 0x2C, '3'), 'BMI' : (Branch, 0x2B, '3'), 'BMS' : (Branch, 0x2D, '3'), 'BNE' : (Branch, 0x26, '3'), 'BPL' : (Branch, 0x2A, '3'), 'BRA' : (Branch, 0x20, '3'), 'BRN' : (Branch, 0x21, '3'), 'BSR' : (Branch, 0xAD, '6'), 'DBNZA': (Branch, 0x4B, '3'), 'DBNZX': (Branch, 0x5B, '3'), 'ADC' : (Multi, (0xA9, 0xB9, 0xC9, 0xF9, 0xE9, 0xD9, 0x9EE9, 0x9ED9), ('2', '3', '4', '2', '3', '4', '4', '5'), False), 'ADD' : (Multi, (0xAB, 0xBB, 0xCB, 0xFB, 0xEB, 0xDB, 0x9EEB, 0x9EDB), ('2', '3', '4', '2', '3', '4', '4', '5'), False), 'AND' : (Multi, (0xA4, 0xB4, 0xC4, 0xF4, 0xE4, 0xD4, 0x9EE4, 0x9ED4), ('2', '3', '4', '2', '3', '4', '4', '5'), False), 'AIS' : (Multi, (0xA7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), ('2', '', '', '', '', '', '', ''), False), 'AIX' : (Multi, (0xAF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), ('2', '', '', '', '', '', '', ''), False), 'ASL' : (Multi, (0x00, 0x38, 0x00, 0x78, 0x68, 0x00, 0x9E68, 0x00), ('', '4', '', '3', '4', '', '5', ''), False), 'ASR' : (Multi, (0x00, 0x37, 0x00, 0x77, 0x67, 0x00, 0x9E67, 0x00), ('', '4', '', '3', '4', '', '5', ''), False), 'BIT' : (Multi, (0xA5, 0xB5, 0xC5, 0xF5, 0xE5, 0xD5, 0x9EE5, 0x9ED5), ('2', '3', '4', '2', '3', '4', '4', '5'), False), 'CLR' : (Multi, (0x00, 0x3F, 0x00, 0x7F, 0x6F, 0x00, 0x9E6F, 0x00), ('', '3', '', '2', '3', '', '4', ''), False), 'CMP' : (Multi, (0xA1, 0xB1, 0xC1, 0xF1, 0xE1, 0xD1, 0x9EE1, 0x9ED1), ('2', '3', '4', '2', '3', '4', '4', '5'), False), 'COM' : (Multi, (0x00, 0x33, 0x00, 0x73, 0x63, 0x00, 0x9E63, 0x00), ('', '4', '', '3', '4', '', '5', ''), False), 'CPHX' : (Multi, (0x65, 0x75, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), ('3', '4', '', '', '', '', '', ''), True), 'CPX' : (Multi, (0xA3, 0xB3, 0xC3, 0xF3, 0xE3, 0xD3, 0x9EE3, 0x9ED3), ('2', '3', '4', '2', '3', '4', '4', '5'), False), 'DEC' : (Multi, (0x00, 0x3A, 0x00, 0x7A, 0x6A, 0x00, 0x9E6A, 0x00), ('', '4', '', '3', '4', '', '5', ''), False), 'EOR' : (Multi, (0xA8, 0xB8, 0xC8, 0xF8, 0xE8, 0xD8, 0x9EE8, 0x9ED8), ('2', '3', '4', '2', '3', '4', '4', '5'), False), 'INC' : (Multi, (0x00, 0x3C, 0x00, 0x7C, 0x6C, 0x00, 0x9E6C, 0x00), ('', '4', '', '3', '4', '', '5', ''), False), 'JMP' : (Multi, (0x00, 0xBC, 0xCC, 0xFC, 0xEC, 0xDC, 0x00, 0x00), ('', '2', '3', '2', '3', '4', '', ''), False), 'JSR' : (Multi, (0x00, 0xBD, 0xCD, 0xFD, 0xED, 0xDD, 0x00, 0x00), ('', '4', '5', '4', '5', '6', '', ''), False), 'LDA' : (Multi, (0xA6, 0xB6, 0xC6, 0xF6, 0xE6, 0xD6, 0x9EE6, 0x9ED6), ('2', '3', '4', '2', '3', '4', '4', '5'), False), 'LDHX' : (Multi, (0x45, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), ('3', '4', '', '', '', '', '', ''), True), 'LDX' : (Multi, (0xAE, 0xBE, 0xCE, 0xFE, 0xEE, 0xDE, 0x9EEE, 0x9EDE), ('2', '3', '4', '2', '3', '4', '4', '5'), False), 'LSL' : (Multi, (0x00, 0x38, 0x00, 0x78, 0x68, 0x00, 0x9E68, 0x00), ('', '4', '', '3', '4', '', '5', ''), False), 'LSR' : (Multi, (0x00, 0x34, 0x00, 0x74, 0x64, 0x00, 0x9E64, 0x00), ('', '4', '', '3', '4', '', '5', ''), False), 'NEG' : (Multi, (0x00, 0x30, 0x00, 0x70, 0x60, 0x00, 0x9E60, 0x00), ('', '4', '', '3', '4', '', '5', ''), False), 'ORA' : (Multi, (0xAA, 0xBA, 0xCA, 0xFA, 0xEA, 0xDA, 0x9EEA, 0x9EDA), ('2', '3', '4', '2', '3', '4', '4', '5'), False), 'ROL' : (Multi, (0x00, 0x39, 0x00, 0x79, 0x69, 0x00, 0x9E69, 0x00), ('', '4', '', '3', '4', '', '5', ''), False), 'ROR' : (Multi, (0x00, 0x36, 0x00, 0x76, 0x66, 0x00, 0x9E66, 0x00), ('', '4', '', '3', '4', '', '5', ''), False), 'SBC' : (Multi, (0xA2, 0xB2, 0xC2, 0xF2, 0xE2, 0xD2, 0x9EE2, 0x9ED2), ('2', '3', '4', '2', '3', '4', '4', '5'), False), 'STA' : (Multi, (0x00, 0xB7, 0xC7, 0xF7, 0xE7, 0xD7, 0x9EE7, 0x9ED7), ('', '3', '4', '2', '3', '4', '4', '5'), False), 'STHX' : (Multi, (0x00, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), ('', '4', '', '', '', '', '', ''), False), 'STX' : (Multi, (0x00, 0xBF, 0xCF, 0xFF, 0xEF, 0xDF, 0x9EEF, 0x9EDF), ('', '3', '4', '2', '3', '4', '4', '5'), False), 'SUB' : (Multi, (0xA0, 0xB0, 0xC0, 0xF0, 0xE0, 0xD0, 0x9EE0, 0x9ED0), ('2', '3', '4', '2', '3', '4', '4', '5'), False), 'TST' : (Multi, (0x00, 0x3D, 0x00, 0x7D, 0x6D, 0x00, 0x9E6D, 0x00), ('', '3', '', '2', '3', '', '4', ''), False), 'BCLR' : (Bits, 0x11, '4'), 'BSET' : (Bits, 0x10, '4'), 'BRCLR': (Bits, 0x01, '5'), 'BRSET': (Bits, 0x00, '5'), 'MOV' : (Move, (0x6E, 0x4E, 0x7E, 0x5E), ('4', '5', '4', '4')), 'CBEQ' : (CompBranch, (0x31, 0x71, 0x61, 0x9E61), ('5', '4', '5', '6')), 'CBEQA': (CompBranch, 0x41, '4'), 'CBEQX': (CompBranch, 0x51, '4'), 'DBNZ' : (CompBranch, (0x3B, 0x7B, 0x6B, 0x9E6B), ('5', '4', '5', '6')) } dec.Asm.Timing_Length = 1 dec.Asm.Memory = 0 if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = dec.MAX16 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = True return
def CrossInit(): global Asm, Flags assem.CheckVersions(crossversion, minversion) # The instructions directory contains a tuple with: # function which handles this opcode, # integer value of opcode # string with cycle time(s) of this instruction on an 8085 # string with cycle time(s) of this instruction on an 8080 dec.Asm.Instructions = { 'CALL': (Absolute, 0xCD, '18', '17'), 'CC': (Absolute, 0xDC, '9/18', '11/17'), 'CM': (Absolute, 0xFC, '9/18', '11/17'), 'CNC': (Absolute, 0xD4, '9/18', '11/17'), 'CNZ': (Absolute, 0xC4, '9/18', '11/17'), 'CP': (Absolute, 0xF4, '9/18', '11/17'), 'CPE': (Absolute, 0xEC, '9/18', '11/17'), 'CPO': (Absolute, 0xE4, '9/18', '11/17'), 'CZ': (Absolute, 0xCC, '9/18', '11/17'), 'JC': (Absolute, 0xDA, '7/10', '10'), 'JM': (Absolute, 0xFA, '7/10', '10'), 'JMP': (Absolute, 0xC3, '7', '10'), 'JNC': (Absolute, 0xD2, '7/10', '10'), 'JNZ': (Absolute, 0xC2, '7/10', '10'), 'JP': (Absolute, 0xF2, '7/10', '10'), 'JPE': (Absolute, 0xEA, '7/10', '10'), 'JPO': (Absolute, 0xE2, '7/10', '10'), 'JZ': (Absolute, 0xCA, '7/10', '10'), 'LDA': (Absolute, 0x3A, '13', '13'), 'LHLD': (Absolute, 0x2A, '16', '16'), 'SHLD': (Absolute, 0x22, '16', '16'), 'STA': (Absolute, 0x32, '13', '13'), 'CMA': (Inherent, 0x2F, '4', '4'), 'CMC': (Inherent, 0x3F, '4', '4'), 'DAA': (Inherent, 0x27, '4', '4'), 'DI': (Inherent, 0xF3, '4', '4'), 'EI': (Inherent, 0xFB, '4', '4'), 'HLT': (Inherent, 0x76, '5', '7'), 'NOP': (Inherent, 0x00, '4', '4'), 'PCHL': (Inherent, 0xE9, '6', '5'), 'RAL': (Inherent, 0x17, '4', '4'), 'RAR': (Inherent, 0x1F, '4', '4'), 'RC': (Inherent, 0xD8, '6/12', '5/11'), 'RET': (Inherent, 0xC9, '10', '10'), 'RIM': (Inherent, 0x20, '4', ''), 'RLC': (Inherent, 0x07, '4', '4'), 'RM': (Inherent, 0xF8, '6/12', '5/11'), 'RNC': (Inherent, 0xD0, '6/12', '5/11'), 'RNZ': (Inherent, 0xC0, '6/12', '5/11'), 'RP': (Inherent, 0xF0, '6/12', '5/11'), 'RPE': (Inherent, 0xE8, '6/12', '5/11'), 'RPO': (Inherent, 0xE0, '6/12', '5/11'), 'RRC': (Inherent, 0x0F, '4', '4'), 'RZ': (Inherent, 0xC8, '6/12', '5/11'), 'SIM': (Inherent, 0x30, '4', ''), 'SPHL': (Inherent, 0xF9, '6', '5'), 'STC': (Inherent, 0x37, '4', '4'), 'XCHG': (Inherent, 0xEB, '4', '4'), 'XTHL': (Inherent, 0xE3, '16', '18'), 'MOV': (MovInst, 0x40, '4:7', '5:7'), 'ADC': (Math, 0x88, '4:7', '4:7'), 'ADD': (Math, 0x80, '4:7', '4:7'), 'ANA': (Math, 0xA0, '4:7', '4:7'), 'CMP': (Math, 0xB8, '4:7', '4:7'), 'DCR': (Math, 0x05, '4:10', '5:10'), 'INR': (Math, 0x04, '4:10', '5:10'), 'ORA': (Math, 0xB0, '4:7', '4:7'), 'SBB': (Math, 0x98, '4:7', '4:7'), 'SUB': (Math, 0x90, '4:7', '4:7'), 'XRA': (Math, 0xA8, '4:7', '4:7'), 'ACI': (Immediate, 0xCE, '7', '7'), 'ADI': (Immediate, 0xC6, '7', '7'), 'ANI': (Immediate, 0xE6, '7', '7'), 'CPI': (Immediate, 0xFE, '7', '7'), 'LXI': (Immediate, 0x01, '10', '10'), 'MVI': (Immediate, 0x06, '7:10', '7:10'), 'ORI': (Immediate, 0xF6, '7', '7'), 'SBI': (Immediate, 0xDE, '7', '7'), 'SUI': (Immediate, 0xD6, '7', '7'), 'XRI': (Immediate, 0xEE, '7', '7'), 'IN': (InOut, 0xDB, '10', '10'), 'OUT': (InOut, 0xD3, '10', '10'), 'DAD': (RegPair, 0x09, '10', '10'), 'DCX': (RegPair, 0x0B, '6', '5'), 'INX': (RegPair, 0x03, '6', '5'), 'POP': (RegPair, 0xC1, '10', '10'), 'PUSH': (RegPair, 0xC5, '12', '11'), 'LDAX': (LdaxStax, 0x0A, '7', '7'), 'STAX': (LdaxStax, 0x02, '7', '7'), 'RST': (Restart, 0xC7, '12', '11') } dec.Asm.Memory = 0 length = 0 if dec.Cross.Name == 'cr8085': for i in dec.Asm.Instructions: if len(dec.Asm.Instructions[i][2]) > length: length = len(dec.Asm.Instructions[i][2]) else: for i in dec.Asm.Instructions: if len(dec.Asm.Instructions[i][3]) > length: length = len(dec.Asm.Instructions[i][3]) dec.Asm.Timing_Length = length if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = dec.MAX16 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = False return
def CrossInit(): global Asm, Flags assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { 'NOP': (Inherent, 0x04, '2'), 'RET': (Inherent, 0xCD, '2'), 'RETI': (Inherent, 0x4D, '2'), 'STOP': (Inherent, 0x6D, '2'), 'WAIT': (Inherent, 0xED, '2'), # DATA A X Y V W (X) (Y) 'CLR': (Single, ('0DXX00', 'DFFF', '0D8000', '0D8100', '0D8200', '0D8300', '', ''), ('4', '4', '4', '4', '4', '4', '4', '4')), 'COM': (Single, ('', '2D', '', '', '', '', '', ''), ('0', '4', '0', '0', '0', '0', '0', '0')), 'DEC': (Single, ('FFXX', 'FFFF', '1D', '5D', '9D', 'DD', 'E7', 'EF'), ('4', '4', '4', '4', '4', '4', '4', '4')), 'DEC': (Single, ('FFXX', 'FFFF', '1D', '5D', '9D', 'DD', 'E7', 'EF'), ('4', '4', '4', '4', '4', '4', '4', '4')), 'INC': (Single, ('7FXX', '7FFF', '15', '55', '95', 'D5', '67', '6F'), ('4', '4', '4', '4', '4', '4', '4', '4')), 'RLC': (Single, ('', 'AD', '', '', '', '', '', ''), ('0', '4', '0', '0', '0', '0', '0', '0')), 'SLA': (Single, ('', '5FFF', '', '', '', '', '', ''), ('0', '4', '0', '0', '0', '0', '0', '0')), 'ADD': (Math, ('5FXX', '5FFF', '5F80', '5F81', '5F82', '5F83', '47', '4F'), ('4', '4', '4', '4', '4', '4', '4', '4')), 'AND': (Math, ('BFXX', 'BFFF', 'BF80', 'BF81', 'BF82', 'BF83', 'A7', 'AF'), ('4', '4', '4', '4', '4', '4', '4', '4')), 'CP': (Math, ('3FXX', '3FFF', '3F80', '3F81', '3F82', '3F83', '27', '2F'), ('4', '4', '4', '4', '4', '4', '4', '4')), 'SUB': (Math, ('DFXX', 'DFFF', 'DF80', 'DF81', 'DF82', 'DF83', 'C7', 'CF'), ('4', '4', '4', '4', '4', '4', '4', '4')), # DATA, A, X, Y, V, W 'ADDI': (Immediate, ('', '57', '', '', '', ''), ('0', '4', '0', '0', '0', '0')), 'ANDI': (Immediate, ('', 'B7', '', '', '', ''), ('0', '4', '0', '0', '0', '0')), 'CPI': (Immediate, ('', '37', '', '', '', ''), ('0', '4', '0', '0', '0', '0')), 'LDI': (Immediate, ('0DXX', '17', '0D80', '0D81', '0D82', '0D83'), ('4', '4', '4', '4', '4', '4')), 'SUBI': (Immediate, ('', 'D7', '', '', '', ''), ('0', '4', '0', '0', '0', '0')), # DATA, A, X, Y, V, W, (X), (Y) # First tupple A,reg # Second tupple reg,A 'LD': (LDInst, ('1FXX', '1FFF', '35', '75', 'B5', 'F5', '07', '0F'), ('9FXX', '9FFF', '3D', '7D', 'BD', 'FD', '87', '8F')), 'JRC': (Branch, 0x06, '2'), 'JRNC': (Branch, 0x02, '2'), 'JRNZ': (Branch, 0x00, '2'), 'JRZ': (Branch, 0x04, '2'), 'JRR': (BitTest, 0x03, '5'), 'JRS': (BitTest, 0x13, '5'), 'CALL': (Extended, 0x01, '4'), 'JP': (Extended, 0x09, '4'), 'RES': (BitInst, 0x0B, '4'), 'SET': (BitInst, 0x1B, '4') } dec.Asm.Timing_Length = 1 dec.Asm.Memory = 0 # Select code memory as default if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = (1 << 12) - 1 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = True return
def CrossInit(): global Asm, Flags, Error_List assem.CheckVersions(crossversion, minversion) dec.Asm.Instructions = { # Instructions which don't require an operand and are 1 byte long 'INX': (Implied, 0x60, '2'), 'LDX': (Implied, 0xF0, '2'), 'LDXA': (Implied, 0x72, '2'), 'STXD': (Implied, 0x73, '2'), 'OR': (Implied, 0xF1, '2'), 'XOR': (Implied, 0xF3, '2'), 'AND': (Implied, 0xF2, '2'), 'SHR': (Implied, 0xF6, '2'), 'SHRC': (Implied, 0x76, '2'), 'RSHR': (Implied, 0x76, '2'), 'SHL': (Implied, 0xFE, '2'), 'SHLC': (Implied, 0x7E, '2'), 'RSHL': (Implied, 0x7E, '2'), 'ADD': (Implied, 0xF4, '2'), 'ADC': (Implied, 0x74, '2'), 'SD': (Implied, 0xF5, '2'), 'SDB': (Implied, 0x75, '2'), 'SM': (Implied, 0xF7, '2'), 'SMB': (Implied, 0x77, '2'), 'IDL': (Implied, 0x00, '*'), 'NOP': (Implied, 0xC4, '2'), 'SEQ': (Implied, 0x7B, '2'), 'REQ': (Implied, 0x7A, '2'), 'SAV': (Implied, 0x78, '2'), 'MARK': (Implied, 0x79, '2'), 'RET': (Implied, 0x70, '2'), 'DIS': (Implied, 0x71, '2'), # Skip instructions (may be the same as branch instructions # but this time no operand is required. Used during debugging # or clever weaving of code. Skips over the next one or two # bytes, which are most likely instructions instead of a # destination address.) 'SKP': (Implied, 0x38, '2'), 'LSKP': (Implied, 0xC8, '3'), 'LSZ': (Implied, 0xCE, '3'), 'LSNZ': (Implied, 0xC6, '3'), 'LSDF': (Implied, 0xCF, '3'), 'LSNF': (Implied, 0xC7, '3'), 'LSQ': (Implied, 0xCD, '3'), 'LSNQ': (Implied, 0xC5, '3'), 'LSIE': (Implied, 0xCC, '3'), # Unique instructions to the 1804 'ETQ': (Implied, 0x6809, '3'), 'LDC': (Implied, 0x6806, '3'), 'GEC': (Implied, 0x6808, '3'), 'STPC': (Implied, 0x6800, '3'), 'DTC': (Implied, 0x6801, '3'), 'STM': (Implied, 0x6807, '3'), 'SCM1': (Implied, 0x6805, '3'), 'SCM2': (Implied, 0x6803, '3'), 'SPM1': (Implied, 0x6804, '3'), 'SPM2': (Implied, 0x6802, '3'), 'XIE': (Implied, 0x680A, '3'), 'XID': (Implied, 0x680B, '3'), 'CIE': (Implied, 0x680C, '3'), 'CID': (Implied, 0x680D, '3'), # Unique instructions tho the 1805 'DADD': (Implied, 0x68F4, '4'), 'DADC': (Implied, 0x6874, '4'), 'DSM': (Implied, 0x68F7, '4'), 'DSMB': (Implied, 0x6877, '4'), 'DSAV': (Implied, 0x6876, '6'), # Instructions which require a register 'INC': (RegArg, 0x10, '2'), 'DEC': (RegArg, 0x20, '2'), 'GLO': (RegArg, 0x80, '2'), 'PLO': (RegArg, 0xA0, '2'), 'GHI': (RegArg, 0x90, '2'), 'PHI': (RegArg, 0xB0, '2'), 'LDN': (RegArg, 0x00, '2'), 'LDA': (RegArg, 0x40, '2'), 'STR': (RegArg, 0x50, '2'), 'SEP': (RegArg, 0xD0, '2'), 'SEX': (RegArg, 0xE0, '2'), 'OUT': (RegArg, 0x60, '2'), # Second nibble is a dummy 'INP': (RegArg, 0x68, '2'), # Second nibble is a dummy # Unique instructions to the 1804 'RLXA': (RegArg, 0x6860, '5'), 'RSXD': (RegArg, 0x68A0, '5'), 'RNX': (RegArg, 0x68B0, '4'), 'SCAL': (RegArg, 0x6880, '10'), 'SRET': (RegArg, 0x6890, '8'), # Unique instructions to the 1805 'DBNZ': (RegArg, 0x6820, '5'), # Immediate addressing 'LDI': (Immediate, 0xF8, '2'), 'ORI': (Immediate, 0xF9, '2'), 'XRI': (Immediate, 0xFB, '2'), 'ANI': (Immediate, 0xFA, '2'), 'ADI': (Immediate, 0xFC, '2'), 'ADCI': (Immediate, 0x7C, '2'), 'SDI': (Immediate, 0xFD, '2'), 'SDBI': (Immediate, 0x7D, '2'), 'SMI': (Immediate, 0xFF, '2'), 'SMBI': (Immediate, 0x7F, '2'), # Unique instructions to the 1804 'RLDI': (Immediate2, 0x68C0, '5'), # Unique instructions to the 1805 'DADI': (Immediate, 0x68FC, '4'), 'DACI': (Immediate, 0x687C, '4'), 'DSMI': (Immediate, 0x68FF, '4'), 'DSBI': (Immediate, 0x687F, '4'), # Branching 'BR': (Branch, 0x30, '2'), 'NBR': (Branch, 0x38, '2'), 'BZ': (Branch, 0x32, '2'), 'BNZ': (Branch, 0x3A, '2'), 'BDF': (Branch, 0x33, '2'), 'BPZ': (Branch, 0x33, '2'), 'BGE': (Branch, 0x33, '2'), 'BNF': (Branch, 0x3B, '2'), 'BM': (Branch, 0x3B, '2'), 'BL': (Branch, 0x3B, '2'), 'BQ': (Branch, 0x31, '2'), 'BNQ': (Branch, 0x39, '2'), 'B1': (Branch, 0x34, '2'), 'BN1': (Branch, 0x3C, '2'), 'B2': (Branch, 0x35, '2'), 'BN2': (Branch, 0x3D, '2'), 'B3': (Branch, 0x36, '2'), 'BN3': (Branch, 0x3E, '2'), 'B4': (Branch, 0x37, '2'), 'BN4': (Branch, 0x3F, '2'), # Unique instructions to the 1804 'BCI': (Branch, 0x683E, '3'), 'BXI': (Branch, 0x683F, '3'), # Long Branches 'LBR': (LongBranch, 0xC0, '3'), 'NLBR': (LongBranch, 0xC8, '3'), 'LBZ': (LongBranch, 0xC2, '3'), 'LBNZ': (LongBranch, 0xCA, '3'), 'LBDF': (LongBranch, 0xC3, '3'), 'LBNF': (LongBranch, 0xCB, '3'), 'LBQ': (LongBranch, 0xC1, '3'), 'LBNQ': (LongBranch, 0xC9, '3') } dec.Asm.Timing_Length = 4 # Longest timing string dec.Asm.Memory = 0 # Select code memory as default if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = dec.MAX16 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = True # Because of long branch byte order return
def CrossInit(): """ Initialize this cross overlay. """ global Asm, Flags assem.CheckVersions(crossversion, minversion) # Tupple: Handling routine, opcode, 6800 timing, 6801 timing dec.Asm.Instructions = { 'ABA' : (Implied, 0x1B, '2', '2', '1'), 'ABX' : (Implied, 0x3A, '0', '3', '1'), 'ASLA': (Implied, 0x48, '2', '2', '1'), 'ASLB': (Implied, 0x58, '2', '2', '1'), 'ASLD': (Implied, 0x05, '0', '3', '1'), 'ASRA': (Implied, 0x47, '2', '2', '1'), 'ASRB': (Implied, 0x57, '2', '2', '1'), 'CBA' : (Implied, 0x11, '2', '2', '1'), 'CLC' : (Implied, 0x0C, '2', '2', '1'), 'CLI' : (Implied, 0x0E, '2', '2', '1'), 'CLRA': (Implied, 0x4F, '2', '2', '1'), 'CLRB': (Implied, 0x5F, '2', '2', '1'), 'CLV' : (Implied, 0x0A, '2', '2', '1'), 'COMA': (Implied, 0x43, '2', '2', '1'), 'COMB': (Implied, 0x53, '2', '2', '1'), 'DAA' : (Implied, 0x19, '2', '2', '2'), 'DECA': (Implied, 0x4A, '2', '2', '1'), 'DECB': (Implied, 0x5A, '2', '2', '1'), 'DES' : (Implied, 0x34, '4', '3', '1'), 'DEX' : (Implied, 0x09, '4', '3', '1'), 'INCA': (Implied, 0x4C, '2', '2', '1'), 'INCB': (Implied, 0x5C, '2', '2', '1'), 'INS' : (Implied, 0x31, '4', '3', '1'), 'INX' : (Implied, 0x08, '4', '3', '1'), 'LSLA': (Implied, 0x48, '2', '2', '1'), 'LSLB': (Implied, 0x58, '2', '2', '1'), 'LSLD': (Implied, 0x05, '0', '3', '1'), 'LSRA': (Implied, 0x44, '2', '2', '1'), 'LSRB': (Implied, 0x54, '2', '2', '1'), 'LSRD': (Implied, 0x04, '0', '3', '1'), 'MUL' : (Implied, 0x3D, '0', '10', '7'), 'NEGA': (Implied, 0x40, '2', '2', '1'), 'NEGB': (Implied, 0x50, '2', '2', '1'), 'NOP' : (Implied, 0x01, '2', '2', '1'), 'PSHA': (Implied, 0x36, '4', '3', '4'), 'PSHB': (Implied, 0x37, '4', '3', '4'), 'PSHX': (Implied, 0x3C, '0', '4', '5'), 'PULA': (Implied, 0x32, '4', '4', '3'), 'PULB': (Implied, 0x33, '4', '4', '3'), 'PULX': (Implied, 0x38, '0', '5', '4'), 'ROLA': (Implied, 0x49, '2', '2', '1'), 'ROLB': (Implied, 0x59, '2', '2', '1'), 'RORA': (Implied, 0x46, '2', '2', '1'), 'RORB': (Implied, 0x56, '2', '2', '1'), 'RTI' : (Implied, 0x3B, '10', '10', '10'), 'RTS' : (Implied, 0x39, '5', '5', '5'), 'SBA' : (Implied, 0x10, '2', '2', '1'), 'SEC' : (Implied, 0x0D, '2', '2', '1'), 'SEI' : (Implied, 0x0F, '2', '2', '1'), 'SEV' : (Implied, 0x0B, '2', '2', '1'), 'SLP' : (Implied, 0x1A, '0', '0', '4'), 'SWI' : (Implied, 0x3F, '12', '12', '12'), 'TAB' : (Implied, 0x16, '2', '2', '1'), 'TAP' : (Implied, 0x06, '2', '2', '1'), 'TBA' : (Implied, 0x17, '2', '2', '1'), 'TPA' : (Implied, 0x07, '2', '2', '1'), 'TSTA': (Implied, 0x4D, '2', '2', '1'), 'TSTB': (Implied, 0x5D, '2', '2', '1'), 'TSX' : (Implied, 0x30, '4', '3', '1'), 'TXS' : (Implied, 0x35, '4', '3', '1'), 'WAI' : (Implied, 0x3E, '9', '9', '9'), 'XGDX': (Implied, 0x18, '0', '0', '2'), 'BCC' : (Branch, 0x24, '4', '3', '3'), 'BCS' : (Branch, 0x25, '4', '3', '3'), 'BEQ' : (Branch, 0x27, '4', '3', '3'), 'BGE' : (Branch, 0x2C, '4', '3', '3'), 'BGT' : (Branch, 0x2E, '4', '3', '3'), 'BHI' : (Branch, 0x22, '4', '3', '3'), 'BLE' : (Branch, 0x2F, '4', '3', '3'), 'BLS' : (Branch, 0x23, '4', '3', '3'), 'BLT' : (Branch, 0x2D, '4', '3', '3'), 'BMI' : (Branch, 0x2B, '4', '3', '3'), 'BNE' : (Branch, 0x26, '4', '3', '3'), 'BPL' : (Branch, 0x2A, '4', '3', '3'), 'BRA' : (Branch, 0x20, '4', '3', '3'), 'BRN' : (Branch, 0x21, '0', '3', '3'), 'BSR' : (Branch, 0x8D, '8', '3', '3'), 'BVC' : (Branch, 0x28, '4', '3', '3'), 'BVS' : (Branch, 0x29, '4', '3', '3'), 'BHS' : (Branch, 0x24, '4', '3', '3'), 'BLO' : (Branch, 0x25, '4', '3', '3'), 'ADCA' : (Multi, (0x89, 0x99, 0xA9, 0xB9), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'ADCB' : (Multi, (0xC9, 0xD9, 0xE9, 0xF9), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'ADDA' : (Multi, (0x8B, 0x9B, 0xAB, 0xBB), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'ADDB' : (Multi, (0xCB, 0xDB, 0xEB, 0xFB), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'ADDD' : (Multi, (0xC3, 0xD3, 0xE3, 0xF3), ('0', '0', '0', '0'), ('4', '5', '6', '6'), ('3', '4', '5', '5')), 'ANDA' : (Multi, (0x84, 0x94, 0xA4, 0xB4), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'ANDB' : (Multi, (0xC4, 0xD4, 0xE4, 0xF4), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'ASL' : (Multi, (0x00, 0x00, 0x68, 0x78), ('0', '0', '7', '6'), ('0', '0', '6', '6'), ('0', '0', '6', '6')), 'ASR' : (Multi, (0x00, 0x00, 0x67, 0x77), ('0', '0', '7', '6'), ('0', '0', '6', '6'), ('0', '0', '6', '6')), 'BITA' : (Multi, (0x85, 0x95, 0xA5, 0xB5), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'BITB' : (Multi, (0xC5, 0xD5, 0xE5, 0xF5), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'CLR' : (Multi, (0x00, 0x00, 0x6F, 0x7F), ('0', '0', '7', '6'), ('0', '0', '6', '6'), ('0', '0', '5', '5')), 'CMPA' : (Multi, (0x81, 0x91, 0xA1, 0xB1), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'CMPB' : (Multi, (0xC1, 0xD1, 0xE1, 0xF1), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'COM' : (Multi, (0x00, 0x00, 0x63, 0x73), ('0', '0', '7', '6'), ('0', '0', '6', '6'), ('0', '0', '6', '6')), 'CPX' : (Multi, (0x8C, 0x9C, 0xAC, 0xBC), ('3', '4', '6', '5'), ('4', '5', '6', '6'), ('3', '4', '5', '5')), 'DEC' : (Multi, (0x00, 0x00, 0x6A, 0x7A), ('0', '0', '7', '6'), ('0', '0', '6', '6'), ('0', '0', '6', '6')), 'EORA' : (Multi, (0x88, 0x98, 0xA8, 0xB8), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'EORB' : (Multi, (0xC8, 0xD8, 0xE8, 0xF8), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'INC' : (Multi, (0x00, 0x00, 0x6C, 0x7C), ('0', '0', '7', '6'), ('0', '0', '6', '6'), ('0', '0', '6', '6')), 'JMP' : (Multi, (0x00, 0x00, 0x6E, 0x7E), ('0', '0', '4', '3'), ('0', '0', '3', '3'), ('0', '0', '3', '3')), 'JSR' : (Multi, (0x00, 0x9D, 0xAD, 0xBD), ('0', '0', '8', '9'), ('0', '5', '6', '6'), ('0', '5', '5', '6')), 'LDAA' : (Multi, (0x86, 0x96, 0xA6, 0xB6), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'LDAB' : (Multi, (0xC6, 0xD6, 0xE6, 0xF6), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'LDD' : (Multi, (0xCC, 0xDC, 0xEC, 0xFC), ('0', '0', '0', '0'), ('3', '4', '5', '5'), ('3', '4', '5', '5')), 'LDAD' : (Multi, (0xCC, 0xDC, 0xEC, 0xFC), ('0', '0', '0', '0'), ('3', '4', '5', '5'), ('3', '4', '5', '5')), 'LDS' : (Multi, (0x8E, 0x9E, 0xAE, 0xBE), ('3', '4', '6', '5'), ('3', '4', '5', '5'), ('3', '4', '5', '5')), 'LDX' : (Multi, (0xCE, 0xDE, 0xEE, 0xFE), ('3', '4', '6', '5'), ('3', '4', '5', '5'), ('3', '4', '5', '5')), 'LSL' : (Multi, (0x00, 0x00, 0x68, 0x78), ('0', '0', '7', '6'), ('0', '0', '6', '6'), ('0', '0', '6', '6')), 'LSR' : (Multi, (0x00, 0x00, 0x64, 0x74), ('0', '0', '7', '6'), ('0', '0', '6', '6'), ('0', '0', '6', '6')), 'NEG' : (Multi, (0x00, 0x00, 0x60, 0x70), ('0', '0', '7', '6'), ('0', '0', '6', '6'), ('0', '0', '6', '6')), 'ORAA' : (Multi, (0x8A, 0x9A, 0xAA, 0xBA), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'ORAB' : (Multi, (0xCA, 0xDA, 0xEA, 0xFA), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'ROL' : (Multi, (0x00, 0x00, 0x69, 0x79), ('0', '0', '7', '6'), ('0', '0', '6', '6'), ('0', '0', '6', '6')), 'ROR' : (Multi, (0x00, 0x00, 0x66, 0x76), ('0', '0', '7', '6'), ('0', '0', '6', '6'), ('0', '0', '6', '6')), 'SBCA' : (Multi, (0x82, 0x92, 0xA2, 0xB2), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'SBCB' : (Multi, (0xC2, 0xD2, 0xE2, 0xF2), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'STAA' : (Multi, (0x00, 0x97, 0xA7, 0xB7), ('0', '4', '6', '5'), ('0', '3', '4', '4'), ('0', '3', '4', '4')), 'STAB' : (Multi, (0x00, 0xD7, 0xE7, 0xF7), ('0', '4', '6', '5'), ('0', '3', '4', '4'), ('0', '3', '4', '4')), 'STD' : (Multi, (0x00, 0xDD, 0xED, 0xFD), ('0', '0', '0', '0'), ('0', '4', '5', '5'), ('0', '4', '5', '5')), 'STAD' : (Multi, (0x00, 0xDD, 0xED, 0xFD), ('0', '0', '0', '0'), ('0', '4', '5', '5'), ('0', '4', '5', '5')), 'STS' : (Multi, (0x00, 0x9F, 0xAF, 0xBF), ('0', '5', '7', '6'), ('0', '4', '5', '5'), ('0', '4', '5', '5')), 'STX' : (Multi, (0x00, 0xDF, 0xEF, 0xFF), ('0', '5', '7', '6'), ('0', '4', '5', '5'), ('0', '4', '5', '5')), 'SUBA' : (Multi, (0x80, 0x90, 0xA0, 0xB0), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'SUBB' : (Multi, (0xC0, 0xD0, 0xE0, 0xF0), ('2', '3', '5', '4'), ('2', '3', '4', '4'), ('2', '3', '4', '4')), 'SUBD' : (Multi, (0x83, 0x93, 0xA3, 0xB3), ('0', '0', '0', '0'), ('4', '5', '6', '6'), ('3', '4', '5', '5')), 'TST' : (Multi, (0x00, 0x00, 0x6D, 0x7D), ('0', '0', '7', '6'), ('0', '0', '6', '6'), ('0', '0', '4', '4')), 'AIM' : (H6301, (0x71, 0x61), ('6', '7')), 'EIM' : (H6301, (0x75, 0x65), ('6', '7')), 'OIM' : (H6301, (0x72, 0x62), ('6', '7')), 'TIM' : (H6301, (0x7B, 0x6B), ('4', '5')) } dec.Asm.Timing_Length = 2 dec.Asm.Memory = 0 if dec.Asm.Pass == 1: sys.stdout.write('Loaded ' + dec.Cross.Name[2:] + ' overlay version ' + crossversion + dec.EOL) dec.Asm.Max_Address = dec.MAX16 dec.Asm.PP_TA_Factor = 1 dec.Flags.BigEndian = True return