def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
monitor_axis_tdata = Signal(intbv(0)[64:])
monitor_axis_tkeep = Signal(intbv(0)[8:])
monitor_axis_tvalid = Signal(bool(0))
monitor_axis_tready = Signal(bool(0))
monitor_axis_tlast = Signal(bool(0))
monitor_axis_tuser = Signal(bool(0))
output_axis_tready = Signal(bool(0))
tag = Signal(intbv(16)[16:])
trigger = Signal(bool(0))
# Outputs
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
busy = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
monitor_sink_queue = Queue()
monitor_sink_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=monitor_axis_tdata,
tkeep=monitor_axis_tkeep,
tvalid=monitor_axis_tvalid,
tready=monitor_axis_tready,
tlast=monitor_axis_tlast,
tuser=monitor_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
monitor_sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=monitor_axis_tdata,
tkeep=monitor_axis_tkeep,
tvalid=monitor_axis_tvalid,
tready=monitor_axis_tready,
tlast=monitor_axis_tlast,
tuser=monitor_axis_tuser,
fifo=monitor_sink_queue,
pause=monitor_sink_pause,
name='monitor_sink')
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
# DUT
dut = dut_axis_stat_counter(clk,
rst,
current_test,
monitor_axis_tdata,
monitor_axis_tkeep,
monitor_axis_tvalid,
monitor_axis_tready,
monitor_axis_tlast,
monitor_axis_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
tag,
trigger,
busy)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
tag.next = 1
yield clk.posedge
print("test 1: test tick timer")
current_test.next = 1
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
for i in range(100-1):
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[1] == 100*8
yield delay(100)
yield clk.posedge
print("test 2: pause sink")
current_test.next = 2
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
for i in range(100-1):
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
while trigger or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[1] == 100*8
yield delay(100)
yield clk.posedge
print("test 3: test packet")
current_test.next = 3
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[2] == len(test_frame.data)
assert rx_frame_values[3] == 1
yield delay(100)
yield clk.posedge
print("test 4: longer packet")
current_test.next = 4
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[2] == len(test_frame.data)
assert rx_frame_values[3] == 1
yield delay(100)
yield clk.posedge
print("test 5: test packet with pauses")
current_test.next = 5
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield delay(64)
yield clk.posedge
monitor_sink_pause.next = True
yield delay(32)
yield clk.posedge
monitor_sink_pause.next = False
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[2] == len(test_frame.data)
assert rx_frame_values[3] == 1
yield delay(100)
yield clk.posedge
print("test 6: back-to-back packets")
current_test.next = 6
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[2] == len(test_frame1.data) + len(test_frame2.data)
assert rx_frame_values[3] == 2
yield delay(100)
yield clk.posedge
print("test 7: alternate pause source")
current_test.next = 7
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[2] == len(test_frame1.data) + len(test_frame2.data)
assert rx_frame_values[3] == 2
yield delay(100)
yield clk.posedge
print("test 8: alternate pause sink")
current_test.next = 8
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[2] == len(test_frame1.data) + len(test_frame2.data)
assert rx_frame_values[3] == 2
yield delay(100)
yield clk.posedge
print("test 9: various length packets")
current_test.next = 9
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
lens = [32, 48, 96, 128, 256]
test_frame = []
for i in range(len(lens)):
test_frame.append(axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(lens[i]))))
for f in test_frame:
source_queue.put(f)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
print(rx_frame_values)
assert rx_frame_values[0] == 1
assert rx_frame_values[1] == cycles*8
assert rx_frame_values[2] == sum(len(f.data) for f in test_frame)
assert rx_frame_values[3] == len(test_frame)
yield delay(100)
yield clk.posedge
print("test 10: various length packets with intermediate trigger")
current_test.next = 10
yield clk.posedge
start_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
lens = [32, 48, 96, 128, 256]
test_frame = []
for i in range(len(lens)):
test_frame.append(axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(lens[i]))))
for f in test_frame:
source_queue.put(f)
yield clk.posedge
yield delay(200)
yield clk.posedge
trigger_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
stop_time = now()
trigger.next = 1
yield clk.posedge
trigger.next = 0
yield clk.posedge
while output_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
# discard first trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame = sink_queue.get()
# check second trigger output
if not sink_queue.empty():
rx_frame2 = sink_queue.get()
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
cycles = (stop_time - start_time) / 8
cycles1 = (trigger_time - start_time) / 8
print(rx_frame_values)
rx_frame2_values = struct.unpack(">HLLL", bytes(rx_frame2.data))
cycles2 = (stop_time - trigger_time) / 8
print(rx_frame2_values)
assert rx_frame_values[0] == 1
assert rx_frame2_values[0] == 1
assert rx_frame_values[1] == cycles1*8
assert rx_frame2_values[1] == cycles2*8
assert rx_frame_values[1] + rx_frame2_values[1] == cycles*8
assert rx_frame_values[2] + rx_frame2_values[2] == sum(len(f.data) for f in test_frame)
assert rx_frame_values[3] + rx_frame2_values[3] == len(test_frame)
yield delay(100)
raise StopSimulation
return dut, source, monitor_sink, sink, clkgen, check
def bench():
# Parameters
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
LAST_ENABLE = 1
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0))
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks
source_pause = Signal(bool(0))
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource()
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser
)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1
)
source.send(test_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)),
id=2,
dest=1
)
source.send(test_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=1
)
source.send(test_frame)
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=1
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 7: tuser assert")
current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1,
last_cycle_user=1
)
source.send(test_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert rx_frame.last_cycle_user
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
DEPTH = 512
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH > 8)
KEEP_WIDTH = (DATA_WIDTH / 8)
LAST_ENABLE = 1
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
FRAME_FIFO = 1
USER_BAD_FRAME_VALUE = 1
USER_BAD_FRAME_MASK = 1
DROP_BAD_FRAME = 1
DROP_WHEN_FULL = 0
# Inputs
async_rst = Signal(bool(0))
s_clk = Signal(bool(0))
m_clk = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
s_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
s_axis_tvalid = Signal(bool(0))
s_axis_tlast = Signal(bool(0))
s_axis_tid = Signal(intbv(0)[ID_WIDTH:])
s_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
s_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
m_axis_tready = Signal(bool(0))
# Outputs
s_axis_tready = Signal(bool(0))
m_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
m_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
m_axis_tvalid = Signal(bool(0))
m_axis_tlast = Signal(bool(0))
m_axis_tid = Signal(intbv(0)[ID_WIDTH:])
m_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
m_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
s_status_overflow = Signal(bool(0))
s_status_bad_frame = Signal(bool(0))
s_status_good_frame = Signal(bool(0))
m_status_overflow = Signal(bool(0))
m_status_bad_frame = Signal(bool(0))
m_status_good_frame = Signal(bool(0))
# sources and sinks
source_pause = Signal(bool(0))
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource()
source_logic = source.create_logic(s_clk,
async_rst,
tdata=s_axis_tdata,
tkeep=s_axis_tkeep,
tvalid=s_axis_tvalid,
tready=s_axis_tready,
tlast=s_axis_tlast,
tid=s_axis_tid,
tdest=s_axis_tdest,
tuser=s_axis_tuser,
pause=source_pause,
name='source')
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(m_clk,
async_rst,
tdata=m_axis_tdata,
tkeep=m_axis_tkeep,
tvalid=m_axis_tvalid,
tready=m_axis_tready,
tlast=m_axis_tlast,
tid=m_axis_tid,
tdest=m_axis_tdest,
tuser=m_axis_tuser,
pause=sink_pause,
name='sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
async_rst=async_rst,
s_clk=s_clk,
m_clk=m_clk,
current_test=current_test,
s_axis_tdata=s_axis_tdata,
s_axis_tkeep=s_axis_tkeep,
s_axis_tvalid=s_axis_tvalid,
s_axis_tready=s_axis_tready,
s_axis_tlast=s_axis_tlast,
s_axis_tid=s_axis_tid,
s_axis_tdest=s_axis_tdest,
s_axis_tuser=s_axis_tuser,
m_axis_tdata=m_axis_tdata,
m_axis_tkeep=m_axis_tkeep,
m_axis_tvalid=m_axis_tvalid,
m_axis_tready=m_axis_tready,
m_axis_tlast=m_axis_tlast,
m_axis_tid=m_axis_tid,
m_axis_tdest=m_axis_tdest,
m_axis_tuser=m_axis_tuser,
s_status_overflow=s_status_overflow,
s_status_bad_frame=s_status_bad_frame,
s_status_good_frame=s_status_good_frame,
m_status_overflow=m_status_overflow,
m_status_bad_frame=m_status_bad_frame,
m_status_good_frame=m_status_good_frame)
@always(delay(4))
def s_clkgen():
s_clk.next = not s_clk
@always(delay(5))
def m_clkgen():
m_clk.next = not m_clk
s_status_overflow_asserted = Signal(bool(0))
s_status_bad_frame_asserted = Signal(bool(0))
s_status_good_frame_asserted = Signal(bool(0))
m_status_overflow_asserted = Signal(bool(0))
m_status_bad_frame_asserted = Signal(bool(0))
m_status_good_frame_asserted = Signal(bool(0))
@always(s_clk.posedge)
def monitor_1():
if (s_status_overflow):
s_status_overflow_asserted.next = 1
if (s_status_bad_frame):
s_status_bad_frame_asserted.next = 1
if (s_status_good_frame):
s_status_good_frame_asserted.next = 1
@always(m_clk.posedge)
def monitor_2():
if (m_status_overflow):
m_status_overflow_asserted.next = 1
if (m_status_bad_frame):
m_status_bad_frame_asserted.next = 1
if (m_status_good_frame):
m_status_good_frame_asserted.next = 1
@instance
def check():
yield delay(100)
yield s_clk.posedge
async_rst.next = 1
yield s_clk.posedge
yield s_clk.posedge
yield s_clk.posedge
async_rst.next = 0
yield s_clk.posedge
yield delay(100)
yield s_clk.posedge
yield s_clk.posedge
yield s_clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1)
s_status_overflow_asserted.next = 0
s_status_bad_frame_asserted.next = 0
s_status_good_frame_asserted.next = 0
m_status_overflow_asserted.next = 0
m_status_bad_frame_asserted.next = 0
m_status_good_frame_asserted.next = 0
source.send(test_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert not s_status_overflow_asserted
assert not s_status_bad_frame_asserted
assert s_status_good_frame_asserted
assert not m_status_overflow_asserted
assert not m_status_bad_frame_asserted
assert m_status_good_frame_asserted
yield delay(100)
yield s_clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' + bytearray(range(256)),
id=2,
dest=1)
s_status_overflow_asserted.next = 0
s_status_bad_frame_asserted.next = 0
s_status_good_frame_asserted.next = 0
m_status_overflow_asserted.next = 0
m_status_bad_frame_asserted.next = 0
m_status_good_frame_asserted.next = 0
source.send(test_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert not s_status_overflow_asserted
assert not s_status_bad_frame_asserted
assert s_status_good_frame_asserted
assert not m_status_overflow_asserted
assert not m_status_bad_frame_asserted
assert m_status_good_frame_asserted
yield s_clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=1)
s_status_overflow_asserted.next = 0
s_status_bad_frame_asserted.next = 0
s_status_good_frame_asserted.next = 0
m_status_overflow_asserted.next = 0
m_status_bad_frame_asserted.next = 0
m_status_good_frame_asserted.next = 0
source.send(test_frame)
yield s_clk.posedge
yield delay(64)
yield s_clk.posedge
source_pause.next = True
yield delay(32)
yield s_clk.posedge
source_pause.next = False
yield delay(64)
yield m_clk.posedge
sink_pause.next = True
yield delay(32)
yield m_clk.posedge
sink_pause.next = False
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert not s_status_overflow_asserted
assert not s_status_bad_frame_asserted
assert s_status_good_frame_asserted
assert not m_status_overflow_asserted
assert not m_status_bad_frame_asserted
assert m_status_good_frame_asserted
yield delay(100)
yield s_clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2)
s_status_overflow_asserted.next = 0
s_status_bad_frame_asserted.next = 0
s_status_good_frame_asserted.next = 0
m_status_overflow_asserted.next = 0
m_status_bad_frame_asserted.next = 0
m_status_good_frame_asserted.next = 0
source.send(test_frame1)
source.send(test_frame2)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert not s_status_overflow_asserted
assert not s_status_bad_frame_asserted
assert s_status_good_frame_asserted
assert not m_status_overflow_asserted
assert not m_status_bad_frame_asserted
assert m_status_good_frame_asserted
yield delay(100)
yield s_clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2)
s_status_overflow_asserted.next = 0
s_status_bad_frame_asserted.next = 0
s_status_good_frame_asserted.next = 0
m_status_overflow_asserted.next = 0
m_status_bad_frame_asserted.next = 0
m_status_good_frame_asserted.next = 0
source.send(test_frame1)
source.send(test_frame2)
yield s_clk.posedge
while s_axis_tvalid or m_axis_tvalid:
yield s_clk.posedge
yield s_clk.posedge
source_pause.next = False
yield s_clk.posedge
source_pause.next = True
yield s_clk.posedge
source_pause.next = False
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert not s_status_overflow_asserted
assert not s_status_bad_frame_asserted
assert s_status_good_frame_asserted
assert not m_status_overflow_asserted
assert not m_status_bad_frame_asserted
assert m_status_good_frame_asserted
yield delay(100)
yield s_clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=6)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2)
s_status_overflow_asserted.next = 0
s_status_bad_frame_asserted.next = 0
s_status_good_frame_asserted.next = 0
m_status_overflow_asserted.next = 0
m_status_bad_frame_asserted.next = 0
m_status_good_frame_asserted.next = 0
source.send(test_frame1)
source.send(test_frame2)
yield s_clk.posedge
while s_axis_tvalid or m_axis_tvalid:
sink_pause.next = True
yield m_clk.posedge
yield m_clk.posedge
yield m_clk.posedge
sink_pause.next = False
yield m_clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert not s_status_overflow_asserted
assert not s_status_bad_frame_asserted
assert s_status_good_frame_asserted
assert not m_status_overflow_asserted
assert not m_status_bad_frame_asserted
assert m_status_good_frame_asserted
yield delay(100)
yield s_clk.posedge
print("test 7: tuser assert")
current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1,
last_cycle_user=1)
s_status_overflow_asserted.next = 0
s_status_bad_frame_asserted.next = 0
s_status_good_frame_asserted.next = 0
m_status_overflow_asserted.next = 0
m_status_bad_frame_asserted.next = 0
m_status_good_frame_asserted.next = 0
source.send(test_frame)
yield s_clk.posedge
yield delay(1000)
assert sink.empty()
assert not s_status_overflow_asserted
assert s_status_bad_frame_asserted
assert not s_status_good_frame_asserted
assert not m_status_overflow_asserted
assert m_status_bad_frame_asserted
assert not m_status_good_frame_asserted
yield delay(100)
yield s_clk.posedge
print("test 8: single packet overflow")
current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' + bytearray(range(256)) * 2,
id=8,
dest=1)
s_status_overflow_asserted.next = 0
s_status_bad_frame_asserted.next = 0
s_status_good_frame_asserted.next = 0
m_status_overflow_asserted.next = 0
m_status_bad_frame_asserted.next = 0
m_status_good_frame_asserted.next = 0
source.send(test_frame)
yield s_clk.posedge
yield delay(10000)
assert sink.empty()
assert s_status_overflow_asserted
assert not s_status_bad_frame_asserted
assert not s_status_good_frame_asserted
assert m_status_overflow_asserted
assert not m_status_bad_frame_asserted
assert not m_status_good_frame_asserted
yield delay(100)
yield s_clk.posedge
print("test 9: initial sink pause")
current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03', id=9, dest=1)
sink_pause.next = 1
source.send(test_frame)
yield s_clk.posedge
yield s_clk.posedge
yield s_clk.posedge
yield s_clk.posedge
sink_pause.next = 0
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield s_clk.posedge
print("test 10: initial sink pause, assert reset")
current_test.next = 10
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03', id=10, dest=1)
sink_pause.next = 1
source.send(test_frame)
yield s_clk.posedge
yield s_clk.posedge
yield s_clk.posedge
yield s_clk.posedge
async_rst.next = 1
yield s_clk.posedge
async_rst.next = 0
sink_pause.next = 0
yield delay(100)
yield m_clk.posedge
yield m_clk.posedge
yield m_clk.posedge
assert sink.empty()
yield delay(100)
yield s_clk.posedge
print("test 11: backpressure test")
current_test.next = 11
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' + bytearray(range(256)),
id=11,
dest=1)
sink_pause.next = 1
source.send(test_frame)
source.send(test_frame)
yield delay(5000)
yield s_clk.posedge
sink_pause.next = 0
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield s_clk.posedge
print("test 12: many small packets")
current_test.next = 12
test_frame = axis_ep.AXIStreamFrame(b'\xAA', id=12, dest=1)
for k in range(64):
source.send(test_frame)
for k in range(64):
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
output_axis_tready = Signal(bool(0))
wb_dat_i = Signal(intbv(0)[32:])
wb_ack_i = Signal(bool(0))
wb_err_i = Signal(bool(0))
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
wb_adr_o = Signal(intbv(0)[36:])
wb_dat_o = Signal(intbv(0)[32:])
wb_we_o = Signal(bool(0))
wb_sel_o = Signal(intbv(0)[4:])
wb_stb_o = Signal(bool(0))
wb_cyc_o = Signal(bool(0))
busy = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
fifo=source_queue,
pause=source_pause,
name='source')
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
fifo=sink_queue,
pause=sink_pause,
name='sink')
# WB RAM model
wb_ram_inst = wb.WBRam(2**16)
wb_ram_port0 = wb_ram_inst.create_port(clk,
adr_i=wb_adr_o,
dat_i=wb_dat_o,
dat_o=wb_dat_i,
we_i=wb_we_o,
sel_i=wb_sel_o,
stb_i=wb_stb_o,
ack_o=wb_ack_i,
cyc_i=wb_cyc_o,
latency=1,
async=False,
name='wb_ram')
# DUT
dut = dut_soc_interface_32(clk, rst, current_test, input_axis_tdata,
input_axis_tvalid, input_axis_tready,
input_axis_tlast, output_axis_tdata,
output_axis_tvalid, output_axis_tready,
output_axis_tlast, wb_adr_o, wb_dat_i, wb_dat_o,
wb_we_o, wb_sel_o, wb_stb_o, wb_ack_i, wb_err_i,
wb_cyc_o, busy)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
print("test 1: Write to bank 0")
current_test.next = 1
test_frame = bytearray('\xB0\x00\x00\x00\x00\xAA')
source_queue.put(test_frame)
yield clk.posedge
yield busy.negedge
yield clk.posedge
yield clk.posedge
data = wb_ram_inst.read_mem(0, 1)
assert data == '\xAA'
yield delay(100)
yield clk.posedge
print("test 2: Longer write to bank 0")
current_test.next = 2
test_frame = bytearray(
'\xB0\x00\x00\x00\x20\x11\x22\x33\x44\x55\x66\x77')
source_queue.put(test_frame)
yield clk.posedge
yield busy.negedge
yield clk.posedge
yield clk.posedge
data = wb_ram_inst.read_mem(32, 7)
assert data == '\x11\x22\x33\x44\x55\x66\x77'
yield delay(100)
yield clk.posedge
print("test 3: Read from bank 0")
current_test.next = 3
test_frame = bytearray('\xA0\x00\x00\x00\x00' + '\x00' * 8)
source_queue.put(test_frame)
yield clk.posedge
yield busy.negedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = bytearray(sink_queue.get())
assert rx_frame.find('\x01\xAA') >= 0
yield delay(100)
yield clk.posedge
print("test 4: Longer read from bank 0")
current_test.next = 4
test_frame = bytearray('\xA0\x00\x00\x00\x20' + '\x00' * 15)
source_queue.put(test_frame)
yield clk.posedge
yield busy.negedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = bytearray(sink_queue.get())
print(repr(rx_frame))
assert rx_frame.find('\x01\x11\x22\x33\x44\x55\x66\x77') >= 0
yield delay(100)
yield clk.posedge
print("test 5: Write to bank 0, source pause")
current_test.next = 5
test_frame = bytearray(
'\xB0\x00\x00\x00\x20\x11\x22\x33\x44\x55\x66\x77')
source_queue.put(test_frame)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
data = wb_ram_inst.read_mem(32, 7)
assert data == '\x11\x22\x33\x44\x55\x66\x77'
yield delay(100)
yield clk.posedge
print("test 6: Read from bank 0, source pause")
current_test.next = 6
test_frame = bytearray('\xA0\x00\x00\x00\x20' + '\x00' * 10)
source_queue.put(test_frame)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = bytearray(sink_queue.get())
assert rx_frame.find('\x01\x11\x22\x33\x44\x55\x66\x77') >= 0
yield delay(100)
yield clk.posedge
print("test 7: Read from bank 0, sink pause")
current_test.next = 7
test_frame = bytearray('\xA0\x00\x00\x00\x20' + '\x00' * 40)
source_queue.put(test_frame)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = bytearray(sink_queue.get())
print(repr(rx_frame))
assert rx_frame.find('\x01\x11\x22\x33\x44\x55\x66\x77') >= 0
yield delay(100)
yield clk.posedge
print("test 8: Write to bank 1")
current_test.next = 8
test_frame = bytearray('\xB1\x00\x00\x01\x00\x11')
source_queue.put(test_frame)
yield clk.posedge
yield busy.negedge
yield clk.posedge
yield clk.posedge
data = wb_ram_inst.read_mem(256, 1)
assert data == '\x11'
yield delay(100)
yield clk.posedge
print("test 9: Longer write to bank 1")
current_test.next = 9
test_frame = bytearray(
'\xB1\x00\x00\x01\x20\xAA\xBB\xCC\xDD\xEE\xFF\x77')
source_queue.put(test_frame)
yield clk.posedge
yield busy.negedge
yield clk.posedge
yield clk.posedge
data = wb_ram_inst.read_mem(288, 7)
assert data == '\xAA\xBB\xCC\xDD\xEE\xFF\x77'
yield delay(100)
yield clk.posedge
print("test 10: Read from bank 1")
current_test.next = 10
test_frame = bytearray('\xA1\x00\x00\x01\x00' + '\x00' * 8)
source_queue.put(test_frame)
yield clk.posedge
yield busy.negedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = bytearray(sink_queue.get())
assert rx_frame.find('\x01\x11') >= 0
yield delay(100)
yield clk.posedge
print("test 11: Longer read from bank 1")
current_test.next = 11
test_frame = bytearray('\xA1\x00\x00\x01\x20' + '\x00' * 15)
source_queue.put(test_frame)
yield clk.posedge
yield busy.negedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = bytearray(sink_queue.get())
assert rx_frame.find('\x01\xAA\xBB\xCC\xDD\xEE\xFF\x77') >= 0
yield delay(100)
raise StopSimulation
return dut, source, sink, wb_ram_port0, clkgen, check
def bench():
# Parameters
FIFO_DEPTH = 512
SPEEDUP = 0
S_COUNT = 4
M_COUNT = 4
S_DATA_WIDTH = 64
S_KEEP_ENABLE = (S_DATA_WIDTH>8)
S_KEEP_WIDTH = (S_DATA_WIDTH/8)
M_DATA_WIDTH = 64
M_KEEP_ENABLE = (M_DATA_WIDTH>8)
M_KEEP_WIDTH = (M_DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_WIDTH = (M_COUNT+1-1).bit_length()
USER_ENABLE = 1
USER_WIDTH = 1
USER_BAD_FRAME_VALUE = 1
USER_BAD_FRAME_MASK = 1
DROP_BAD_FRAME = 1
DROP_WHEN_FULL = 0
M_BASE = [0, 1, 2, 3]
M_TOP = [0, 1, 2, 3]
M_CONNECT = [0b1111]*M_COUNT
ARB_TYPE_ROUND_ROBIN = 1
ARB_LSB_HIGH_PRIORITY = 1
RAM_PIPELINE = 2
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_tdata_list = [Signal(intbv(0)[S_DATA_WIDTH:]) for i in range(S_COUNT)]
s_axis_tkeep_list = [Signal(intbv(1)[S_KEEP_WIDTH:]) for i in range(S_COUNT)]
s_axis_tvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axis_tlast_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axis_tid_list = [Signal(intbv(0)[ID_WIDTH:]) for i in range(S_COUNT)]
s_axis_tdest_list = [Signal(intbv(0)[DEST_WIDTH:]) for i in range(S_COUNT)]
s_axis_tuser_list = [Signal(intbv(0)[USER_WIDTH:]) for i in range(S_COUNT)]
s_axis_tdata = ConcatSignal(*reversed(s_axis_tdata_list))
s_axis_tkeep = ConcatSignal(*reversed(s_axis_tkeep_list))
s_axis_tvalid = ConcatSignal(*reversed(s_axis_tvalid_list))
s_axis_tlast = ConcatSignal(*reversed(s_axis_tlast_list))
s_axis_tid = ConcatSignal(*reversed(s_axis_tid_list))
s_axis_tdest = ConcatSignal(*reversed(s_axis_tdest_list))
s_axis_tuser = ConcatSignal(*reversed(s_axis_tuser_list))
m_axis_tready_list = [Signal(bool(0)) for i in range(M_COUNT)]
m_axis_tready = ConcatSignal(*reversed(m_axis_tready_list))
# Outputs
s_axis_tready = Signal(intbv(0)[S_COUNT:])
s_axis_tready_list = [s_axis_tready(i) for i in range(S_COUNT)]
m_axis_tdata = Signal(intbv(0)[M_COUNT*M_DATA_WIDTH:])
m_axis_tkeep = Signal(intbv(0xf)[M_COUNT*M_KEEP_WIDTH:])
m_axis_tvalid = Signal(intbv(0)[M_COUNT:])
m_axis_tlast = Signal(intbv(0)[M_COUNT:])
m_axis_tid = Signal(intbv(0)[M_COUNT*ID_WIDTH:])
m_axis_tdest = Signal(intbv(0)[M_COUNT*DEST_WIDTH:])
m_axis_tuser = Signal(intbv(0)[M_COUNT*USER_WIDTH:])
m_axis_tdata_list = [m_axis_tdata((i+1)*M_DATA_WIDTH, i*M_DATA_WIDTH) for i in range(M_COUNT)]
m_axis_tkeep_list = [m_axis_tkeep((i+1)*M_KEEP_WIDTH, i*M_KEEP_WIDTH) for i in range(M_COUNT)]
m_axis_tvalid_list = [m_axis_tvalid(i) for i in range(M_COUNT)]
m_axis_tlast_list = [m_axis_tlast(i) for i in range(M_COUNT)]
m_axis_tid_list = [m_axis_tid((i+1)*ID_WIDTH, i*ID_WIDTH) for i in range(M_COUNT)]
m_axis_tdest_list = [m_axis_tdest((i+1)*DEST_WIDTH, i*DEST_WIDTH) for i in range(M_COUNT)]
m_axis_tuser_list = [m_axis_tuser((i+1)*USER_WIDTH, i*USER_WIDTH) for i in range(M_COUNT)]
status_overflow = Signal(intbv(0)[S_COUNT:])
status_bad_frame = Signal(intbv(0)[S_COUNT:])
status_good_frame = Signal(intbv(0)[S_COUNT:])
# sources and sinks
source_pause_list = []
source_list = []
source_logic_list = []
sink_pause_list = []
sink_list = []
sink_logic_list = []
for k in range(S_COUNT):
s = axis_ep.AXIStreamSource()
p = Signal(bool(0))
source_list.append(s)
source_pause_list.append(p)
source_logic_list.append(s.create_logic(
clk,
rst,
tdata=s_axis_tdata_list[k],
tkeep=s_axis_tkeep_list[k],
tvalid=s_axis_tvalid_list[k],
tready=s_axis_tready_list[k],
tlast=s_axis_tlast_list[k],
tid=s_axis_tid_list[k],
tdest=s_axis_tdest_list[k],
tuser=s_axis_tuser_list[k],
pause=p,
name='source_%d' % k
))
for k in range(M_COUNT):
s = axis_ep.AXIStreamSink()
p = Signal(bool(0))
sink_list.append(s)
sink_pause_list.append(p)
sink_logic_list.append(s.create_logic(
clk,
rst,
tdata=m_axis_tdata_list[k],
tkeep=m_axis_tkeep_list[k],
tvalid=m_axis_tvalid_list[k],
tready=m_axis_tready_list[k],
tlast=m_axis_tlast_list[k],
tid=m_axis_tid_list[k],
tdest=m_axis_tdest_list[k],
tuser=m_axis_tuser_list[k],
pause=p,
name='sink_%d' % k
))
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_axis_tdata=s_axis_tdata,
s_axis_tkeep=s_axis_tkeep,
s_axis_tvalid=s_axis_tvalid,
s_axis_tready=s_axis_tready,
s_axis_tlast=s_axis_tlast,
s_axis_tid=s_axis_tid,
s_axis_tdest=s_axis_tdest,
s_axis_tuser=s_axis_tuser,
m_axis_tdata=m_axis_tdata,
m_axis_tkeep=m_axis_tkeep,
m_axis_tvalid=m_axis_tvalid,
m_axis_tready=m_axis_tready,
m_axis_tlast=m_axis_tlast,
m_axis_tid=m_axis_tid,
m_axis_tdest=m_axis_tdest,
m_axis_tuser=m_axis_tuser,
status_overflow=status_overflow,
status_bad_frame=status_bad_frame,
status_good_frame=status_good_frame
)
@always(delay(4))
def clkgen():
clk.next = not clk
status_overflow_latch = Signal(intbv(0)[S_COUNT:])
status_bad_frame_latch = Signal(intbv(0)[S_COUNT:])
status_good_frame_latch = Signal(intbv(0)[S_COUNT:])
@always(clk.posedge)
def monitor():
if status_overflow:
status_overflow_latch.next = status_overflow_latch | status_overflow
if status_bad_frame:
status_bad_frame_latch.next = status_bad_frame_latch | status_bad_frame
if status_good_frame:
status_good_frame_latch.next = status_good_frame_latch | status_good_frame
def wait_normal():
while s_axis_tvalid:
yield clk.posedge
def wait_pause_source():
while s_axis_tvalid:
yield clk.posedge
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = True
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
def wait_pause_sink():
while s_axis_tvalid:
for k in range(M_COUNT):
sink_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
for k in range(M_COUNT):
sink_pause_list[k].next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: 0123 -> 0123")
current_test.next = 1
test_frame0 = axis_ep.AXIStreamFrame(b'\x01\x00\x00\xFF'+bytearray(range(256)), id=0, dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x01\x01\x01\xFF'+bytearray(range(256)), id=1, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(b'\x01\x02\x02\xFF'+bytearray(range(256)), id=2, dest=2)
test_frame3 = axis_ep.AXIStreamFrame(b'\x01\x03\x03\xFF'+bytearray(range(256)), id=3, dest=3)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
source_list[1].send(test_frame1)
source_list[2].send(test_frame2)
source_list[3].send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
yield sink_list[1].wait()
rx_frame1 = sink_list[1].recv()
assert rx_frame1 == test_frame1
yield sink_list[2].wait()
rx_frame2 = sink_list[2].recv()
assert rx_frame2 == test_frame2
yield sink_list[3].wait()
rx_frame3 = sink_list[3].recv()
assert rx_frame3 == test_frame3
assert sink_list[0].empty()
assert sink_list[1].empty()
assert sink_list[2].empty()
assert sink_list[3].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0xf
yield delay(100)
yield clk.posedge
print("test 2: 0123 -> 3210")
current_test.next = 2
test_frame0 = axis_ep.AXIStreamFrame(b'\x02\x00\x03\xFF'+bytearray(range(256)), id=0, dest=3)
test_frame1 = axis_ep.AXIStreamFrame(b'\x02\x01\x02\xFF'+bytearray(range(256)), id=1, dest=2)
test_frame2 = axis_ep.AXIStreamFrame(b'\x02\x02\x01\xFF'+bytearray(range(256)), id=2, dest=1)
test_frame3 = axis_ep.AXIStreamFrame(b'\x02\x03\x00\xFF'+bytearray(range(256)), id=3, dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
source_list[1].send(test_frame1)
source_list[2].send(test_frame2)
source_list[3].send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame3
yield sink_list[1].wait()
rx_frame1 = sink_list[1].recv()
assert rx_frame1 == test_frame2
yield sink_list[2].wait()
rx_frame2 = sink_list[2].recv()
assert rx_frame2 == test_frame1
yield sink_list[3].wait()
rx_frame3 = sink_list[3].recv()
assert rx_frame3 == test_frame0
assert sink_list[0].empty()
assert sink_list[1].empty()
assert sink_list[2].empty()
assert sink_list[3].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0xf
yield delay(100)
yield clk.posedge
print("test 3: 0000 -> 0123")
current_test.next = 3
test_frame0 = axis_ep.AXIStreamFrame(b'\x03\x00\x00\xFF'+bytearray(range(256)), id=0, dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x03\x00\x01\xFF'+bytearray(range(256)), id=0, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(b'\x03\x00\x02\xFF'+bytearray(range(256)), id=0, dest=2)
test_frame3 = axis_ep.AXIStreamFrame(b'\x03\x00\x03\xFF'+bytearray(range(256)), id=0, dest=3)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
source_list[0].send(test_frame1)
source_list[0].send(test_frame2)
source_list[0].send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
yield sink_list[1].wait()
rx_frame1 = sink_list[1].recv()
assert rx_frame1 == test_frame1
yield sink_list[2].wait()
rx_frame2 = sink_list[2].recv()
assert rx_frame2 == test_frame2
yield sink_list[3].wait()
rx_frame3 = sink_list[3].recv()
assert rx_frame3 == test_frame3
assert sink_list[0].empty()
assert sink_list[1].empty()
assert sink_list[2].empty()
assert sink_list[3].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0x1
yield delay(100)
yield clk.posedge
print("test 4: 0123 -> 0000")
current_test.next = 4
test_frame0 = axis_ep.AXIStreamFrame(b'\x04\x00\x00\xFF'+bytearray(range(256)), id=0, dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x04\x01\x00\xFF'+bytearray(range(256)), id=1, dest=0)
test_frame2 = axis_ep.AXIStreamFrame(b'\x04\x02\x00\xFF'+bytearray(range(256)), id=2, dest=0)
test_frame3 = axis_ep.AXIStreamFrame(b'\x04\x03\x00\xFF'+bytearray(range(256)), id=3, dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
yield clk.posedge
source_list[1].send(test_frame1)
source_list[2].send(test_frame2)
source_list[3].send(test_frame3)
yield clk.posedge
yield wait()
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
yield sink_list[0].wait()
rx_frame1 = sink_list[0].recv()
assert rx_frame1 == test_frame1
yield sink_list[0].wait()
rx_frame2 = sink_list[0].recv()
assert rx_frame2 == test_frame2
yield sink_list[0].wait()
rx_frame3 = sink_list[0].recv()
assert rx_frame3 == test_frame3
assert sink_list[0].empty()
assert sink_list[1].empty()
assert sink_list[2].empty()
assert sink_list[3].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0xf
yield delay(100)
yield clk.posedge
print("test 5: 0000 -> 0000")
current_test.next = 5
test_frame0 = axis_ep.AXIStreamFrame(b'\x05\x00\x00\xFF'+bytearray(range(256)), id=0, dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x05\x00\x00\xFF'+bytearray(range(256)), id=0, dest=0)
test_frame2 = axis_ep.AXIStreamFrame(b'\x05\x00\x00\xFF'+bytearray(range(256)), id=0, dest=0)
test_frame3 = axis_ep.AXIStreamFrame(b'\x05\x00\x00\xFF'+bytearray(range(256)), id=0, dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
source_list[0].send(test_frame1)
source_list[0].send(test_frame2)
source_list[0].send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
yield sink_list[0].wait()
rx_frame1 = sink_list[0].recv()
assert rx_frame1 == test_frame1
yield sink_list[0].wait()
rx_frame2 = sink_list[0].recv()
assert rx_frame2 == test_frame2
yield sink_list[0].wait()
rx_frame3 = sink_list[0].recv()
assert rx_frame3 == test_frame3
assert sink_list[0].empty()
assert sink_list[1].empty()
assert sink_list[2].empty()
assert sink_list[3].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0x1
yield delay(100)
yield clk.posedge
print("test 6: bad decoding")
current_test.next = 6
test_frame0 = axis_ep.AXIStreamFrame(b'\x06\x00\x00\xFF'+bytearray(range(256)), id=0, dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x06\x01\x01\xFF'+bytearray(range(256)), id=1, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(b'\x06\x02\x04\xFF'+bytearray(range(256)), id=2, dest=4)
test_frame3 = axis_ep.AXIStreamFrame(b'\x06\x03\x05\xFF'+bytearray(range(256)), id=3, dest=5)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
source_list[1].send(test_frame1)
source_list[2].send(test_frame2)
source_list[3].send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
yield sink_list[1].wait()
rx_frame1 = sink_list[1].recv()
assert rx_frame1 == test_frame1
assert sink_list[0].empty()
assert sink_list[1].empty()
assert sink_list[2].empty()
assert sink_list[3].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0x3
yield delay(100)
yield clk.posedge
print("test 7: tuser assert")
current_test.next = 7
test_frame0 = axis_ep.AXIStreamFrame(b'\x07\x00\x00\xFF'+bytearray(range(256)), id=0, dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x07\x00\x01\xFF'+bytearray(range(256)), id=0, dest=1, last_cycle_user=1)
test_frame2 = axis_ep.AXIStreamFrame(b'\x07\x00\x02\xFF'+bytearray(range(256)), id=0, dest=2)
test_frame3 = axis_ep.AXIStreamFrame(b'\x07\x00\x03\xFF'+bytearray(range(256)), id=0, dest=3)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
source_list[0].send(test_frame1)
source_list[0].send(test_frame2)
source_list[0].send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
yield sink_list[2].wait()
rx_frame2 = sink_list[2].recv()
assert rx_frame2 == test_frame2
yield sink_list[3].wait()
rx_frame3 = sink_list[3].recv()
assert rx_frame3 == test_frame3
assert sink_list[0].empty()
assert sink_list[1].empty()
assert sink_list[2].empty()
assert sink_list[3].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x1
assert status_good_frame_latch == 0x1
yield delay(100)
yield clk.posedge
print("test 8: single packet overflow")
current_test.next = 8
test_frame0 = axis_ep.AXIStreamFrame(b'\x08\x00\x00\xFF'+bytearray(range(256))*3, id=0, dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x08\x01\x01\xFF'+bytearray(range(256))*3, id=1, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(b'\x08\x02\x02\xFF'+bytearray(range(256))*3, id=2, dest=2)
test_frame3 = axis_ep.AXIStreamFrame(b'\x08\x03\x03\xFF'+bytearray(range(256))*3, id=3, dest=3)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
source_list[1].send(test_frame1)
source_list[2].send(test_frame2)
source_list[3].send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
yield delay(100)
assert sink_list[0].empty()
assert sink_list[1].empty()
assert sink_list[2].empty()
assert sink_list[3].empty()
assert status_overflow_latch == 0xf
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0x0
yield delay(100)
yield clk.posedge
print("test 9: initial sink pause")
current_test.next = 9
test_frame0 = axis_ep.AXIStreamFrame(b'\x09\x00\x00\xFF'+bytearray(range(256)), id=0, dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x09\x01\x01\xFF'+bytearray(range(256)), id=1, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(b'\x09\x02\x02\xFF'+bytearray(range(256)), id=2, dest=2)
test_frame3 = axis_ep.AXIStreamFrame(b'\x09\x03\x03\xFF'+bytearray(range(256)), id=3, dest=3)
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
source_list[1].send(test_frame1)
source_list[2].send(test_frame2)
source_list[3].send(test_frame3)
for k in range(M_COUNT):
sink_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
while (s_axis_tvalid):
yield clk.posedge
for k in range(20):
yield clk.posedge
for k in range(M_COUNT):
sink_pause_list[k].next = False
yield wait_normal()
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
yield sink_list[1].wait()
rx_frame1 = sink_list[1].recv()
assert rx_frame1 == test_frame1
yield sink_list[2].wait()
rx_frame2 = sink_list[2].recv()
assert rx_frame2 == test_frame2
yield sink_list[3].wait()
rx_frame3 = sink_list[3].recv()
assert rx_frame3 == test_frame3
assert sink_list[0].empty()
assert sink_list[1].empty()
assert sink_list[2].empty()
assert sink_list[3].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0xf
yield delay(100)
yield clk.posedge
print("test 10: initial sink pause, reset")
current_test.next = 10
test_frame0 = axis_ep.AXIStreamFrame(b'\x0A\x00\x00\xFF'+bytearray(range(256)), id=0, dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x0A\x01\x01\xFF'+bytearray(range(256)), id=1, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(b'\x0A\x02\x02\xFF'+bytearray(range(256)), id=2, dest=2)
test_frame3 = axis_ep.AXIStreamFrame(b'\x0A\x03\x03\xFF'+bytearray(range(256)), id=3, dest=3)
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
source_list[1].send(test_frame1)
source_list[2].send(test_frame2)
source_list[3].send(test_frame3)
for k in range(M_COUNT):
sink_pause_list[k].next = True
yield clk.posedge
yield clk.posedge
while (s_axis_tvalid):
yield clk.posedge
for k in range(20):
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
for k in range(M_COUNT):
sink_pause_list[k].next = False
yield delay(500)
assert sink_list[0].empty()
assert sink_list[1].empty()
assert sink_list[2].empty()
assert sink_list[3].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0xf
yield delay(100)
yield clk.posedge
print("test 11: backpressure test")
current_test.next = 11
test_frame0 = axis_ep.AXIStreamFrame(b'\x0B\x00\x00\xFF'+bytearray(range(256)), id=0, dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x0B\x00\x00\xFF'+bytearray(range(256)), id=0, dest=0)
test_frame2 = axis_ep.AXIStreamFrame(b'\x0B\x00\x00\xFF'+bytearray(range(256)), id=0, dest=0)
test_frame3 = axis_ep.AXIStreamFrame(b'\x0B\x00\x00\xFF'+bytearray(range(256)), id=0, dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
source_list[0].send(test_frame0)
source_list[0].send(test_frame1)
source_list[0].send(test_frame2)
source_list[0].send(test_frame3)
for k in range(M_COUNT):
sink_pause_list[k].next = True
for k in range(100):
yield clk.posedge
for k in range(M_COUNT):
sink_pause_list[k].next = False
yield wait()
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
yield sink_list[0].wait()
rx_frame1 = sink_list[0].recv()
assert rx_frame1 == test_frame1
yield sink_list[0].wait()
rx_frame2 = sink_list[0].recv()
assert rx_frame2 == test_frame2
yield sink_list[0].wait()
rx_frame3 = sink_list[0].recv()
assert rx_frame3 == test_frame3
assert sink_list[0].empty()
assert sink_list[1].empty()
assert sink_list[2].empty()
assert sink_list[3].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0x1
yield delay(100)
yield clk.posedge
print("test 12: many small packets, one to one parallel")
current_test.next = 12
test_frame0 = axis_ep.AXIStreamFrame(b'\x0C\x00\x00\xFF'+bytearray(range(4)), id=0, dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x0C\x01\x01\xFF'+bytearray(range(4)), id=1, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(b'\x0C\x02\x02\xFF'+bytearray(range(4)), id=2, dest=2)
test_frame3 = axis_ep.AXIStreamFrame(b'\x0C\x03\x03\xFF'+bytearray(range(4)), id=3, dest=3)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
for k in range(64):
source_list[0].send(test_frame0)
source_list[1].send(test_frame1)
source_list[2].send(test_frame2)
source_list[3].send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
for k in range(64):
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
yield sink_list[1].wait()
rx_frame1 = sink_list[1].recv()
assert rx_frame1 == test_frame1
yield sink_list[2].wait()
rx_frame2 = sink_list[2].recv()
assert rx_frame2 == test_frame2
yield sink_list[3].wait()
rx_frame3 = sink_list[3].recv()
assert rx_frame3 == test_frame3
assert sink_list[0].empty()
assert sink_list[1].empty()
assert sink_list[2].empty()
assert sink_list[3].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0xf
yield delay(100)
yield clk.posedge
print("test 13: many small packets, many to one")
current_test.next = 13
test_frame0 = axis_ep.AXIStreamFrame(b'\x0D\x00\x00\xFF'+bytearray(range(4)), id=0, dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x0D\x01\x00\xFF'+bytearray(range(4)), id=1, dest=0)
test_frame2 = axis_ep.AXIStreamFrame(b'\x0D\x02\x00\xFF'+bytearray(range(4)), id=2, dest=0)
test_frame3 = axis_ep.AXIStreamFrame(b'\x0D\x03\x00\xFF'+bytearray(range(4)), id=3, dest=0)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
for k in range(64):
source_list[0].send(test_frame0)
yield clk.posedge
yield clk.posedge
source_list[1].send(test_frame1)
source_list[2].send(test_frame2)
source_list[3].send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
for k in range(64):
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
yield sink_list[0].wait()
rx_frame1 = sink_list[0].recv()
assert rx_frame1 == test_frame1
yield sink_list[0].wait()
rx_frame2 = sink_list[0].recv()
assert rx_frame2 == test_frame2
yield sink_list[0].wait()
rx_frame3 = sink_list[0].recv()
assert rx_frame3 == test_frame3
assert sink_list[0].empty()
assert sink_list[1].empty()
assert sink_list[2].empty()
assert sink_list[3].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0xf
yield delay(100)
yield clk.posedge
print("test 14: many small packets, one to many")
current_test.next = 14
test_frame0 = axis_ep.AXIStreamFrame(b'\x0E\x00\x00\xFF'+bytearray(range(4)), id=0, dest=0)
test_frame1 = axis_ep.AXIStreamFrame(b'\x0E\x00\x01\xFF'+bytearray(range(4)), id=0, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(b'\x0E\x00\x02\xFF'+bytearray(range(4)), id=0, dest=2)
test_frame3 = axis_ep.AXIStreamFrame(b'\x0E\x00\x03\xFF'+bytearray(range(4)), id=0, dest=3)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
status_overflow_latch.next = 0
status_bad_frame_latch.next = 0
status_good_frame_latch.next = 0
for k in range(64):
source_list[0].send(test_frame0)
source_list[0].send(test_frame1)
source_list[0].send(test_frame2)
source_list[0].send(test_frame3)
yield clk.posedge
yield clk.posedge
yield wait()
for k in range(64):
yield sink_list[0].wait()
rx_frame0 = sink_list[0].recv()
assert rx_frame0 == test_frame0
yield sink_list[1].wait()
rx_frame1 = sink_list[1].recv()
assert rx_frame1 == test_frame1
yield sink_list[2].wait()
rx_frame2 = sink_list[2].recv()
assert rx_frame2 == test_frame2
yield sink_list[3].wait()
rx_frame3 = sink_list[3].recv()
assert rx_frame3 == test_frame3
assert sink_list[0].empty()
assert sink_list[1].empty()
assert sink_list[2].empty()
assert sink_list[3].empty()
assert status_overflow_latch == 0x0
assert status_bad_frame_latch == 0x0
assert status_good_frame_latch == 0x1
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH > 8)
KEEP_WIDTH = (DATA_WIDTH / 8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_0_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_0_axis_tvalid = Signal(bool(0))
input_0_axis_tlast = Signal(bool(0))
input_0_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_0_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_0_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_1_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_1_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_1_axis_tvalid = Signal(bool(0))
input_1_axis_tlast = Signal(bool(0))
input_1_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_1_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_1_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_2_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_2_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_2_axis_tvalid = Signal(bool(0))
input_2_axis_tlast = Signal(bool(0))
input_2_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_2_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_2_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_3_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_3_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_3_axis_tvalid = Signal(bool(0))
input_3_axis_tlast = Signal(bool(0))
input_3_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_3_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_3_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0))
enable = Signal(bool(0))
select = Signal(intbv(0)[2:])
# Outputs
input_0_axis_tready = Signal(bool(0))
input_1_axis_tready = Signal(bool(0))
input_2_axis_tready = Signal(bool(0))
input_3_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks
source_0_pause = Signal(bool(0))
source_1_pause = Signal(bool(0))
source_2_pause = Signal(bool(0))
source_3_pause = Signal(bool(0))
sink_pause = Signal(bool(0))
source_0 = axis_ep.AXIStreamSource()
source_0_logic = source_0.create_logic(clk,
rst,
tdata=input_0_axis_tdata,
tkeep=input_0_axis_tkeep,
tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready,
tlast=input_0_axis_tlast,
tid=input_0_axis_tid,
tdest=input_0_axis_tdest,
tuser=input_0_axis_tuser,
pause=source_0_pause,
name='source_0')
source_1 = axis_ep.AXIStreamSource()
source_1_logic = source_1.create_logic(clk,
rst,
tdata=input_1_axis_tdata,
tkeep=input_1_axis_tkeep,
tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready,
tlast=input_1_axis_tlast,
tid=input_1_axis_tid,
tdest=input_1_axis_tdest,
tuser=input_1_axis_tuser,
pause=source_1_pause,
name='source_1')
source_2 = axis_ep.AXIStreamSource()
source_2_logic = source_2.create_logic(clk,
rst,
tdata=input_2_axis_tdata,
tkeep=input_2_axis_tkeep,
tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready,
tlast=input_2_axis_tlast,
tid=input_2_axis_tid,
tdest=input_2_axis_tdest,
tuser=input_2_axis_tuser,
pause=source_2_pause,
name='source_2')
source_3 = axis_ep.AXIStreamSource()
source_3_logic = source_3.create_logic(clk,
rst,
tdata=input_3_axis_tdata,
tkeep=input_3_axis_tkeep,
tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready,
tlast=input_3_axis_tlast,
tid=input_3_axis_tid,
tdest=input_3_axis_tdest,
tuser=input_3_axis_tuser,
pause=source_3_pause,
name='source_3')
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tkeep=input_0_axis_tkeep,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tid=input_0_axis_tid,
input_0_axis_tdest=input_0_axis_tdest,
input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tkeep=input_1_axis_tkeep,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tid=input_1_axis_tid,
input_1_axis_tdest=input_1_axis_tdest,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tkeep=input_2_axis_tkeep,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tid=input_2_axis_tid,
input_2_axis_tdest=input_2_axis_tdest,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tkeep=input_3_axis_tkeep,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tid=input_3_axis_tid,
input_3_axis_tdest=input_3_axis_tdest,
input_3_axis_tuser=input_3_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser,
enable=enable,
select=select)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
enable.next = True
yield clk.posedge
print("test 1: select port 0")
current_test.next = 1
select.next = 0
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1)
source_0.send(test_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: select port 1")
current_test.next = 2
select.next = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=2,
dest=1)
source_1.send(test_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 3: back-to-back packets, same port")
current_test.next = 3
select.next = 0
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=2)
source_0.send(test_frame1)
source_0.send(test_frame2)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets, different ports")
current_test.next = 4
select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
yield clk.posedge
select.next = 2
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alterate pause source")
current_test.next = 5
select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
source_0_pause.next = True
source_1_pause.next = True
source_2_pause.next = True
source_3_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_0_pause.next = False
source_1_pause.next = False
source_2_pause.next = False
source_3_pause.next = False
yield clk.posedge
select.next = 2
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alterate pause sink")
current_test.next = 6
select.next = 1
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2)
source_1.send(test_frame1)
source_2.send(test_frame2)
yield clk.posedge
while input_0_axis_tvalid or input_1_axis_tvalid or input_2_axis_tvalid or input_3_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
select.next = 2
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
S_COUNT = 4
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH > 8)
KEEP_WIDTH = (DATA_WIDTH / 8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
ARB_TYPE = "PRIORITY"
LSB_PRIORITY = "HIGH"
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_tdata_list = [Signal(intbv(0)[DATA_WIDTH:]) for i in range(S_COUNT)]
s_axis_tkeep_list = [Signal(intbv(0)[KEEP_WIDTH:]) for i in range(S_COUNT)]
s_axis_tvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axis_tlast_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axis_tid_list = [Signal(intbv(0)[ID_WIDTH:]) for i in range(S_COUNT)]
s_axis_tdest_list = [Signal(intbv(0)[DEST_WIDTH:]) for i in range(S_COUNT)]
s_axis_tuser_list = [Signal(intbv(0)[USER_WIDTH:]) for i in range(S_COUNT)]
s_axis_tdata = ConcatSignal(*reversed(s_axis_tdata_list))
s_axis_tkeep = ConcatSignal(*reversed(s_axis_tkeep_list))
s_axis_tvalid = ConcatSignal(*reversed(s_axis_tvalid_list))
s_axis_tlast = ConcatSignal(*reversed(s_axis_tlast_list))
s_axis_tid = ConcatSignal(*reversed(s_axis_tid_list))
s_axis_tdest = ConcatSignal(*reversed(s_axis_tdest_list))
s_axis_tuser = ConcatSignal(*reversed(s_axis_tuser_list))
m_axis_tready = Signal(bool(0))
# Outputs
s_axis_tready = Signal(intbv(0)[S_COUNT:])
s_axis_tready_list = [s_axis_tready(i) for i in range(S_COUNT)]
m_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
m_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
m_axis_tvalid = Signal(bool(0))
m_axis_tlast = Signal(bool(0))
m_axis_tid = Signal(intbv(0)[ID_WIDTH:])
m_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
m_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks
source_pause_list = []
source_list = []
source_logic_list = []
sink_pause = Signal(bool(0))
for k in range(S_COUNT):
s = axis_ep.AXIStreamSource()
p = Signal(bool(0))
source_list.append(s)
source_pause_list.append(p)
source_logic_list.append(
s.create_logic(clk,
rst,
tdata=s_axis_tdata_list[k],
tkeep=s_axis_tkeep_list[k],
tvalid=s_axis_tvalid_list[k],
tready=s_axis_tready_list[k],
tlast=s_axis_tlast_list[k],
tid=s_axis_tid_list[k],
tdest=s_axis_tdest_list[k],
tuser=s_axis_tuser_list[k],
pause=p,
name='source_%d' % k))
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(clk,
rst,
tdata=m_axis_tdata,
tkeep=m_axis_tkeep,
tvalid=m_axis_tvalid,
tready=m_axis_tready,
tlast=m_axis_tlast,
tid=m_axis_tid,
tdest=m_axis_tdest,
tuser=m_axis_tuser,
pause=sink_pause,
name='sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_axis_tdata=s_axis_tdata,
s_axis_tkeep=s_axis_tkeep,
s_axis_tvalid=s_axis_tvalid,
s_axis_tready=s_axis_tready,
s_axis_tlast=s_axis_tlast,
s_axis_tid=s_axis_tid,
s_axis_tdest=s_axis_tdest,
s_axis_tuser=s_axis_tuser,
m_axis_tdata=m_axis_tdata,
m_axis_tkeep=m_axis_tkeep,
m_axis_tvalid=m_axis_tvalid,
m_axis_tready=m_axis_tready,
m_axis_tlast=m_axis_tlast,
m_axis_tid=m_axis_tid,
m_axis_tdest=m_axis_tdest,
m_axis_tuser=m_axis_tuser)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
print("test 1: port 0")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x00\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1)
source_list[0].send(test_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: port 1")
current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x00\x52\x53\x54\x55' +
b'\x80\x01' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=2,
dest=1)
source_list[1].send(test_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 3: back-to-back packets, same port")
current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x00\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x00\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=3,
dest=2)
source_list[0].send(test_frame1)
source_list[0].send(test_frame2)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets, different ports")
current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x01\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2)
source_list[1].send(test_frame1)
source_list[2].send(test_frame2)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x01\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1)
source_list[1].send(test_frame1)
source_list[2].send(test_frame2)
yield clk.posedge
while s_axis_tvalid:
yield clk.posedge
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = True
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x01\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2)
source_list[1].send(test_frame1)
source_list[2].send(test_frame2)
yield clk.posedge
while s_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print(
"test 7: back-to-back packets, different ports, arbitration test")
current_test.next = 7
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x01\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x02\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=2)
source_list[1].send(test_frame1)
source_list[2].send(test_frame2)
source_list[2].send(test_frame2)
source_list[2].send(test_frame2)
source_list[2].send(test_frame2)
source_list[2].send(test_frame2)
yield clk.posedge
yield delay(800)
yield clk.posedge
source_list[1].send(test_frame1)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
AXI_DATA_WIDTH = 32
AXI_ADDR_WIDTH = 16
AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8)
AXI_ID_WIDTH = 8
AXI_MAX_BURST_LEN = 16
AXIS_DATA_WIDTH = AXI_DATA_WIDTH
AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8)
AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8)
AXIS_ID_ENABLE = 1
AXIS_ID_WIDTH = 8
AXIS_DEST_ENABLE = 0
AXIS_DEST_WIDTH = 8
AXIS_USER_ENABLE = 1
AXIS_USER_WIDTH = 1
LEN_WIDTH = 20
TAG_WIDTH = 8
ENABLE_SG = 0
ENABLE_UNALIGNED = 1
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_read_desc_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
s_axis_read_desc_len = Signal(intbv(0)[LEN_WIDTH:])
s_axis_read_desc_tag = Signal(intbv(0)[TAG_WIDTH:])
s_axis_read_desc_id = Signal(intbv(0)[AXIS_ID_WIDTH:])
s_axis_read_desc_dest = Signal(intbv(0)[AXIS_DEST_WIDTH:])
s_axis_read_desc_user = Signal(intbv(0)[AXIS_USER_WIDTH:])
s_axis_read_desc_valid = Signal(bool(0))
m_axis_read_data_tready = Signal(bool(0))
m_axi_arready = Signal(bool(0))
m_axi_rid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_rdata = Signal(intbv(0)[AXI_DATA_WIDTH:])
m_axi_rresp = Signal(intbv(0)[2:])
m_axi_rlast = Signal(bool(0))
m_axi_rvalid = Signal(bool(0))
enable = Signal(bool(0))
# Outputs
s_axis_read_desc_ready = Signal(bool(0))
m_axis_read_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:])
m_axis_read_desc_status_valid = Signal(bool(0))
m_axis_read_data_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
m_axis_read_data_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:])
m_axis_read_data_tvalid = Signal(bool(0))
m_axis_read_data_tlast = Signal(bool(0))
m_axis_read_data_tid = Signal(intbv(0)[AXIS_ID_WIDTH:])
m_axis_read_data_tdest = Signal(intbv(0)[AXIS_DEST_WIDTH:])
m_axis_read_data_tuser = Signal(intbv(0)[AXIS_USER_WIDTH:])
m_axi_arid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_araddr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
m_axi_arlen = Signal(intbv(0)[8:])
m_axi_arsize = Signal(intbv(2)[3:])
m_axi_arburst = Signal(intbv(1)[2:])
m_axi_arlock = Signal(bool(0))
m_axi_arcache = Signal(intbv(0)[4:])
m_axi_arprot = Signal(intbv(0)[3:])
m_axi_arvalid = Signal(bool(0))
m_axi_rready = Signal(bool(0))
# AXI4 RAM model
axi_ram_inst = axi.AXIRam(2**16)
axi_ram_pause = Signal(bool(False))
axi_ram_port0 = axi_ram_inst.create_port(
clk,
s_axi_arid=m_axi_arid,
s_axi_araddr=m_axi_araddr,
s_axi_arlen=m_axi_arlen,
s_axi_arsize=m_axi_arsize,
s_axi_arburst=m_axi_arburst,
s_axi_arlock=m_axi_arlock,
s_axi_arcache=m_axi_arcache,
s_axi_arprot=m_axi_arprot,
s_axi_arvalid=m_axi_arvalid,
s_axi_arready=m_axi_arready,
s_axi_rid=m_axi_rid,
s_axi_rdata=m_axi_rdata,
s_axi_rresp=m_axi_rresp,
s_axi_rlast=m_axi_rlast,
s_axi_rvalid=m_axi_rvalid,
s_axi_rready=m_axi_rready,
pause=axi_ram_pause,
name='port0'
)
# sources and sinks
read_desc_source = axis_ep.AXIStreamSource()
read_desc_source_pause = Signal(bool(False))
read_desc_source_logic = read_desc_source.create_logic(
clk,
rst,
tdata=(s_axis_read_desc_addr, s_axis_read_desc_len, s_axis_read_desc_tag, s_axis_read_desc_id, s_axis_read_desc_dest, s_axis_read_desc_user),
tvalid=s_axis_read_desc_valid,
tready=s_axis_read_desc_ready,
pause=read_desc_source_pause,
name='read_desc_source'
)
read_desc_status_sink = axis_ep.AXIStreamSink()
read_desc_status_sink_logic = read_desc_status_sink.create_logic(
clk,
rst,
tdata=(m_axis_read_desc_status_tag,),
tvalid=m_axis_read_desc_status_valid,
name='read_desc_status_sink'
)
read_data_sink = axis_ep.AXIStreamSink()
read_data_sink_pause = Signal(bool(False))
read_data_sink_logic = read_data_sink.create_logic(
clk,
rst,
tdata=m_axis_read_data_tdata,
tkeep=m_axis_read_data_tkeep,
tvalid=m_axis_read_data_tvalid,
tready=m_axis_read_data_tready,
tlast=m_axis_read_data_tlast,
tid=m_axis_read_data_tid,
tdest=m_axis_read_data_tdest,
tuser=m_axis_read_data_tuser,
pause=read_data_sink_pause,
name='read_data_sink'
)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_axis_read_desc_addr=s_axis_read_desc_addr,
s_axis_read_desc_len=s_axis_read_desc_len,
s_axis_read_desc_tag=s_axis_read_desc_tag,
s_axis_read_desc_id=s_axis_read_desc_id,
s_axis_read_desc_dest=s_axis_read_desc_dest,
s_axis_read_desc_user=s_axis_read_desc_user,
s_axis_read_desc_valid=s_axis_read_desc_valid,
s_axis_read_desc_ready=s_axis_read_desc_ready,
m_axis_read_desc_status_tag=m_axis_read_desc_status_tag,
m_axis_read_desc_status_valid=m_axis_read_desc_status_valid,
m_axis_read_data_tdata=m_axis_read_data_tdata,
m_axis_read_data_tkeep=m_axis_read_data_tkeep,
m_axis_read_data_tvalid=m_axis_read_data_tvalid,
m_axis_read_data_tready=m_axis_read_data_tready,
m_axis_read_data_tlast=m_axis_read_data_tlast,
m_axis_read_data_tid=m_axis_read_data_tid,
m_axis_read_data_tdest=m_axis_read_data_tdest,
m_axis_read_data_tuser=m_axis_read_data_tuser,
m_axi_arid=m_axi_arid,
m_axi_araddr=m_axi_araddr,
m_axi_arlen=m_axi_arlen,
m_axi_arsize=m_axi_arsize,
m_axi_arburst=m_axi_arburst,
m_axi_arlock=m_axi_arlock,
m_axi_arcache=m_axi_arcache,
m_axi_arprot=m_axi_arprot,
m_axi_arvalid=m_axi_arvalid,
m_axi_arready=m_axi_arready,
m_axi_rid=m_axi_rid,
m_axi_rdata=m_axi_rdata,
m_axi_rresp=m_axi_rresp,
m_axi_rlast=m_axi_rlast,
m_axi_rvalid=m_axi_rvalid,
m_axi_rready=m_axi_rready,
enable=enable
)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while read_desc_status_sink.empty() or read_data_sink.empty():
yield clk.posedge
def wait_pause_ram():
while read_desc_status_sink.empty() or read_data_sink.empty():
axi_ram_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
axi_ram_pause.next = False
yield clk.posedge
def wait_pause_sink():
while read_desc_status_sink.empty() or read_data_sink.empty():
read_data_sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
read_data_sink_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
cur_tag = 1
enable.next = 1
yield clk.posedge
print("test 1: read")
current_test.next = 1
addr = 0x00000000
test_data = b'\x11\x22\x33\x44'
axi_ram_inst.write_mem(addr, test_data)
data = axi_ram_inst.read_mem(addr, 32)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
read_desc_source.send([(addr, len(test_data), cur_tag, cur_tag, 0, 0)])
yield read_desc_status_sink.wait(1000)
yield read_data_sink.wait(1000)
status = read_desc_status_sink.recv()
read_data = read_data_sink.recv()
print(status)
print(read_data)
assert status.data[0][0] == cur_tag
assert read_data.data == test_data
assert read_data.id[0] == cur_tag
cur_tag = (cur_tag + 1) % 256
yield delay(100)
yield clk.posedge
print("test 2: various reads")
current_test.next = 2
for length in list(range(1,17))+[128]:
for offset in list(range(8,16))+list(range(4096-8,4096)):
for wait in wait_normal, wait_pause_ram, wait_pause_sink:
print("length %d, offset %d"% (length, offset))
#addr = length * 0x100000000 + offset * 0x10000 + offset
addr = offset
test_data = bytearray([x%256 for x in range(length)])
axi_ram_inst.write_mem(addr & 0xffff80, b'\xaa'*(len(test_data)+256))
axi_ram_inst.write_mem(addr, test_data)
data = axi_ram_inst.read_mem(addr&0xfffff0, 64)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c) for c in bytearray(data[i:i+16]))))
read_desc_source.send([(addr, len(test_data), cur_tag, cur_tag, 0, 0)])
yield wait()
status = read_desc_status_sink.recv()
read_data = read_data_sink.recv()
print(status)
print(read_data)
assert status.data[0][0] == cur_tag
assert read_data.data == test_data
assert read_data.id[0] == cur_tag
cur_tag = (cur_tag + 1) % 256
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[64:])
input_axis_tkeep = Signal(intbv(0)[8:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
output_axis_tready = Signal(bool(0))
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tkeep = Signal(intbv(0)[1:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
# DUT
dut = dut_axis_adapter_64_8(clk, rst, current_test, input_axis_tdata,
input_axis_tkeep, input_axis_tvalid,
input_axis_tready, input_axis_tlast,
input_axis_tuser, output_axis_tdata,
output_axis_tkeep, output_axis_tvalid,
output_axis_tready, output_axis_tlast,
output_axis_tuser)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while input_axis_tvalid or output_axis_tvalid:
yield clk.posedge
def wait_pause_source():
while input_axis_tvalid or output_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
def wait_pause_sink():
while input_axis_tvalid or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
for payload_len in range(1, 18):
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(payload_len)))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
assert sink_queue.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(payload_len)))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
assert sink_queue.empty()
yield delay(100)
yield clk.posedge
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(payload_len)))
test_frame1.user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
assert rx_frame.user[-1]
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
assert sink_queue.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
def bench():
# Parameters
WIDTH = 32
INITIAL_PHASE = 0
INITIAL_PHASE_STEP = 0
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_phase_tdata = Signal(intbv(0)[WIDTH:])
input_phase_tvalid = Signal(bool(0))
input_phase_step_tdata = Signal(intbv(0)[WIDTH:])
input_phase_step_tvalid = Signal(bool(0))
output_phase_tready = Signal(bool(0))
# Outputs
input_phase_tready = Signal(bool(1))
input_phase_step_tready = Signal(bool(1))
output_phase_tdata = Signal(intbv(0)[WIDTH:])
output_phase_tvalid = Signal(bool(1))
# sources and sinks
phase_source_queue = Queue()
phase_source_pause = Signal(bool(0))
phase_step_source_queue = Queue()
phase_step_source_pause = Signal(bool(0))
phase_sink_queue = Queue()
phase_sink_pause = Signal(bool(0))
phase_source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_phase_tdata,
tvalid=input_phase_tvalid,
tready=input_phase_tready,
fifo=phase_source_queue,
pause=phase_source_pause,
name='phase_source')
phase_step_source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_phase_step_tdata,
tvalid=input_phase_step_tvalid,
tready=input_phase_step_tready,
fifo=phase_step_source_queue,
pause=phase_step_source_pause,
name='phase_step_source')
phase_sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_phase_tdata,
tvalid=output_phase_tvalid,
tready=output_phase_tready,
fifo=phase_sink_queue,
pause=phase_sink_pause,
name='phase_sink')
# DUT
dut = dut_phase_accumulator(clk, rst, current_test, input_phase_tdata,
input_phase_tvalid, input_phase_tready,
input_phase_step_tdata,
input_phase_step_tvalid,
input_phase_step_tready, output_phase_tdata,
output_phase_tvalid, output_phase_tready)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
yield clk.posedge
print("test 1: initial phase")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame()
test_frame.data = [123456]
phase_source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
while not phase_sink_queue.empty():
phase_sink_queue.get(False)
yield clk.posedge
yield clk.posedge
rx_frame = phase_sink_queue.get(False)
assert rx_frame.data[0] == 123456
yield delay(100)
yield clk.posedge
print("test 2: phase step")
current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame()
test_frame1.data = [10000]
test_frame2 = axis_ep.AXIStreamFrame()
test_frame2.data = [5000]
phase_source_queue.put(test_frame1)
phase_step_source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
while not phase_sink_queue.empty():
phase_sink_queue.get(False)
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = phase_sink_queue.get(False)
assert rx_frame.data[0] == 10000
rx_frame = phase_sink_queue.get(False)
assert rx_frame.data[0] == 15000
rx_frame = phase_sink_queue.get(False)
assert rx_frame.data[0] == 20000
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
S_COUNT = 4
DATA_WIDTH = 8
TAG_ENABLE = 1
TAG_WIDTH = 16
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_tdata_list = [Signal(intbv(0)[DATA_WIDTH:]) for i in range(S_COUNT)]
s_axis_tvalid_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axis_tlast_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axis_tuser_list = [Signal(bool(0)) for i in range(S_COUNT)]
s_axis_tdata = ConcatSignal(*reversed(s_axis_tdata_list))
s_axis_tvalid = ConcatSignal(*reversed(s_axis_tvalid_list))
s_axis_tlast = ConcatSignal(*reversed(s_axis_tlast_list))
s_axis_tuser = ConcatSignal(*reversed(s_axis_tuser_list))
m_axis_tready = Signal(bool(0))
tag = Signal(intbv(0)[TAG_WIDTH:])
# Outputs
s_axis_tready = Signal(intbv(0)[S_COUNT:])
s_axis_tready_list = [s_axis_tready(i) for i in range(S_COUNT)]
m_axis_tdata = Signal(intbv(0)[8:])
m_axis_tvalid = Signal(bool(0))
m_axis_tlast = Signal(bool(0))
m_axis_tuser = Signal(bool(0))
busy = Signal(bool(0))
# sources and sinks
source_pause_list = []
source_list = []
source_logic_list = []
sink_pause = Signal(bool(0))
for k in range(S_COUNT):
s = axis_ep.AXIStreamSource()
p = Signal(bool(0))
source_list.append(s)
source_pause_list.append(p)
source_logic_list.append(
s.create_logic(clk,
rst,
tdata=s_axis_tdata_list[k],
tvalid=s_axis_tvalid_list[k],
tready=s_axis_tready_list[k],
tlast=s_axis_tlast_list[k],
tuser=s_axis_tuser_list[k],
pause=p,
name='source_%d' % k))
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(clk,
rst,
tdata=m_axis_tdata,
tvalid=m_axis_tvalid,
tready=m_axis_tready,
tlast=m_axis_tlast,
tuser=m_axis_tuser,
pause=sink_pause,
name='sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_axis_tdata=s_axis_tdata,
s_axis_tvalid=s_axis_tvalid,
s_axis_tready=s_axis_tready,
s_axis_tlast=s_axis_tlast,
s_axis_tuser=s_axis_tuser,
m_axis_tdata=m_axis_tdata,
m_axis_tvalid=m_axis_tvalid,
m_axis_tready=m_axis_tready,
m_axis_tlast=m_axis_tlast,
m_axis_tuser=m_axis_tuser,
tag=tag,
busy=busy)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
tag.next = 1
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame_0 = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_list[0].send(test_frame_0)
source_list[1].send(test_frame_1)
source_list[2].send(test_frame_2)
source_list[3].send(test_frame_3)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
yield delay(100)
yield clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame_0 = axis_ep.AXIStreamFrame(b'\x00' + bytearray(range(256)) +
b'\x00')
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_list[0].send(test_frame_0)
source_list[1].send(test_frame_1)
source_list[2].send(test_frame_2)
source_list[3].send(test_frame_3)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
yield delay(100)
yield clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame_0 = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_list[0].send(test_frame_0)
source_list[1].send(test_frame_1)
source_list[2].send(test_frame_2)
source_list[3].send(test_frame_3)
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause_list[1].next = True
yield delay(32)
yield clk.posedge
source_pause_list[1].next = False
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame_0a = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_0b = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1a = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_1b = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2a = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_list[0].send(test_frame_0a)
source_list[0].send(test_frame_0b)
source_list[1].send(test_frame_1a)
source_list[1].send(test_frame_1b)
source_list[2].send(test_frame_2a)
source_list[2].send(test_frame_2b)
source_list[3].send(test_frame_3a)
source_list[3].send(test_frame_3b)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
yield delay(100)
yield clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame_0a = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_0b = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1a = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_1b = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2a = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_list[0].send(test_frame_0a)
source_list[0].send(test_frame_0b)
source_list[1].send(test_frame_1a)
source_list[1].send(test_frame_1b)
source_list[2].send(test_frame_2a)
source_list[2].send(test_frame_2b)
source_list[3].send(test_frame_3a)
source_list[3].send(test_frame_3b)
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
yield clk.posedge
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = True
yield clk.posedge
for k in range(S_COUNT):
source_pause_list[k].next = False
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
yield delay(100)
yield clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame_0a = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_0b = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1a = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_1b = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2a = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_list[0].send(test_frame_0a)
source_list[0].send(test_frame_0b)
source_list[1].send(test_frame_1a)
source_list[1].send(test_frame_1b)
source_list[2].send(test_frame_2a)
source_list[2].send(test_frame_2b)
source_list[3].send(test_frame_3a)
source_list[3].send(test_frame_3b)
yield clk.posedge
while s_axis_tvalid or m_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
yield delay(100)
yield clk.posedge
print("test 7: tuser assert")
current_test.next = 7
test_frame_0 = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_0.last_cycle_user = 1
source_list[0].send(test_frame_0)
source_list[1].send(test_frame_1)
source_list[2].send(test_frame_2)
source_list[3].send(test_frame_3)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'<H', tag
) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
assert rx_frame.last_cycle_user
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
output_eth_payload_tready = Signal(bool(0))
output_eth_hdr_ready = Signal(bool(0))
# Outputs
input_axis_tready = Signal(bool(0))
output_eth_hdr_valid = Signal(bool(0))
output_eth_dest_mac = Signal(intbv(0)[48:])
output_eth_src_mac = Signal(intbv(0)[48:])
output_eth_type = Signal(intbv(0)[16:])
output_eth_payload_tdata = Signal(intbv(0)[8:])
output_eth_payload_tvalid = Signal(bool(0))
output_eth_payload_tlast = Signal(bool(0))
output_eth_payload_tuser = Signal(bool(0))
busy = Signal(bool(0))
error_header_early_termination = Signal(bool(0))
# sources and sinks
source_pause = Signal(bool(0))
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource()
source_logic = source.create_logic(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source')
sink = eth_ep.EthFrameSink()
sink_logic = sink.create_logic(
clk,
rst,
eth_hdr_ready=output_eth_hdr_ready,
eth_hdr_valid=output_eth_hdr_valid,
eth_dest_mac=output_eth_dest_mac,
eth_src_mac=output_eth_src_mac,
eth_type=output_eth_type,
eth_payload_tdata=output_eth_payload_tdata,
eth_payload_tvalid=output_eth_payload_tvalid,
eth_payload_tready=output_eth_payload_tready,
eth_payload_tlast=output_eth_payload_tlast,
eth_payload_tuser=output_eth_payload_tuser,
pause=sink_pause,
name='sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_eth_hdr_valid=output_eth_hdr_valid,
output_eth_hdr_ready=output_eth_hdr_ready,
output_eth_dest_mac=output_eth_dest_mac,
output_eth_src_mac=output_eth_src_mac,
output_eth_type=output_eth_type,
output_eth_payload_tdata=output_eth_payload_tdata,
output_eth_payload_tvalid=output_eth_payload_tvalid,
output_eth_payload_tready=output_eth_payload_tready,
output_eth_payload_tlast=output_eth_payload_tlast,
output_eth_payload_tuser=output_eth_payload_tuser,
busy=busy,
error_header_early_termination=error_header_early_termination)
@always(delay(4))
def clkgen():
clk.next = not clk
error_header_early_termination_asserted = Signal(bool(0))
@always(clk.posedge)
def monitor():
if (error_header_early_termination):
error_header_early_termination_asserted.next = 1
def wait_normal():
while input_axis_tvalid or output_eth_payload_tvalid:
yield clk.posedge
def wait_pause_source():
while input_axis_tvalid or output_eth_payload_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
def wait_pause_sink():
while input_axis_tvalid or output_eth_payload_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
for payload_len in range(1, 18):
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(payload_len))
axis_frame = test_frame.build_axis()
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(axis_frame)
yield clk.posedge
yield clk.posedge
yield wait()
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame
assert sink.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(payload_len))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(payload_len))
axis_frame1 = test_frame1.build_axis()
axis_frame2 = test_frame2.build_axis()
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(axis_frame1)
source.send(axis_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert sink.empty()
yield delay(100)
yield clk.posedge
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(payload_len))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(payload_len))
axis_frame1 = test_frame1.build_axis()
axis_frame2 = test_frame2.build_axis()
axis_frame1.user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(axis_frame1)
source.send(axis_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame1
assert rx_frame.payload.user[-1]
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert sink.empty()
yield delay(100)
for length in range(1, 15):
yield clk.posedge
print("test 4: truncated packet, length %d" % length)
current_test.next = 4
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(16))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(16))
axis_frame1 = test_frame1.build_axis()
axis_frame2 = test_frame2.build_axis()
axis_frame1.data = axis_frame1.data[:length]
for wait in wait_normal, wait_pause_source, wait_pause_sink:
error_header_early_termination_asserted.next = 0
source.send(axis_frame1)
source.send(axis_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield sink.wait()
rx_frame = sink.recv()
assert error_header_early_termination_asserted
assert rx_frame == test_frame2
assert sink.empty()
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
output_axis_tready = Signal(bool(0))
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
count = Signal(intbv(0)[3:])
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
# DUT
dut = dut_axis_srl_fifo(clk, rst, current_test, input_axis_tdata,
input_axis_tvalid, input_axis_tready,
input_axis_tlast, input_axis_tuser,
output_axis_tdata, output_axis_tvalid,
output_axis_tready, output_axis_tlast,
output_axis_tuser, count)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source_queue.put(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source_queue.put(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source_queue.put(test_frame)
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while input_axis_tvalid or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 7: tuser assert")
current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame.user = 1
source_queue.put(test_frame)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
assert rx_frame.user[-1]
yield delay(100)
yield clk.posedge
print("test 8: initial sink pause")
current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = 0
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 9: initial sink pause, reset")
current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
sink_pause.next = 0
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
assert sink_queue.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
def bench():
# Parameters
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH > 8)
KEEP_WIDTH = (DATA_WIDTH / 8)
LEN_WIDTH = 16
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
monitor_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
monitor_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
monitor_axis_tvalid = Signal(bool(0))
monitor_axis_tready = Signal(bool(0))
monitor_axis_tlast = Signal(bool(0))
# Outputs
frame_len = Signal(intbv(0)[LEN_WIDTH:])
frame_len_valid = Signal(bool(0))
# sources and sinks
source_pause = Signal(bool(0))
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource()
source_logic = source.create_logic(clk,
rst,
tdata=monitor_axis_tdata,
tkeep=monitor_axis_tkeep,
tvalid=monitor_axis_tvalid,
tready=monitor_axis_tready,
tlast=monitor_axis_tlast,
pause=source_pause,
name='source')
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(clk,
rst,
tdata=monitor_axis_tdata,
tkeep=monitor_axis_tkeep,
tvalid=monitor_axis_tvalid,
tready=monitor_axis_tready,
tlast=monitor_axis_tlast,
pause=sink_pause,
name='sink')
frame_len_sink = axis_ep.AXIStreamSink()
frame_len_sink_logic = frame_len_sink.create_logic(clk,
rst,
tdata=frame_len,
tvalid=frame_len_valid,
name='frame_len_sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
monitor_axis_tkeep=monitor_axis_tkeep,
monitor_axis_tvalid=monitor_axis_tvalid,
monitor_axis_tready=monitor_axis_tready,
monitor_axis_tlast=monitor_axis_tlast,
frame_len=frame_len,
frame_len_valid=frame_len_valid)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source.send(test_frame)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 4: longer packet")
current_test.next = 4
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source.send(test_frame)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 5: test packet with pauses")
current_test.next = 5
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
bytearray(range(256)))
source.send(test_frame)
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
while monitor_axis_tvalid:
yield clk.posedge
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 6: back-to-back packets")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 7: alternate pause source")
current_test.next = 7
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
source_pause.next = True
yield clk.posedge
source_pause.next = False
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 8: alternate pause sink")
current_test.next = 8
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
while monitor_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
yield clk.posedge
print("test 9: various length packets")
current_test.next = 9
lens = [32, 48, 96, 128, 256]
test_frame = []
for i in lens:
test_frame.append(
axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' + bytearray(range(i))))
for f in test_frame:
source.send(f)
yield clk.posedge
while monitor_axis_tvalid:
yield clk.posedge
for i in lens:
yield sink.wait()
f = sink.recv()
yield frame_len_sink.wait()
l = frame_len_sink.recv()
assert len(f.data) == l.data[0]
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
APPEND_ZERO = 1
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
output_axis_tready = Signal(bool(0))
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
# sources and sinks
source_pause = Signal(bool(0))
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource()
source_logic = source.create_logic(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source')
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
i = 4
while i > 0:
i = max(0, i - 1)
if input_axis_tvalid or output_axis_tvalid or not source.empty():
i = 4
yield clk.posedge
def wait_pause_source():
i = 2
while i > 0:
i = max(0, i - 1)
if input_axis_tvalid or output_axis_tvalid or not source.empty():
i = 2
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
def wait_pause_sink():
i = 2
while i > 0:
i = max(0, i - 1)
if input_axis_tvalid or output_axis_tvalid or not source.empty():
i = 2
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
for payload_len in list(range(1, 33)) + list(range(253, 259)) + [512]:
gen = prbs31()
for block in [
bytearray([0] * payload_len),
bytearray([k % 255 + 1 for k in range(payload_len)]),
b'\x00' +
bytearray([k % 255 + 1
for k in range(payload_len)]) + b'\x00',
bytearray([next(gen) for i in range(payload_len)])
]:
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
enc = cobs_encode(block)
test_frame = axis_ep.AXIStreamFrame(block)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == enc + b'\x00'
assert cobs_decode(rx_frame.data[:-1]) == block
assert not rx_frame.user[-1]
assert sink.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(block)
test_frame2 = axis_ep.AXIStreamFrame(block)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == enc + b'\x00'
assert cobs_decode(rx_frame.data[:-1]) == block
assert not rx_frame.user[-1]
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == enc + b'\x00'
assert cobs_decode(rx_frame.data[:-1]) == block
assert not rx_frame.user[-1]
assert sink.empty()
yield delay(100)
yield clk.posedge
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(block)
test_frame2 = axis_ep.AXIStreamFrame(block)
test_frame1.user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert cobs_decode(rx_frame.data[:-1]) == None
assert rx_frame.user[-1]
rx_frame = sink.recv()
assert cobs_decode(enc) == block
assert rx_frame.data == enc + b'\x00'
assert cobs_decode(rx_frame.data[:-1]) == block
assert not rx_frame.user[-1]
assert sink.empty()
yield delay(100)
raise StopSimulation
return dut, source_logic, sink_logic, clkgen, check
def bench():
# Parameters
CACHE_ADDR_WIDTH = 2
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
query_request_valid = Signal(bool(0))
query_request_ip = Signal(intbv(0)[32:])
query_response_ready = Signal(bool(0))
write_request_valid = Signal(bool(0))
write_request_ip = Signal(intbv(0)[32:])
write_request_mac = Signal(intbv(0)[48:])
clear_cache = Signal(bool(0))
# Outputs
query_request_ready = Signal(bool(0))
query_response_valid = Signal(bool(0))
query_response_error = Signal(bool(0))
query_response_mac = Signal(intbv(0)[48:])
write_request_ready = Signal(bool(0))
# sources and sinks
query_request_source_pause = Signal(bool(0))
query_response_sink_pause = Signal(bool(0))
write_request_source_pause = Signal(bool(0))
query_request_source = axis_ep.AXIStreamSource()
query_request_source_logic = query_request_source.create_logic(
clk,
rst,
tdata=(query_request_ip, ),
tvalid=query_request_valid,
tready=query_request_ready,
pause=query_request_source_pause,
name='query_request_source')
query_response_sink = axis_ep.AXIStreamSink()
query_response_sink_logic = query_response_sink.create_logic(
clk,
rst,
tdata=(query_response_mac, ),
tvalid=query_response_valid,
tready=query_response_ready,
tuser=query_response_error,
pause=query_response_sink_pause,
name='query_response_sink')
write_request_source = axis_ep.AXIStreamSource()
write_request_source_logic = write_request_source.create_logic(
clk,
rst,
tdata=(write_request_ip, write_request_mac),
tvalid=write_request_valid,
tready=write_request_ready,
pause=write_request_source_pause,
name='write_request_source')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
query_request_valid=query_request_valid,
query_request_ready=query_request_ready,
query_request_ip=query_request_ip,
query_response_valid=query_response_valid,
query_response_ready=query_response_ready,
query_response_error=query_response_error,
query_response_mac=query_response_mac,
write_request_valid=write_request_valid,
write_request_ready=write_request_ready,
write_request_ip=write_request_ip,
write_request_mac=write_request_mac,
clear_cache=clear_cache)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: write")
current_test.next = 1
yield clk.posedge
write_request_source.send([(0xc0a80111, 0x0000c0a80111)])
write_request_source.send([(0xc0a80112, 0x0000c0a80112)])
yield delay(100)
while not write_request_source.empty():
yield clk.posedge
yield delay(100)
yield clk.posedge
print("test 2: read")
current_test.next = 2
yield clk.posedge
query_request_source.send([(0xc0a80111, )])
query_request_source.send([(0xc0a80112, )])
query_request_source.send([(0xc0a80113, )])
yield query_response_sink.wait()
resp = query_response_sink.recv()
assert resp.data[0][0] == 0x0000c0a80111
assert not resp.user[0]
yield query_response_sink.wait()
resp = query_response_sink.recv()
assert resp.data[0][0] == 0x0000c0a80112
assert not resp.user[0]
# not in cache; was not written
yield query_response_sink.wait()
resp = query_response_sink.recv()
assert resp.user[0]
yield delay(100)
yield clk.posedge
print("test 3: write more")
current_test.next = 3
yield clk.posedge
write_request_source.send([(0xc0a80121, 0x0000c0a80121)])
write_request_source.send([(0xc0a80122, 0x0000c0a80122)])
# overwrites 0xc0a80112
write_request_source.send([(0xc0a80123, 0x0000c0a80123)])
while not write_request_source.empty():
yield clk.posedge
yield delay(100)
yield clk.posedge
print("test 4: read more")
current_test.next = 4
yield clk.posedge
query_request_source.send([(0xc0a80111, )])
yield query_response_sink.wait()
resp = query_response_sink.recv()
assert resp.data[0][0] == 0x0000c0a80111
assert not resp.user[0]
# not in cache; was overwritten
yield clk.posedge
query_request_source.send([(0xc0a80112, )])
yield query_response_sink.wait()
resp = query_response_sink.recv()
assert resp.user[0]
yield clk.posedge
query_request_source.send([(0xc0a80121, )])
yield query_response_sink.wait()
resp = query_response_sink.recv()
assert resp.data[0][0] == 0x0000c0a80121
assert not resp.user[0]
yield clk.posedge
query_request_source.send([(0xc0a80122, )])
yield query_response_sink.wait()
resp = query_response_sink.recv()
assert resp.data[0][0] == 0x0000c0a80122
assert not resp.user[0]
yield clk.posedge
query_request_source.send([(0xc0a80123, )])
yield query_response_sink.wait()
resp = query_response_sink.recv()
assert resp.data[0][0] == 0x0000c0a80123
assert not resp.user[0]
yield delay(100)
yield clk.posedge
print("test 5: Test overwrite")
current_test.next = 5
yield clk.posedge
write_request_source.send([(0xc0a80123, 0x0000c0a80164)])
while not write_request_source.empty():
yield clk.posedge
# read values
yield clk.posedge
query_request_source.send([(0xc0a80111, )])
yield query_response_sink.wait()
resp = query_response_sink.recv()
assert resp.data[0][0] == 0x0000c0a80111
assert not resp.user[0]
# not in cache; was overwritten
yield clk.posedge
query_request_source.send([(0xc0a80112, )])
yield query_response_sink.wait()
resp = query_response_sink.recv()
assert resp.user[0]
yield clk.posedge
query_request_source.send([(0xc0a80121, )])
yield query_response_sink.wait()
resp = query_response_sink.recv()
assert resp.data[0][0] == 0x0000c0a80121
assert not resp.user[0]
yield clk.posedge
query_request_source.send([(0xc0a80122, )])
yield query_response_sink.wait()
resp = query_response_sink.recv()
assert resp.data[0][0] == 0x0000c0a80122
assert not resp.user[0]
yield clk.posedge
query_request_source.send([(0xc0a80123, )])
yield query_response_sink.wait()
resp = query_response_sink.recv()
assert resp.data[0][0] == 0x0000c0a80164
assert not resp.user[0]
yield delay(100)
yield clk.posedge
print("test 6: clear cache")
current_test.next = 6
yield clk.posedge
clear_cache.next = True
yield clk.posedge
clear_cache.next = False
yield delay(100)
yield clk.posedge
query_request_source.send([(0xc0a80111, )])
yield query_response_sink.wait()
resp = query_response_sink.recv()
assert resp.user[0]
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
ADDR_WIDTH = 6
DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH > 8)
KEEP_WIDTH = (DATA_WIDTH / 8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
USER_BAD_FRAME_VALUE = 1
USER_BAD_FRAME_MASK = 1
DROP_BAD_FRAME = 1
DROP_WHEN_FULL = 0
# Inputs
async_rst = Signal(bool(0))
input_clk = Signal(bool(0))
output_clk = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0))
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
input_status_overflow = Signal(bool(0))
input_status_bad_frame = Signal(bool(0))
input_status_good_frame = Signal(bool(0))
output_status_overflow = Signal(bool(0))
output_status_bad_frame = Signal(bool(0))
output_status_good_frame = Signal(bool(0))
# sources and sinks
source_pause = Signal(bool(0))
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource()
source_logic = source.create_logic(input_clk,
async_rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser,
pause=source_pause,
name='source')
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(output_clk,
async_rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
async_rst=async_rst,
input_clk=input_clk,
output_clk=output_clk,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser,
input_status_overflow=input_status_overflow,
input_status_bad_frame=input_status_bad_frame,
input_status_good_frame=input_status_good_frame,
output_status_overflow=output_status_overflow,
output_status_bad_frame=output_status_bad_frame,
output_status_good_frame=output_status_good_frame)
@always(delay(4))
def input_clkgen():
input_clk.next = not input_clk
@always(delay(5))
def output_clkgen():
output_clk.next = not output_clk
input_status_overflow_asserted = Signal(bool(0))
input_status_bad_frame_asserted = Signal(bool(0))
input_status_good_frame_asserted = Signal(bool(0))
output_status_overflow_asserted = Signal(bool(0))
output_status_bad_frame_asserted = Signal(bool(0))
output_status_good_frame_asserted = Signal(bool(0))
@always(input_clk.posedge)
def monitor_1():
if (input_status_overflow):
input_status_overflow_asserted.next = 1
if (input_status_bad_frame):
input_status_bad_frame_asserted.next = 1
if (input_status_good_frame):
input_status_good_frame_asserted.next = 1
@always(output_clk.posedge)
def monitor_2():
if (output_status_overflow):
output_status_overflow_asserted.next = 1
if (output_status_bad_frame):
output_status_bad_frame_asserted.next = 1
if (output_status_good_frame):
output_status_good_frame_asserted.next = 1
@instance
def check():
yield delay(100)
yield input_clk.posedge
async_rst.next = 1
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
async_rst.next = 0
yield input_clk.posedge
yield delay(100)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=1)
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source.send(test_frame)
yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
yield input_clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' + bytearray(range(256)),
id=2,
dest=1)
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source.send(test_frame)
yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield input_clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' + bytearray(range(256)),
id=3,
dest=1)
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source.send(test_frame)
yield input_clk.posedge
yield delay(64)
yield input_clk.posedge
source_pause.next = True
yield delay(32)
yield input_clk.posedge
source_pause.next = False
yield delay(64)
yield output_clk.posedge
sink_pause.next = True
yield delay(32)
yield output_clk.posedge
sink_pause.next = False
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
yield input_clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=4,
dest=2)
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
yield input_clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=5,
dest=2)
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
while input_axis_tvalid or output_axis_tvalid:
source_pause.next = True
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
source_pause.next = False
yield input_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
if output_axis_tvalid:
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
yield input_clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=1,
dest=6)
test_frame2 = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=6,
dest=2)
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source.send(test_frame1)
source.send(test_frame2)
yield input_clk.posedge
while input_axis_tvalid or output_axis_tvalid:
sink_pause.next = True
yield output_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
sink_pause.next = False
yield output_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame1
rx_frame = sink.recv()
assert rx_frame == test_frame2
assert not input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert output_status_good_frame_asserted
yield delay(100)
yield input_clk.posedge
print("test 7: tuser assert")
current_test.next = 7
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10',
id=7,
dest=1,
last_cycle_user=1)
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source.send(test_frame)
yield input_clk.posedge
yield delay(1000)
assert sink.empty()
assert not input_status_overflow_asserted
assert input_status_bad_frame_asserted
assert not input_status_good_frame_asserted
assert not output_status_overflow_asserted
assert output_status_bad_frame_asserted
assert not output_status_good_frame_asserted
yield delay(100)
yield input_clk.posedge
print("test 8: single packet overflow")
current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' + bytearray(range(256)) * 2,
id=8,
dest=1)
input_status_overflow_asserted.next = 0
input_status_bad_frame_asserted.next = 0
input_status_good_frame_asserted.next = 0
output_status_overflow_asserted.next = 0
output_status_bad_frame_asserted.next = 0
output_status_good_frame_asserted.next = 0
source.send(test_frame)
yield input_clk.posedge
yield delay(10000)
assert sink.empty()
assert input_status_overflow_asserted
assert not input_status_bad_frame_asserted
assert not input_status_good_frame_asserted
assert output_status_overflow_asserted
assert not output_status_bad_frame_asserted
assert not output_status_good_frame_asserted
yield delay(100)
yield input_clk.posedge
print("test 9: initial sink pause")
current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)), id=9, dest=1)
sink_pause.next = 1
source.send(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
sink_pause.next = 0
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = sink.recv()
assert rx_frame == test_frame
yield delay(100)
yield input_clk.posedge
print("test 10: initial sink pause, assert reset")
current_test.next = 10
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)),
id=10,
dest=1)
sink_pause.next = 1
source.send(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
async_rst.next = 1
yield input_clk.posedge
async_rst.next = 0
sink_pause.next = 0
yield delay(100)
yield output_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
assert sink.empty()
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
ENABLE_PADDING = 1
MIN_FRAME_LENGTH = 64
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_tdata = Signal(intbv(0)[8:])
s_axis_tvalid = Signal(bool(0))
s_axis_tlast = Signal(bool(0))
s_axis_tuser = Signal(bool(0))
clk_enable = Signal(bool(1))
mii_select = Signal(bool(0))
ifg_delay = Signal(intbv(0)[8:])
# Outputs
s_axis_tready = Signal(bool(0))
gmii_txd = Signal(intbv(0)[8:])
gmii_tx_en = Signal(bool(0))
gmii_tx_er = Signal(bool(0))
start_packet = Signal(bool(0))
# sources and sinks
source_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource()
source_logic = source.create_logic(
clk,
rst,
tdata=s_axis_tdata,
tvalid=s_axis_tvalid,
tready=s_axis_tready,
tlast=s_axis_tlast,
tuser=s_axis_tuser,
pause=source_pause,
name='source'
)
sink = gmii_ep.GMIISink()
sink_logic = sink.create_logic(
clk,
rst,
rxd=gmii_txd,
rx_dv=gmii_tx_en,
rx_er=gmii_tx_er,
clk_enable=clk_enable,
mii_select=mii_select,
name='sink'
)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_axis_tdata=s_axis_tdata,
s_axis_tvalid=s_axis_tvalid,
s_axis_tready=s_axis_tready,
s_axis_tlast=s_axis_tlast,
s_axis_tuser=s_axis_tuser,
gmii_txd=gmii_txd,
gmii_tx_en=gmii_tx_en,
gmii_tx_er=gmii_tx_er,
clk_enable=clk_enable,
mii_select=mii_select,
ifg_delay=ifg_delay,
start_packet=start_packet
)
@always(delay(4))
def clkgen():
clk.next = not clk
clk_enable_rate = Signal(int(1))
clk_enable_div = Signal(int(0))
@always(clk.posedge)
def clk_enable_gen():
if clk_enable_div.next > 0:
clk_enable.next = 0
clk_enable_div.next = clk_enable_div - 1
else:
clk_enable.next = 1
clk_enable_div.next = clk_enable_rate - 1
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
ifg_delay.next = 12
# testbench stimulus
for rate, mii in [(1, 0), (10, 0), (5, 1)]:
clk_enable_rate.next = rate
mii_select.next = mii
yield delay(100)
for payload_len in list(range(1,18))+list(range(64,82)):
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(payload_len))
test_frame.update_fcs()
axis_frame = test_frame.build_axis()
source.send(axis_frame)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == max(payload_len, 46)
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame.eth_src_mac
assert eth_frame.eth_type == test_frame.eth_type
assert eth_frame.payload.data.index(test_frame.payload.data) == 0
assert sink.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(payload_len))
test_frame1.update_fcs()
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(payload_len))
test_frame2.update_fcs()
axis_frame1 = test_frame1.build_axis()
axis_frame2 = test_frame2.build_axis()
source.send(axis_frame1)
source.send(axis_frame2)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == max(payload_len, 46)
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame1.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame1.eth_src_mac
assert eth_frame.eth_type == test_frame1.eth_type
assert eth_frame.payload.data.index(test_frame1.payload.data) == 0
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == max(payload_len, 46)
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame2.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame2.eth_src_mac
assert eth_frame.eth_type == test_frame2.eth_type
assert eth_frame.payload.data.index(test_frame2.payload.data) == 0
assert sink.empty()
yield delay(100)
yield clk.posedge
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(payload_len))
test_frame1.update_fcs()
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(payload_len))
test_frame2.update_fcs()
axis_frame1 = test_frame1.build_axis()
axis_frame2 = test_frame2.build_axis()
axis_frame1.user = 1
source.send(axis_frame1)
source.send(axis_frame2)
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
assert rx_frame.error[-1]
# bad packet
yield sink.wait()
rx_frame = sink.recv()
assert rx_frame.data[0:8] == bytearray(b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == max(payload_len, 46)
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame2.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame2.eth_src_mac
assert eth_frame.eth_type == test_frame2.eth_type
assert eth_frame.payload.data.index(test_frame2.payload.data) == 0
assert sink.empty()
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH > 8)
KEEP_WIDTH = (DATA_WIDTH / 8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
FRAME_FIFO_ADDR_WIDTH = 12
HEADER_FIFO_ADDR_WIDTH = 3
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_hdr_ready = Signal(bool(0))
output_axis_tready = Signal(bool(0))
length_min = Signal(intbv(0)[16:])
length_max = Signal(intbv(0)[16:])
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_hdr_valid = Signal(bool(0))
output_axis_hdr_pad = Signal(bool(0))
output_axis_hdr_truncate = Signal(bool(0))
output_axis_hdr_length = Signal(intbv(0)[16:])
output_axis_hdr_original_length = Signal(intbv(0)[16:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks
source_pause = Signal(bool(0))
sink_pause = Signal(bool(0))
hdr_sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource()
source_logic = source.create_logic(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser,
pause=source_pause,
name='source')
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink')
hdr_sink = axis_ep.AXIStreamSink()
hdr_sink_logic = hdr_sink.create_logic(
clk,
rst,
tdata=(output_axis_hdr_pad, output_axis_hdr_truncate,
output_axis_hdr_length, output_axis_hdr_original_length),
tvalid=output_axis_hdr_valid,
tready=output_axis_hdr_ready,
pause=hdr_sink_pause,
name='hdr_sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser,
output_axis_hdr_valid=output_axis_hdr_valid,
output_axis_hdr_ready=output_axis_hdr_ready,
output_axis_hdr_pad=output_axis_hdr_pad,
output_axis_hdr_truncate=output_axis_hdr_truncate,
output_axis_hdr_length=output_axis_hdr_length,
output_axis_hdr_original_length=output_axis_hdr_original_length,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser,
length_min=length_min,
length_max=length_max)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while input_axis_tvalid or output_axis_tvalid:
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
length_min.next = 1
length_max.next = 20
for lmax in range(1, 6):
for lmin in range(0, lmax + 1):
length_min.next = lmin
length_max.next = lmax
for payload_len in range(1, 6):
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(bytearray(
range(payload_len)),
id=1,
dest=1)
for wait in wait_normal, :
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield wait()
yield sink.wait()
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame.data[:lm]
yield hdr_sink.wait()
hdr = hdr_sink.recv()
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert sink.empty()
assert hdr_sink.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" %
payload_len)
current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(bytearray(
range(payload_len)),
id=2,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(
range(payload_len)),
id=2,
dest=2)
for wait in wait_normal, :
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield sink.wait()
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
yield hdr_sink.wait()
hdr = hdr_sink.recv()
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
yield sink.wait()
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
yield hdr_sink.wait()
hdr = hdr_sink.recv()
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert sink.empty()
assert hdr_sink.empty()
yield delay(100)
yield clk.posedge
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(bytearray(
range(payload_len)),
id=3,
dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(
range(payload_len)),
id=3,
dest=2)
test_frame1.last_cycle_user = 1
for wait in wait_normal, :
source.send(test_frame1)
source.send(test_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield sink.wait()
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame1.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
yield hdr_sink.wait()
hdr = hdr_sink.recv()
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert rx_frame.last_cycle_user
yield sink.wait()
rx_frame = sink.recv()
lrx = len(rx_frame.data)
lt = len(test_frame2.data)
lm = min(lrx, lt)
assert lrx >= lmin
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame2.data[:lm]
yield hdr_sink.wait()
hdr = hdr_sink.recv()
assert hdr.data[0][0] == (lt < lmin)
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert sink.empty()
assert hdr_sink.empty()
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
AXIS_PCIE_DATA_WIDTH = 64
AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH / 32)
AXIS_PCIE_RC_USER_WIDTH = 75
AXIS_PCIE_RQ_USER_WIDTH = 60
RQ_SEQ_NUM_WIDTH = 4 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 6
RQ_SEQ_NUM_ENABLE = 1
AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH
AXI_ADDR_WIDTH = 64
AXI_STRB_WIDTH = (AXI_DATA_WIDTH / 8)
AXI_ID_WIDTH = 8
AXI_MAX_BURST_LEN = 256
PCIE_ADDR_WIDTH = 64
PCIE_TAG_COUNT = 64 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 256
PCIE_TAG_WIDTH = (PCIE_TAG_COUNT - 1).bit_length()
PCIE_EXT_TAG_ENABLE = 1
LEN_WIDTH = 20
TAG_WIDTH = 8
OP_TABLE_SIZE = PCIE_TAG_COUNT
TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH - 1)
TX_FC_ENABLE = 1
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_rc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
s_axis_rc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
s_axis_rc_tvalid = Signal(bool(0))
s_axis_rc_tlast = Signal(bool(0))
s_axis_rc_tuser = Signal(intbv(0)[AXIS_PCIE_RC_USER_WIDTH:])
m_axis_rq_tready = Signal(bool(0))
s_axis_rq_seq_num_0 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:])
s_axis_rq_seq_num_valid_0 = Signal(bool(0))
s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:])
s_axis_rq_seq_num_valid_1 = Signal(bool(0))
pcie_tx_fc_nph_av = Signal(intbv(0)[8:])
s_axis_read_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:])
s_axis_read_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
s_axis_read_desc_len = Signal(intbv(0)[LEN_WIDTH:])
s_axis_read_desc_tag = Signal(intbv(0)[TAG_WIDTH:])
s_axis_read_desc_valid = Signal(bool(0))
m_axi_awready = Signal(bool(0))
m_axi_wready = Signal(bool(0))
m_axi_bid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_bresp = Signal(intbv(0)[2:])
m_axi_bvalid = Signal(bool(0))
enable = Signal(bool(0))
ext_tag_enable = Signal(bool(0))
requester_id = Signal(intbv(0)[16:])
requester_id_enable = Signal(bool(0))
max_read_request_size = Signal(intbv(0)[3:])
# Outputs
s_axis_rc_tready = Signal(bool(0))
m_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
m_axis_rq_tvalid = Signal(bool(0))
m_axis_rq_tlast = Signal(bool(0))
m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:])
s_axis_read_desc_ready = Signal(bool(0))
m_axis_read_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:])
m_axis_read_desc_status_valid = Signal(bool(0))
m_axi_awid = Signal(intbv(0)[AXI_ID_WIDTH:])
m_axi_awaddr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
m_axi_awlen = Signal(intbv(0)[8:])
m_axi_awsize = Signal(intbv(3)[3:])
m_axi_awburst = Signal(intbv(1)[2:])
m_axi_awlock = Signal(bool(0))
m_axi_awcache = Signal(intbv(3)[4:])
m_axi_awprot = Signal(intbv(2)[3:])
m_axi_awvalid = Signal(bool(0))
m_axi_wdata = Signal(intbv(0)[AXI_DATA_WIDTH:])
m_axi_wstrb = Signal(intbv(0)[AXI_STRB_WIDTH:])
m_axi_wlast = Signal(bool(0))
m_axi_wvalid = Signal(bool(0))
m_axi_bready = Signal(bool(0))
status_error_cor = Signal(bool(0))
status_error_uncor = Signal(bool(0))
# Clock and Reset Interface
user_clk = Signal(bool(0))
user_reset = Signal(bool(0))
sys_clk = Signal(bool(0))
sys_reset = Signal(bool(0))
# AXI4 RAM model
axi_ram_inst = axi.AXIRam(2**16)
axi_ram_port0 = axi_ram_inst.create_port(user_clk,
s_axi_awid=m_axi_awid,
s_axi_awaddr=m_axi_awaddr,
s_axi_awlen=m_axi_awlen,
s_axi_awsize=m_axi_awsize,
s_axi_awburst=m_axi_awburst,
s_axi_awlock=m_axi_awlock,
s_axi_awcache=m_axi_awcache,
s_axi_awprot=m_axi_awprot,
s_axi_awvalid=m_axi_awvalid,
s_axi_awready=m_axi_awready,
s_axi_wdata=m_axi_wdata,
s_axi_wstrb=m_axi_wstrb,
s_axi_wlast=m_axi_wlast,
s_axi_wvalid=m_axi_wvalid,
s_axi_wready=m_axi_wready,
s_axi_bid=m_axi_bid,
s_axi_bresp=m_axi_bresp,
s_axi_bvalid=m_axi_bvalid,
s_axi_bready=m_axi_bready,
name='port0')
# sources and sinks
read_desc_source = axis_ep.AXIStreamSource()
read_desc_source_logic = read_desc_source.create_logic(
user_clk,
user_reset,
tdata=(s_axis_read_desc_pcie_addr, s_axis_read_desc_axi_addr,
s_axis_read_desc_len, s_axis_read_desc_tag),
tvalid=s_axis_read_desc_valid,
tready=s_axis_read_desc_ready,
name='read_desc_source')
read_desc_status_sink = axis_ep.AXIStreamSink()
read_desc_status_sink_logic = read_desc_status_sink.create_logic(
user_clk,
user_reset,
tdata=(m_axis_read_desc_status_tag, ),
tvalid=m_axis_read_desc_status_valid,
name='read_desc_status_sink')
# PCIe devices
rc = pcie.RootComplex()
mem_base, mem_data = rc.alloc_region(16 * 1024 * 1024)
dev = pcie_us.UltrascalePCIe()
dev.pcie_generation = 3
dev.pcie_link_width = 2
dev.user_clock_frequency = 256e6
rc.make_port().connect(dev)
cq_pause = Signal(bool(0))
cc_pause = Signal(bool(0))
rq_pause = Signal(bool(0))
rc_pause = Signal(bool(0))
pcie_logic = dev.create_logic(
# Completer reQuest Interface
m_axis_cq_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
m_axis_cq_tuser=Signal(intbv(0)[85:]),
m_axis_cq_tlast=Signal(bool(0)),
m_axis_cq_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
m_axis_cq_tvalid=Signal(bool(0)),
m_axis_cq_tready=Signal(bool(1)),
pcie_cq_np_req=Signal(bool(1)),
pcie_cq_np_req_count=Signal(intbv(0)[6:]),
# Completer Completion Interface
s_axis_cc_tdata=Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:]),
s_axis_cc_tuser=Signal(intbv(0)[33:]),
s_axis_cc_tlast=Signal(bool(0)),
s_axis_cc_tkeep=Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:]),
s_axis_cc_tvalid=Signal(bool(0)),
s_axis_cc_tready=Signal(bool(0)),
# Requester reQuest Interface
s_axis_rq_tdata=m_axis_rq_tdata,
s_axis_rq_tuser=m_axis_rq_tuser,
s_axis_rq_tlast=m_axis_rq_tlast,
s_axis_rq_tkeep=m_axis_rq_tkeep,
s_axis_rq_tvalid=m_axis_rq_tvalid,
s_axis_rq_tready=m_axis_rq_tready,
pcie_rq_seq_num=s_axis_rq_seq_num_0,
pcie_rq_seq_num_vld=s_axis_rq_seq_num_valid_0,
# pcie_rq_tag=pcie_rq_tag,
# pcie_rq_tag_av=pcie_rq_tag_av,
# pcie_rq_tag_vld=pcie_rq_tag_vld,
# Requester Completion Interface
m_axis_rc_tdata=s_axis_rc_tdata,
m_axis_rc_tuser=s_axis_rc_tuser,
m_axis_rc_tlast=s_axis_rc_tlast,
m_axis_rc_tkeep=s_axis_rc_tkeep,
m_axis_rc_tvalid=s_axis_rc_tvalid,
m_axis_rc_tready=s_axis_rc_tready,
# Transmit Flow Control Interface
# pcie_tfc_nph_av=pcie_tfc_nph_av,
# pcie_tfc_npd_av=pcie_tfc_npd_av,
# Configuration Flow Control Interface
#cfg_fc_ph=cfg_fc_ph,
#cfg_fc_pd=cfg_fc_pd,
cfg_fc_nph=pcie_tx_fc_nph_av,
#cfg_fc_npd=cfg_fc_npd,
#cfg_fc_cplh=cfg_fc_cplh,
#cfg_fc_cpld=cfg_fc_cpld,
cfg_fc_sel=Signal(intbv(0b100)[3:]),
# Configuration Control Interface
# cfg_hot_reset_in=cfg_hot_reset_in,
# cfg_hot_reset_out=cfg_hot_reset_out,
# cfg_config_space_enable=cfg_config_space_enable,
# cfg_per_function_update_done=cfg_per_function_update_done,
# cfg_per_function_number=cfg_per_function_number,
# cfg_per_function_output_request=cfg_per_function_output_request,
# cfg_dsn=cfg_dsn,
# cfg_ds_bus_number=cfg_ds_bus_number,
# cfg_ds_device_number=cfg_ds_device_number,
# cfg_ds_function_number=cfg_ds_function_number,
# cfg_power_state_change_ack=cfg_power_state_change_ack,
# cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
# cfg_err_cor_in=cfg_err_cor_in,
# cfg_err_uncor_in=cfg_err_uncor_in,
# cfg_flr_done=cfg_flr_done,
# cfg_vf_flr_done=cfg_vf_flr_done,
# cfg_flr_in_process=cfg_flr_in_process,
# cfg_vf_flr_in_process=cfg_vf_flr_in_process,
# cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
# cfg_link_training_enable=cfg_link_training_enable,
# Clock and Reset Interface
user_clk=user_clk,
user_reset=user_reset,
#user_lnk_up=user_lnk_up,
sys_clk=sys_clk,
sys_clk_gt=sys_clk,
sys_reset=sys_reset,
cq_pause=cq_pause,
cc_pause=cc_pause,
rq_pause=rq_pause,
rc_pause=rc_pause)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=user_clk,
rst=user_reset,
current_test=current_test,
s_axis_rc_tdata=s_axis_rc_tdata,
s_axis_rc_tkeep=s_axis_rc_tkeep,
s_axis_rc_tvalid=s_axis_rc_tvalid,
s_axis_rc_tready=s_axis_rc_tready,
s_axis_rc_tlast=s_axis_rc_tlast,
s_axis_rc_tuser=s_axis_rc_tuser,
m_axis_rq_tdata=m_axis_rq_tdata,
m_axis_rq_tkeep=m_axis_rq_tkeep,
m_axis_rq_tvalid=m_axis_rq_tvalid,
m_axis_rq_tready=m_axis_rq_tready,
m_axis_rq_tlast=m_axis_rq_tlast,
m_axis_rq_tuser=m_axis_rq_tuser,
s_axis_rq_seq_num_0=s_axis_rq_seq_num_0,
s_axis_rq_seq_num_valid_0=s_axis_rq_seq_num_valid_0,
s_axis_rq_seq_num_1=s_axis_rq_seq_num_1,
s_axis_rq_seq_num_valid_1=s_axis_rq_seq_num_valid_1,
pcie_tx_fc_nph_av=pcie_tx_fc_nph_av,
s_axis_read_desc_pcie_addr=s_axis_read_desc_pcie_addr,
s_axis_read_desc_axi_addr=s_axis_read_desc_axi_addr,
s_axis_read_desc_len=s_axis_read_desc_len,
s_axis_read_desc_tag=s_axis_read_desc_tag,
s_axis_read_desc_valid=s_axis_read_desc_valid,
s_axis_read_desc_ready=s_axis_read_desc_ready,
m_axis_read_desc_status_tag=m_axis_read_desc_status_tag,
m_axis_read_desc_status_valid=m_axis_read_desc_status_valid,
m_axi_awid=m_axi_awid,
m_axi_awaddr=m_axi_awaddr,
m_axi_awlen=m_axi_awlen,
m_axi_awsize=m_axi_awsize,
m_axi_awburst=m_axi_awburst,
m_axi_awlock=m_axi_awlock,
m_axi_awcache=m_axi_awcache,
m_axi_awprot=m_axi_awprot,
m_axi_awvalid=m_axi_awvalid,
m_axi_awready=m_axi_awready,
m_axi_wdata=m_axi_wdata,
m_axi_wstrb=m_axi_wstrb,
m_axi_wlast=m_axi_wlast,
m_axi_wvalid=m_axi_wvalid,
m_axi_wready=m_axi_wready,
m_axi_bid=m_axi_bid,
m_axi_bresp=m_axi_bresp,
m_axi_bvalid=m_axi_bvalid,
m_axi_bready=m_axi_bready,
enable=enable,
ext_tag_enable=ext_tag_enable,
requester_id=requester_id,
requester_id_enable=requester_id_enable,
max_read_request_size=max_read_request_size,
status_error_cor=status_error_cor,
status_error_uncor=status_error_uncor)
@always(delay(4))
def clkgen():
clk.next = not clk
@always_comb
def clk_logic():
sys_clk.next = clk
sys_reset.next = not rst
status_error_cor_asserted = Signal(bool(0))
status_error_uncor_asserted = Signal(bool(0))
@always(clk.posedge)
def monitor():
if (status_error_cor):
status_error_cor_asserted.next = 1
if (status_error_uncor):
status_error_uncor_asserted.next = 1
cq_pause_toggle = Signal(bool(0))
cc_pause_toggle = Signal(bool(0))
rq_pause_toggle = Signal(bool(0))
rc_pause_toggle = Signal(bool(0))
@instance
def pause_toggle():
while True:
if (cq_pause_toggle or cc_pause_toggle or rq_pause_toggle
or rc_pause_toggle):
cq_pause.next = cq_pause_toggle
cc_pause.next = cc_pause_toggle
rq_pause.next = rq_pause_toggle
rc_pause.next = rc_pause_toggle
yield user_clk.posedge
yield user_clk.posedge
yield user_clk.posedge
cq_pause.next = 0
cc_pause.next = 0
rq_pause.next = 0
rc_pause.next = 0
yield user_clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
cur_tag = 1
max_read_request_size.next = 2
enable.next = 1
yield user_clk.posedge
print("test 1: enumeration")
current_test.next = 1
yield rc.enumerate(enable_bus_mastering=True)
yield delay(100)
yield user_clk.posedge
print("test 2: PCIe read")
current_test.next = 2
pcie_addr = 0x00000000
axi_addr = 0x00000000
test_data = b'\x11\x22\x33\x44'
mem_data[pcie_addr:pcie_addr + len(test_data)] = test_data
data = mem_data[pcie_addr:pcie_addr + 32]
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
read_desc_source.send([(pcie_addr, axi_addr, len(test_data), cur_tag)])
yield read_desc_status_sink.wait(2000)
yield delay(50)
status = read_desc_status_sink.recv()
print(status)
data = axi_ram_inst.read_mem(axi_addr, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
assert axi_ram_inst.read_mem(axi_addr, len(test_data)) == test_data
cur_tag = (cur_tag + 1) % 256
yield delay(100)
yield user_clk.posedge
print("test 3: various reads")
current_test.next = 3
for length in list(range(1, 11)) + list(range(128 - 4,
128 + 4)) + [1024]:
for pcie_offset in list(range(8, 13)) + list(
range(4096 - 4, 4096 + 4)):
for axi_offset in list(range(8, 17)) + list(
range(4096 - 8, 4096)):
for pause in [False, True]:
print("length %d, pcie_offset %d, axi_offset %d" %
(length, pcie_offset, axi_offset))
#pcie_addr = length * 0x100000000 + pcie_offset * 0x10000 + offset
pcie_addr = pcie_offset
axi_addr = axi_offset
test_data = bytearray([x % 256 for x in range(length)])
mem_data[pcie_addr:pcie_addr +
len(test_data)] = test_data
data = mem_data[pcie_addr
& 0xffff80:(pcie_addr & 0xffff80) + 64]
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
axi_ram_inst.write_mem(
axi_addr & 0xffff80,
b'\xaa' * (len(test_data) + 256))
rq_pause_toggle.next = pause
rc_pause_toggle.next = pause
read_desc_source.send([(pcie_addr, axi_addr,
len(test_data), cur_tag)])
yield read_desc_status_sink.wait(4000)
rq_pause_toggle.next = 0
rc_pause_toggle.next = 0
status = read_desc_status_sink.recv()
print(status)
assert status.data[0][0] == cur_tag
data = axi_ram_inst.read_mem(axi_addr & 0xfffff0, 64)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
assert axi_ram_inst.read_mem(
axi_addr - 8,
len(test_data) +
16) == b'\xaa' * 8 + test_data + b'\xaa' * 8
cur_tag = (cur_tag + 1) % 256
yield delay(50)
raise StopSimulation
return instances()
def bench():
# Parameters
TAG_ENABLE = 1
TAG_WIDTH = 16
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_0_axis_tdata = Signal(intbv(0)[8:])
input_0_axis_tvalid = Signal(bool(0))
input_0_axis_tlast = Signal(bool(0))
input_0_axis_tuser = Signal(bool(0))
input_1_axis_tdata = Signal(intbv(0)[8:])
input_1_axis_tvalid = Signal(bool(0))
input_1_axis_tlast = Signal(bool(0))
input_1_axis_tuser = Signal(bool(0))
input_2_axis_tdata = Signal(intbv(0)[8:])
input_2_axis_tvalid = Signal(bool(0))
input_2_axis_tlast = Signal(bool(0))
input_2_axis_tuser = Signal(bool(0))
input_3_axis_tdata = Signal(intbv(0)[8:])
input_3_axis_tvalid = Signal(bool(0))
input_3_axis_tlast = Signal(bool(0))
input_3_axis_tuser = Signal(bool(0))
output_axis_tready = Signal(bool(0))
tag = Signal(intbv(0)[TAG_WIDTH:])
# Outputs
input_0_axis_tready = Signal(bool(0))
input_1_axis_tready = Signal(bool(0))
input_2_axis_tready = Signal(bool(0))
input_3_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
busy = Signal(bool(0))
# sources and sinks
source_0_pause = Signal(bool(0))
source_1_pause = Signal(bool(0))
source_2_pause = Signal(bool(0))
source_3_pause = Signal(bool(0))
sink_pause = Signal(bool(0))
source_0 = axis_ep.AXIStreamSource()
source_0_logic = source_0.create_logic(clk,
rst,
tdata=input_0_axis_tdata,
tvalid=input_0_axis_tvalid,
tready=input_0_axis_tready,
tlast=input_0_axis_tlast,
tuser=input_0_axis_tuser,
pause=source_0_pause,
name='source_0')
source_1 = axis_ep.AXIStreamSource()
source_1_logic = source_1.create_logic(clk,
rst,
tdata=input_1_axis_tdata,
tvalid=input_1_axis_tvalid,
tready=input_1_axis_tready,
tlast=input_1_axis_tlast,
tuser=input_1_axis_tuser,
pause=source_1_pause,
name='source_1')
source_2 = axis_ep.AXIStreamSource()
source_2_logic = source_2.create_logic(clk,
rst,
tdata=input_2_axis_tdata,
tvalid=input_2_axis_tvalid,
tready=input_2_axis_tready,
tlast=input_2_axis_tlast,
tuser=input_2_axis_tuser,
pause=source_2_pause,
name='source_2')
source_3 = axis_ep.AXIStreamSource()
source_3_logic = source_3.create_logic(clk,
rst,
tdata=input_3_axis_tdata,
tvalid=input_3_axis_tvalid,
tready=input_3_axis_tready,
tlast=input_3_axis_tlast,
tuser=input_3_axis_tuser,
pause=source_3_pause,
name='source_3')
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_0_axis_tdata=input_0_axis_tdata,
input_0_axis_tvalid=input_0_axis_tvalid,
input_0_axis_tready=input_0_axis_tready,
input_0_axis_tlast=input_0_axis_tlast,
input_0_axis_tuser=input_0_axis_tuser,
input_1_axis_tdata=input_1_axis_tdata,
input_1_axis_tvalid=input_1_axis_tvalid,
input_1_axis_tready=input_1_axis_tready,
input_1_axis_tlast=input_1_axis_tlast,
input_1_axis_tuser=input_1_axis_tuser,
input_2_axis_tdata=input_2_axis_tdata,
input_2_axis_tvalid=input_2_axis_tvalid,
input_2_axis_tready=input_2_axis_tready,
input_2_axis_tlast=input_2_axis_tlast,
input_2_axis_tuser=input_2_axis_tuser,
input_3_axis_tdata=input_3_axis_tdata,
input_3_axis_tvalid=input_3_axis_tvalid,
input_3_axis_tready=input_3_axis_tready,
input_3_axis_tlast=input_3_axis_tlast,
input_3_axis_tuser=input_3_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
tag=tag,
busy=busy)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
tag.next = 1
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame_0 = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0.send(test_frame_0)
source_1.send(test_frame_1)
source_2.send(test_frame_2)
source_3.send(test_frame_3)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'>H', tag
) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
yield delay(100)
yield clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame_0 = axis_ep.AXIStreamFrame(b'\x00' + bytearray(range(256)) +
b'\x00')
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0.send(test_frame_0)
source_1.send(test_frame_1)
source_2.send(test_frame_2)
source_3.send(test_frame_3)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'>H', tag
) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
yield delay(100)
yield clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame_0 = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0.send(test_frame_0)
source_1.send(test_frame_1)
source_2.send(test_frame_2)
source_3.send(test_frame_3)
yield clk.posedge
yield delay(64)
yield clk.posedge
source_1_pause.next = True
yield delay(32)
yield clk.posedge
source_1_pause.next = False
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'>H', tag
) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame_0a = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_0b = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1a = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_1b = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2a = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0.send(test_frame_0a)
source_0.send(test_frame_0b)
source_1.send(test_frame_1a)
source_1.send(test_frame_1b)
source_2.send(test_frame_2a)
source_2.send(test_frame_2b)
source_3.send(test_frame_3a)
source_3.send(test_frame_3b)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'>H', tag
) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'>H', tag
) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
yield delay(100)
yield clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame_0a = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_0b = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1a = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_1b = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2a = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0.send(test_frame_0a)
source_0.send(test_frame_0b)
source_1.send(test_frame_1a)
source_1.send(test_frame_1b)
source_2.send(test_frame_2a)
source_2.send(test_frame_2b)
source_3.send(test_frame_3a)
source_3.send(test_frame_3b)
yield clk.posedge
while input_3_axis_tvalid or output_axis_tvalid:
source_0_pause.next = True
source_1_pause.next = True
source_2_pause.next = True
source_3_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_0_pause.next = False
source_1_pause.next = False
source_2_pause.next = False
source_3_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'>H', tag
) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'>H', tag
) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
yield delay(100)
yield clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame_0a = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_0b = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1a = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_1b = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2a = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_2b = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3a = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_3b = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
source_0.send(test_frame_0a)
source_0.send(test_frame_0b)
source_1.send(test_frame_1a)
source_1.send(test_frame_1b)
source_2.send(test_frame_2a)
source_2.send(test_frame_2b)
source_3.send(test_frame_3a)
source_3.send(test_frame_3b)
yield clk.posedge
while input_3_axis_tvalid or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'>H', tag
) + test_frame_0a.data + test_frame_1a.data + test_frame_2a.data + test_frame_3a.data
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'>H', tag
) + test_frame_0b.data + test_frame_1b.data + test_frame_2b.data + test_frame_3b.data
yield delay(100)
yield clk.posedge
print("test 7: tuser assert")
current_test.next = 7
test_frame_0 = axis_ep.AXIStreamFrame(b'\x00\xAA\xBB\xCC\xDD\x00')
test_frame_1 = axis_ep.AXIStreamFrame(b'\x01\xAA\xBB\xCC\xDD\x01')
test_frame_2 = axis_ep.AXIStreamFrame(b'\x02\xAA\xBB\xCC\xDD\x02')
test_frame_3 = axis_ep.AXIStreamFrame(b'\x03\xAA\xBB\xCC\xDD\x03')
test_frame_0.last_cycle_user = 1
source_0.send(test_frame_0)
source_1.send(test_frame_1)
source_2.send(test_frame_2)
source_3.send(test_frame_3)
yield clk.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame.data == struct.pack(
'>H', tag
) + test_frame_0.data + test_frame_1.data + test_frame_2.data + test_frame_3.data
assert rx_frame.last_cycle_user
yield delay(100)
raise StopSimulation
return dut, source_0_logic, source_1_logic, source_2_logic, source_3_logic, sink_logic, clkgen, check
def bench():
# Parameters
SEG_COUNT = 2
SEG_DATA_WIDTH = 64
SEG_ADDR_WIDTH = 12
SEG_BE_WIDTH = int(SEG_DATA_WIDTH / 8)
RAM_ADDR_WIDTH = SEG_ADDR_WIDTH + (SEG_COUNT - 1).bit_length() + (
SEG_BE_WIDTH - 1).bit_length()
AXIS_DATA_WIDTH = SEG_DATA_WIDTH * SEG_COUNT / 2
AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH > 8)
AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH / 8)
AXIS_LAST_ENABLE = 1
AXIS_ID_ENABLE = 1
AXIS_ID_WIDTH = 8
AXIS_DEST_ENABLE = 0
AXIS_DEST_WIDTH = 8
AXIS_USER_ENABLE = 1
AXIS_USER_WIDTH = 1
LEN_WIDTH = 20
TAG_WIDTH = 8
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_read_desc_ram_addr = Signal(intbv(0)[RAM_ADDR_WIDTH:])
s_axis_read_desc_len = Signal(intbv(0)[LEN_WIDTH:])
s_axis_read_desc_tag = Signal(intbv(0)[TAG_WIDTH:])
s_axis_read_desc_id = Signal(intbv(0)[AXIS_ID_WIDTH:])
s_axis_read_desc_dest = Signal(intbv(0)[AXIS_DEST_WIDTH:])
s_axis_read_desc_user = Signal(intbv(0)[AXIS_USER_WIDTH:])
s_axis_read_desc_valid = Signal(bool(0))
m_axis_read_data_tready = Signal(bool(0))
ram_rd_cmd_ready = Signal(intbv(0)[SEG_COUNT:])
ram_rd_resp_data = Signal(intbv(0)[SEG_COUNT * SEG_DATA_WIDTH:])
ram_rd_resp_valid = Signal(intbv(0)[SEG_COUNT:])
enable = Signal(bool(0))
# Outputs
s_axis_read_desc_ready = Signal(bool(0))
m_axis_read_desc_status_tag = Signal(intbv(0)[TAG_WIDTH:])
m_axis_read_desc_status_valid = Signal(bool(0))
m_axis_read_data_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
m_axis_read_data_tkeep = Signal(intbv(0)[AXIS_KEEP_WIDTH:])
m_axis_read_data_tvalid = Signal(bool(0))
m_axis_read_data_tlast = Signal(bool(0))
m_axis_read_data_tid = Signal(intbv(0)[AXIS_ID_WIDTH:])
m_axis_read_data_tdest = Signal(intbv(0)[AXIS_DEST_WIDTH:])
m_axis_read_data_tuser = Signal(intbv(0)[AXIS_USER_WIDTH:])
ram_rd_cmd_addr = Signal(intbv(0)[SEG_COUNT * SEG_ADDR_WIDTH:])
ram_rd_cmd_valid = Signal(intbv(0)[SEG_COUNT:])
ram_rd_resp_ready = Signal(intbv(0)[SEG_COUNT:])
# PCIe DMA RAM
dma_ram_inst = dma_ram.PSDPRam(2**16)
dma_ram_pause = Signal(bool(0))
dma_ram_port0 = dma_ram_inst.create_read_ports(
clk,
ram_rd_cmd_addr=ram_rd_cmd_addr,
ram_rd_cmd_valid=ram_rd_cmd_valid,
ram_rd_cmd_ready=ram_rd_cmd_ready,
ram_rd_resp_data=ram_rd_resp_data,
ram_rd_resp_valid=ram_rd_resp_valid,
ram_rd_resp_ready=ram_rd_resp_ready,
pause=dma_ram_pause,
name='port0')
# sources and sinks
read_desc_source = axis_ep.AXIStreamSource()
read_desc_source_pause = Signal(bool(False))
read_desc_source_logic = read_desc_source.create_logic(
clk,
rst,
tdata=(s_axis_read_desc_ram_addr, s_axis_read_desc_len,
s_axis_read_desc_tag, s_axis_read_desc_id,
s_axis_read_desc_dest, s_axis_read_desc_user),
tvalid=s_axis_read_desc_valid,
tready=s_axis_read_desc_ready,
pause=read_desc_source_pause,
name='read_desc_source')
read_desc_status_sink = axis_ep.AXIStreamSink()
read_desc_status_sink_logic = read_desc_status_sink.create_logic(
clk,
rst,
tdata=(m_axis_read_desc_status_tag, ),
tvalid=m_axis_read_desc_status_valid,
name='read_desc_status_sink')
read_data_sink = axis_ep.AXIStreamSink()
read_data_sink_pause = Signal(bool(False))
read_data_sink_logic = read_data_sink.create_logic(
clk,
rst,
tdata=m_axis_read_data_tdata,
tkeep=m_axis_read_data_tkeep,
tvalid=m_axis_read_data_tvalid,
tready=m_axis_read_data_tready,
tlast=m_axis_read_data_tlast,
tid=m_axis_read_data_tid,
tdest=m_axis_read_data_tdest,
tuser=m_axis_read_data_tuser,
pause=read_data_sink_pause,
name='read_data_sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_axis_read_desc_ram_addr=s_axis_read_desc_ram_addr,
s_axis_read_desc_len=s_axis_read_desc_len,
s_axis_read_desc_tag=s_axis_read_desc_tag,
s_axis_read_desc_id=s_axis_read_desc_id,
s_axis_read_desc_dest=s_axis_read_desc_dest,
s_axis_read_desc_user=s_axis_read_desc_user,
s_axis_read_desc_valid=s_axis_read_desc_valid,
s_axis_read_desc_ready=s_axis_read_desc_ready,
m_axis_read_desc_status_tag=m_axis_read_desc_status_tag,
m_axis_read_desc_status_valid=m_axis_read_desc_status_valid,
m_axis_read_data_tdata=m_axis_read_data_tdata,
m_axis_read_data_tkeep=m_axis_read_data_tkeep,
m_axis_read_data_tvalid=m_axis_read_data_tvalid,
m_axis_read_data_tready=m_axis_read_data_tready,
m_axis_read_data_tlast=m_axis_read_data_tlast,
m_axis_read_data_tid=m_axis_read_data_tid,
m_axis_read_data_tdest=m_axis_read_data_tdest,
m_axis_read_data_tuser=m_axis_read_data_tuser,
ram_rd_cmd_addr=ram_rd_cmd_addr,
ram_rd_cmd_valid=ram_rd_cmd_valid,
ram_rd_cmd_ready=ram_rd_cmd_ready,
ram_rd_resp_data=ram_rd_resp_data,
ram_rd_resp_valid=ram_rd_resp_valid,
ram_rd_resp_ready=ram_rd_resp_ready,
enable=enable)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while read_desc_status_sink.empty() or read_data_sink.empty():
yield clk.posedge
def wait_pause_ram():
while read_desc_status_sink.empty() or read_data_sink.empty():
dma_ram_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
dma_ram_pause.next = False
yield clk.posedge
def wait_pause_sink():
while read_desc_status_sink.empty() or read_data_sink.empty():
read_data_sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
read_data_sink_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
cur_tag = 1
enable.next = 1
yield clk.posedge
print("test 1: read")
current_test.next = 1
addr = 0x00000000
test_data = b'\x11\x22\x33\x44'
dma_ram_inst.write_mem(addr, test_data)
data = dma_ram_inst.read_mem(addr, 32)
for i in range(0, len(data), 16):
print(" ".join(
("{:02x}".format(c) for c in bytearray(data[i:i + 16]))))
read_desc_source.send([(addr, len(test_data), cur_tag, cur_tag, 0, 0)])
yield read_desc_status_sink.wait(1000)
yield read_data_sink.wait(1000)
status = read_desc_status_sink.recv()
read_data = read_data_sink.recv()
print(status)
print(read_data)
assert status.data[0][0] == cur_tag
assert read_data.data == test_data
assert read_data.id[0] == cur_tag
cur_tag = (cur_tag + 1) % 256
yield delay(100)
yield clk.posedge
print("test 2: various reads")
current_test.next = 2
for length in list(range(1, 34)) + [128]:
for offset in list(range(8, 17, 8)) + list(range(
4096 - 8, 4096, 8)):
for wait in wait_normal, wait_pause_ram, wait_pause_sink:
print("length %d, offset %d" % (length, offset))
#addr = length * 0x100000000 + offset * 0x10000 + offset
addr = offset
test_data = bytearray([x % 256 for x in range(length)])
dma_ram_inst.write_mem(addr & 0xffff80,
b'\xaa' * (len(test_data) + 256))
dma_ram_inst.write_mem(addr, test_data)
data = dma_ram_inst.read_mem(addr & 0xfffff0, 64)
for i in range(0, len(data), 16):
print(" ".join(("{:02x}".format(c)
for c in bytearray(data[i:i + 16]))))
read_desc_source.send([(addr, len(test_data), cur_tag,
cur_tag, 0, 0)])
yield wait()
status = read_desc_status_sink.recv()
read_data = read_data_sink.recv()
print(status)
print(read_data)
assert status.data[0][0] == cur_tag
assert read_data.data == test_data
assert read_data.id[0] == cur_tag
cur_tag = (cur_tag + 1) % 256
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
ENABLE_PADDING = 1
MIN_FRAME_LENGTH = 64
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
output_axis_tready = Signal(bool(0))
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
busy = Signal(bool(0))
# sources and sinks
source_pause = Signal(bool(0))
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource()
source_logic = source.create_logic(
clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
)
sink = axis_ep.AXIStreamSink()
sink_logic = sink.create_logic(
clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
)
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation(
"vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
busy=busy
)
@always(delay(4))
def clkgen():
clk.next = not clk
def wait_normal():
while input_axis_tvalid or output_axis_tvalid:
yield clk.posedge
def wait_pause_source():
while input_axis_tvalid or output_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
def wait_pause_sink():
while input_axis_tvalid or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
for payload_len in list(range(1,18))+list(range(64,82)):
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(payload_len))
test_frame.update_fcs()
axis_frame = test_frame.build_axis()
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(axis_frame)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame)
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert eth_frame.payload.data == test_frame.payload.data
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame.eth_src_mac
assert eth_frame.eth_type == test_frame.eth_type
assert eth_frame.payload.data.index(test_frame.payload.data) == 0
assert sink.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(payload_len))
test_frame1.update_fcs()
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(payload_len))
test_frame2.update_fcs()
axis_frame1 = test_frame1.build_axis()
axis_frame2 = test_frame2.build_axis()
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(axis_frame1)
source.send(axis_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame)
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert eth_frame.payload.data == test_frame1.payload.data
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame1.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame1.eth_src_mac
assert eth_frame.eth_type == test_frame1.eth_type
assert eth_frame.payload.data.index(test_frame1.payload.data) == 0
rx_frame = sink.recv()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame)
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert eth_frame.payload.data == test_frame2.payload.data
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame2.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame2.eth_src_mac
assert eth_frame.eth_type == test_frame2.eth_type
assert eth_frame.payload.data.index(test_frame2.payload.data) == 0
assert sink.empty()
yield delay(100)
yield clk.posedge
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(payload_len))
test_frame1.update_fcs()
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(payload_len))
test_frame2.update_fcs()
axis_frame1 = test_frame1.build_axis()
axis_frame2 = test_frame2.build_axis()
axis_frame1.user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(axis_frame1)
source.send(axis_frame2)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
assert rx_frame.user[-1]
rx_frame = sink.recv()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame)
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert eth_frame.payload.data == test_frame2.payload.data
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame2.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame2.eth_src_mac
assert eth_frame.eth_type == test_frame2.eth_type
assert eth_frame.payload.data.index(test_frame2.payload.data) == 0
assert sink.empty()
yield delay(100)
for payload_len in list(range(1,18)):
yield clk.posedge
print("test 4: test short packet, length %d" % payload_len)
current_test.next = 4
test_frame = bytearray(range(payload_len))
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame)
yield clk.posedge
yield clk.posedge
yield wait()
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = sink.recv()
payload = rx_frame.data[:-4]
fcs = struct.unpack('<L', rx_frame.data[-4:])[0]
check_fcs = zlib.crc32(bytes(payload)) & 0xffffffff
print(hex(fcs))
print(hex(check_fcs))
assert test_frame == payload
assert check_fcs == fcs
assert sink.empty()
yield delay(100)
raise StopSimulation
return dut, source_logic, sink_logic, clkgen, check
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
prescale = Signal(intbv(0)[16:])
# Outputs
input_axis_tready = Signal(bool(0))
txd = Signal(bool(1))
busy = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
fifo=source_queue,
pause=source_pause,
name='source')
sink = uart_ep.UARTSink(clk,
rst,
rxd=txd,
prescale=prescale,
fifo=sink_queue,
name='sink')
# DUT
dut = dut_uart_tx(clk, rst, current_test, input_axis_tdata,
input_axis_tvalid, input_axis_tready, txd, busy,
prescale)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
prescale.next = 1
yield clk.posedge
yield clk.posedge
print("test 1: walk")
current_test.next = 1
source_queue.put(bytearray(b'\x00\x01\x02\x04\x08\x10\x20\x40\x80'))
yield clk.posedge
yield input_axis_tvalid.negedge
yield delay(1000)
yield clk.posedge
rx_data = b''
while not sink_queue.empty():
rx_data += bytearray(sink_queue.get())
assert rx_data == b'\x00\x01\x02\x04\x08\x10\x20\x40\x80'
yield clk.posedge
print("test 2: walk 2")
current_test.next = 2
source_queue.put(bytearray(b'\x00\x01\x03\x07\x0F\x1F\x3F\x7F\xFF'))
yield clk.posedge
yield input_axis_tvalid.negedge
yield delay(1000)
yield clk.posedge
rx_data = b''
while not sink_queue.empty():
rx_data += bytearray(sink_queue.get())
assert rx_data == b'\x00\x01\x03\x07\x0F\x1F\x3F\x7F\xFF'
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
def bench():
# Parameters
DATA_WIDTH = 32
KEEP_WIDTH = (DATA_WIDTH / 8)
CTRL_WIDTH = (DATA_WIDTH / 8)
ENABLE_PADDING = 1
ENABLE_DIC = 1
MIN_FRAME_LENGTH = 64
TX_PTP_TS_ENABLE = 0
TX_PTP_TS_WIDTH = 96
TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE
TX_PTP_TAG_WIDTH = 16
RX_PTP_TS_ENABLE = 0
RX_PTP_TS_WIDTH = 96
TX_USER_WIDTH = (TX_PTP_TAG_WIDTH if TX_PTP_TAG_ENABLE else 0) + 1
RX_USER_WIDTH = (RX_PTP_TS_WIDTH if RX_PTP_TS_ENABLE else 0) + 1
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
rx_clk = Signal(bool(0))
rx_rst = Signal(bool(0))
tx_clk = Signal(bool(0))
tx_rst = Signal(bool(0))
tx_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
tx_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
tx_axis_tvalid = Signal(bool(0))
tx_axis_tlast = Signal(bool(0))
tx_axis_tuser = Signal(intbv(0)[TX_USER_WIDTH:])
xgmii_rxd = Signal(intbv(0x0707070707070707)[DATA_WIDTH:])
xgmii_rxc = Signal(intbv(0xff)[CTRL_WIDTH:])
tx_ptp_ts = Signal(intbv(0)[TX_PTP_TS_WIDTH:])
rx_ptp_ts = Signal(intbv(0)[RX_PTP_TS_WIDTH:])
ifg_delay = Signal(intbv(0)[8:])
# Outputs
tx_axis_tready = Signal(bool(0))
rx_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
rx_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
rx_axis_tvalid = Signal(bool(0))
rx_axis_tlast = Signal(bool(0))
rx_axis_tuser = Signal(intbv(0)[RX_USER_WIDTH:])
xgmii_txd = Signal(intbv(0x0707070707070707)[DATA_WIDTH:])
xgmii_txc = Signal(intbv(0xff)[CTRL_WIDTH:])
tx_axis_ptp_ts = Signal(intbv(0)[TX_PTP_TS_WIDTH:])
tx_axis_ptp_ts_tag = Signal(intbv(0)[TX_PTP_TAG_WIDTH:])
tx_axis_ptp_ts_valid = Signal(bool(0))
tx_start_packet = Signal(intbv(0)[2:])
tx_error_underflow = Signal(bool(0))
rx_start_packet = Signal(intbv(0)[2:])
rx_error_bad_frame = Signal(bool(0))
rx_error_bad_fcs = Signal(bool(0))
# sources and sinks
axis_source_pause = Signal(bool(0))
xgmii_source = xgmii_ep.XGMIISource()
xgmii_source_logic = xgmii_source.create_logic(clk,
rst,
txd=xgmii_rxd,
txc=xgmii_rxc,
name='xgmii_source')
xgmii_sink = xgmii_ep.XGMIISink()
xgmii_sink_logic = xgmii_sink.create_logic(clk,
rst,
rxd=xgmii_txd,
rxc=xgmii_txc,
name='xgmii_sink')
axis_source = axis_ep.AXIStreamSource()
axis_source_logic = axis_source.create_logic(clk,
rst,
tdata=tx_axis_tdata,
tkeep=tx_axis_tkeep,
tvalid=tx_axis_tvalid,
tready=tx_axis_tready,
tlast=tx_axis_tlast,
tuser=tx_axis_tuser,
pause=axis_source_pause,
name='axis_source')
axis_sink = axis_ep.AXIStreamSink()
axis_sink_logic = axis_sink.create_logic(clk,
rst,
tdata=rx_axis_tdata,
tkeep=rx_axis_tkeep,
tvalid=rx_axis_tvalid,
tlast=rx_axis_tlast,
tuser=rx_axis_tuser,
name='axis_sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
rx_clk=rx_clk,
rx_rst=rx_rst,
tx_clk=tx_clk,
tx_rst=tx_rst,
tx_axis_tdata=tx_axis_tdata,
tx_axis_tkeep=tx_axis_tkeep,
tx_axis_tvalid=tx_axis_tvalid,
tx_axis_tready=tx_axis_tready,
tx_axis_tlast=tx_axis_tlast,
tx_axis_tuser=tx_axis_tuser,
rx_axis_tdata=rx_axis_tdata,
rx_axis_tkeep=rx_axis_tkeep,
rx_axis_tvalid=rx_axis_tvalid,
rx_axis_tlast=rx_axis_tlast,
rx_axis_tuser=rx_axis_tuser,
xgmii_rxd=xgmii_rxd,
xgmii_rxc=xgmii_rxc,
xgmii_txd=xgmii_txd,
xgmii_txc=xgmii_txc,
tx_ptp_ts=tx_ptp_ts,
rx_ptp_ts=rx_ptp_ts,
tx_axis_ptp_ts=tx_axis_ptp_ts,
tx_axis_ptp_ts_tag=tx_axis_ptp_ts_tag,
tx_axis_ptp_ts_valid=tx_axis_ptp_ts_valid,
tx_start_packet=tx_start_packet,
tx_error_underflow=tx_error_underflow,
rx_start_packet=rx_start_packet,
rx_error_bad_frame=rx_error_bad_frame,
rx_error_bad_fcs=rx_error_bad_fcs,
ifg_delay=ifg_delay)
@always(delay(4))
def clkgen():
clk.next = not clk
tx_clk.next = not tx_clk
rx_clk.next = not rx_clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
tx_rst.next = 1
rx_rst.next = 1
yield clk.posedge
rst.next = 0
tx_rst.next = 0
rx_rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
ifg_delay.next = 12
# testbench stimulus
yield clk.posedge
print("test 1: test rx packet")
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis_fcs()
xgmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
bytearray(axis_frame))
yield axis_sink.wait()
rx_frame = axis_sink.recv()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis(rx_frame)
eth_frame.update_fcs()
assert eth_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: test tx packet")
current_test.next = 2
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis()
axis_source.send(axis_frame)
yield xgmii_sink.wait()
rx_frame = xgmii_sink.recv()
assert rx_frame.data[0:8] == bytearray(
b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == 46
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame.eth_src_mac
assert eth_frame.eth_type == test_frame.eth_type
assert eth_frame.payload.data.index(test_frame.payload.data) == 0
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
TARGET = "SIM"
CLOCK_INPUT_STYLE = "BUFIO2"
AXIS_DATA_WIDTH = 8
AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH > 8)
AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH / 8)
ENABLE_PADDING = 1
MIN_FRAME_LENGTH = 64
TX_FIFO_DEPTH = 4096
TX_FRAME_FIFO = 1
TX_DROP_BAD_FRAME = TX_FRAME_FIFO
TX_DROP_WHEN_FULL = 0
RX_FIFO_DEPTH = 4096
RX_FRAME_FIFO = 1
RX_DROP_BAD_FRAME = RX_FRAME_FIFO
RX_DROP_WHEN_FULL = RX_FRAME_FIFO
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
logic_clk = Signal(bool(0))
logic_rst = Signal(bool(0))
tx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
tx_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:])
tx_axis_tvalid = Signal(bool(0))
tx_axis_tlast = Signal(bool(0))
tx_axis_tuser = Signal(bool(0))
rx_axis_tready = Signal(bool(0))
mii_rx_clk = Signal(bool(0))
mii_rxd = Signal(intbv(0)[4:])
mii_rx_dv = Signal(bool(0))
mii_rx_er = Signal(bool(0))
mii_tx_clk = Signal(bool(0))
ifg_delay = Signal(intbv(0)[8:])
# Outputs
tx_axis_tready = Signal(bool(0))
rx_axis_tdata = Signal(intbv(0)[AXIS_DATA_WIDTH:])
rx_axis_tkeep = Signal(intbv(1)[AXIS_KEEP_WIDTH:])
rx_axis_tvalid = Signal(bool(0))
rx_axis_tlast = Signal(bool(0))
rx_axis_tuser = Signal(bool(0))
mii_txd = Signal(intbv(0)[4:])
mii_tx_en = Signal(bool(0))
mii_tx_er = Signal(bool(0))
tx_error_underflow = Signal(bool(0))
tx_fifo_overflow = Signal(bool(0))
tx_fifo_bad_frame = Signal(bool(0))
tx_fifo_good_frame = Signal(bool(0))
rx_error_bad_frame = Signal(bool(0))
rx_error_bad_fcs = Signal(bool(0))
rx_fifo_overflow = Signal(bool(0))
rx_fifo_bad_frame = Signal(bool(0))
rx_fifo_good_frame = Signal(bool(0))
# sources and sinks
axis_source_pause = Signal(bool(0))
axis_sink_pause = Signal(bool(0))
mii_source = mii_ep.MIISource()
mii_source_logic = mii_source.create_logic(mii_rx_clk,
rst,
txd=mii_rxd,
tx_en=mii_rx_dv,
tx_er=mii_rx_er,
name='mii_source')
mii_sink = mii_ep.MIISink()
mii_sink_logic = mii_sink.create_logic(mii_tx_clk,
rst,
rxd=mii_txd,
rx_dv=mii_tx_en,
rx_er=mii_tx_er,
name='mii_sink')
axis_source = axis_ep.AXIStreamSource()
axis_source_logic = axis_source.create_logic(logic_clk,
logic_rst,
tdata=tx_axis_tdata,
tkeep=tx_axis_tkeep,
tvalid=tx_axis_tvalid,
tready=tx_axis_tready,
tlast=tx_axis_tlast,
tuser=tx_axis_tuser,
pause=axis_source_pause,
name='axis_source')
axis_sink = axis_ep.AXIStreamSink()
axis_sink_logic = axis_sink.create_logic(logic_clk,
logic_rst,
tdata=rx_axis_tdata,
tkeep=rx_axis_tkeep,
tvalid=rx_axis_tvalid,
tready=rx_axis_tready,
tlast=rx_axis_tlast,
tuser=rx_axis_tuser,
pause=axis_sink_pause,
name='axis_sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
logic_clk=logic_clk,
logic_rst=logic_rst,
tx_axis_tdata=tx_axis_tdata,
tx_axis_tkeep=tx_axis_tkeep,
tx_axis_tvalid=tx_axis_tvalid,
tx_axis_tready=tx_axis_tready,
tx_axis_tlast=tx_axis_tlast,
tx_axis_tuser=tx_axis_tuser,
rx_axis_tdata=rx_axis_tdata,
rx_axis_tkeep=rx_axis_tkeep,
rx_axis_tvalid=rx_axis_tvalid,
rx_axis_tready=rx_axis_tready,
rx_axis_tlast=rx_axis_tlast,
rx_axis_tuser=rx_axis_tuser,
mii_rx_clk=mii_rx_clk,
mii_rxd=mii_rxd,
mii_rx_dv=mii_rx_dv,
mii_rx_er=mii_rx_er,
mii_tx_clk=mii_tx_clk,
mii_txd=mii_txd,
mii_tx_en=mii_tx_en,
mii_tx_er=mii_tx_er,
tx_error_underflow=tx_error_underflow,
tx_fifo_overflow=tx_fifo_overflow,
tx_fifo_bad_frame=tx_fifo_bad_frame,
tx_fifo_good_frame=tx_fifo_good_frame,
rx_error_bad_frame=rx_error_bad_frame,
rx_error_bad_fcs=rx_error_bad_fcs,
rx_fifo_overflow=rx_fifo_overflow,
rx_fifo_bad_frame=rx_fifo_bad_frame,
rx_fifo_good_frame=rx_fifo_good_frame,
ifg_delay=ifg_delay)
@always(delay(4))
def clkgen():
clk.next = not clk
logic_clk.next = not clk
phy_clk_hp = Signal(int(20))
@instance
def phy_clk_gen():
while True:
yield delay(int(phy_clk_hp))
mii_rx_clk.next = not mii_rx_clk
mii_tx_clk.next = not mii_rx_clk
rx_error_bad_frame_asserted = Signal(bool(0))
rx_error_bad_fcs_asserted = Signal(bool(0))
@always(clk.posedge)
def monitor():
if (rx_error_bad_frame):
rx_error_bad_frame_asserted.next = 1
if (rx_error_bad_fcs):
rx_error_bad_fcs_asserted.next = 1
clk_enable_rate = Signal(int(0))
clk_enable_div = Signal(int(0))
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
logic_rst.next = 1
yield clk.posedge
rst.next = 0
logic_rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
ifg_delay.next = 12
# testbench stimulus
for rate in [20, 200]:
phy_clk_hp.next = rate
yield delay(1000)
yield clk.posedge
print("test 1: test rx packet")
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis_fcs()
mii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
bytearray(axis_frame))
yield axis_sink.wait()
rx_frame = axis_sink.recv()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis(rx_frame)
eth_frame.update_fcs()
assert eth_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: test tx packet")
current_test.next = 2
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis()
axis_source.send(axis_frame)
yield mii_sink.wait()
rx_frame = mii_sink.recv()
assert rx_frame.data[0:8] == bytearray(
b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == 46
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame.eth_src_mac
assert eth_frame.eth_type == test_frame.eth_type
assert eth_frame.payload.data.index(test_frame.payload.data) == 0
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
WIDTH = 16
RMAX = 4
M = 1
N = 2
REG_WIDTH = WIDTH+max(N, math.ceil(math.log10(((RMAX*M)**N)/RMAX)/math.log10(2)))
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_tdata = Signal(intbv(0)[WIDTH:])
input_tvalid = Signal(bool(0))
output_tready = Signal(bool(0))
rate = Signal(intbv(0)[math.ceil(math.log10(RMAX+1)/math.log10(2)):])
# Outputs
input_tready = Signal(bool(0))
output_tdata = Signal(intbv(0)[REG_WIDTH:])
output_tvalid = Signal(bool(0))
# sources and sinks
input_source_queue = Queue()
input_source_pause = Signal(bool(0))
output_sink_queue = Queue()
output_sink_pause = Signal(bool(0))
input_source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_tdata,
tvalid=input_tvalid,
tready=input_tready,
fifo=input_source_queue,
pause=input_source_pause,
name='input_source')
output_sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_tdata,
tvalid=output_tvalid,
tready=output_tready,
fifo=output_sink_queue,
pause=output_sink_pause,
name='output_sink')
# DUT
dut = dut_cic_interpolator(clk,
rst,
current_test,
input_tdata,
input_tvalid,
input_tready,
output_tdata,
output_tvalid,
output_tready,
rate)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
rate.next = 2
yield clk.posedge
print("test 1: impulse response")
current_test.next = 1
y = [1, 0, 0, 0, 0]
ref = cic_interpolate(y, N, M, rate)
test_frame = axis_ep.AXIStreamFrame()
test_frame.data = y + [0]*5
input_source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
while input_tvalid:
yield clk.posedge
yield clk.posedge
lst = []
while not output_sink_queue.empty():
lst += output_sink_queue.get(False).data
print(lst)
print(ref)
assert contains(ref, lst)
yield delay(100)
yield clk.posedge
print("test 2: ramp")
current_test.next = 2
y = list(range(100)) + [0,0]
ref = cic_interpolate(y, N, M, rate)
test_frame = axis_ep.AXIStreamFrame()
test_frame.data = y + [0]*5
input_source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
while input_tvalid:
yield clk.posedge
yield clk.posedge
lst = []
while not output_sink_queue.empty():
lst += output_sink_queue.get(False).data
print(lst)
print(ref)
assert contains(ref, lst)
yield delay(100)
yield clk.posedge
print("test 3: source pause")
current_test.next = 3
y = list(range(100)) + [0,0]
ref = cic_interpolate(y, N, M, rate)
test_frame = axis_ep.AXIStreamFrame()
test_frame.data = y + [0]*5
input_source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
while input_tvalid:
input_source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
input_source_pause.next = False
yield clk.posedge
yield clk.posedge
lst = []
while not output_sink_queue.empty():
lst += output_sink_queue.get(False).data
print(lst)
print(ref)
assert contains(ref, lst)
yield delay(100)
yield clk.posedge
print("test 4: sink pause")
current_test.next = 4
y = list(range(100)) + [0,0]
ref = cic_interpolate(y, N, M, rate)
test_frame = axis_ep.AXIStreamFrame()
test_frame.data = y + [0]*5
input_source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
while input_tvalid:
output_sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
output_sink_pause.next = False
yield clk.posedge
yield clk.posedge
lst = []
while not output_sink_queue.empty():
lst += output_sink_queue.get(False).data
print(lst)
print(ref)
assert contains(ref, lst)
yield delay(100)
yield clk.posedge
print("test 5: sinewave")
current_test.next = 5
x = np.arange(0,100)
y = np.r_[(np.sin(2*np.pi*x/50)*1024).astype(int), [0,0]]
ref = cic_interpolate(y, N, M, rate)
ys = y
ys[y < 0] += 2**WIDTH
refs = ref
refs[ref < 0] += 2**REG_WIDTH
test_frame = axis_ep.AXIStreamFrame()
test_frame.data = list(ys) + [0]*5
input_source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
while input_tvalid:
yield clk.posedge
yield clk.posedge
lst = []
while not output_sink_queue.empty():
lst += output_sink_queue.get(False).data
print(lst)
print(ref)
assert contains(ref, lst)
yield delay(100)
yield clk.posedge
print("test 6: rate of 4")
current_test.next = 6
rate.next = 4
yield clk.posedge
x = np.arange(0,100)
y = np.r_[(np.sin(2*np.pi*x/50)*1024).astype(int), [0,0]]
ref = cic_interpolate(y, N, M, rate)
ys = y
ys[y < 0] += 2**WIDTH
refs = ref
refs[ref < 0] += 2**REG_WIDTH
test_frame = axis_ep.AXIStreamFrame()
test_frame.data = list(ys) + [0]*5
input_source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
while input_tvalid:
yield clk.posedge
yield clk.posedge
lst = []
while not output_sink_queue.empty():
lst += output_sink_queue.get(False).data
print(lst)
print(ref)
assert contains(ref, lst)
yield delay(100)
raise StopSimulation
return dut, input_source, output_sink, clkgen, check
def bench():
# Parameters
ENABLE_PADDING = 1
MIN_FRAME_LENGTH = 64
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
rx_clk = Signal(bool(0))
rx_rst = Signal(bool(0))
tx_clk = Signal(bool(0))
tx_rst = Signal(bool(0))
tx_axis_tdata = Signal(intbv(0)[8:])
tx_axis_tvalid = Signal(bool(0))
tx_axis_tlast = Signal(bool(0))
tx_axis_tuser = Signal(bool(0))
gmii_rxd = Signal(intbv(0)[8:])
gmii_rx_dv = Signal(bool(0))
gmii_rx_er = Signal(bool(0))
rx_clk_enable = Signal(bool(1))
tx_clk_enable = Signal(bool(1))
rx_mii_select = Signal(bool(0))
tx_mii_select = Signal(bool(0))
ifg_delay = Signal(intbv(0)[8:])
# Outputs
tx_axis_tready = Signal(bool(0))
rx_axis_tdata = Signal(intbv(0)[8:])
rx_axis_tvalid = Signal(bool(0))
rx_axis_tlast = Signal(bool(0))
rx_axis_tuser = Signal(bool(0))
gmii_txd = Signal(intbv(0)[8:])
gmii_tx_en = Signal(bool(0))
gmii_tx_er = Signal(bool(0))
tx_start_packet = Signal(bool(0))
tx_error_underflow = Signal(bool(0))
rx_start_packet = Signal(bool(0))
rx_error_bad_frame = Signal(bool(0))
rx_error_bad_fcs = Signal(bool(0))
# sources and sinks
axis_source_pause = Signal(bool(0))
gmii_source = gmii_ep.GMIISource()
gmii_source_logic = gmii_source.create_logic(clk,
rst,
txd=gmii_rxd,
tx_en=gmii_rx_dv,
tx_er=gmii_rx_er,
clk_enable=rx_clk_enable,
mii_select=rx_mii_select,
name='gmii_source')
gmii_sink = gmii_ep.GMIISink()
gmii_sink_logic = gmii_sink.create_logic(clk,
rst,
rxd=gmii_txd,
rx_dv=gmii_tx_en,
rx_er=gmii_tx_er,
clk_enable=tx_clk_enable,
mii_select=tx_mii_select,
name='gmii_sink')
axis_source = axis_ep.AXIStreamSource()
axis_source_logic = axis_source.create_logic(clk,
rst,
tdata=tx_axis_tdata,
tvalid=tx_axis_tvalid,
tready=tx_axis_tready,
tlast=tx_axis_tlast,
tuser=tx_axis_tuser,
pause=axis_source_pause,
name='axis_source')
axis_sink = axis_ep.AXIStreamSink()
axis_sink_logic = axis_sink.create_logic(clk,
rst,
tdata=rx_axis_tdata,
tvalid=rx_axis_tvalid,
tlast=rx_axis_tlast,
tuser=rx_axis_tuser,
name='axis_sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
rx_clk=rx_clk,
rx_rst=rx_rst,
tx_clk=tx_clk,
tx_rst=tx_rst,
tx_axis_tdata=tx_axis_tdata,
tx_axis_tvalid=tx_axis_tvalid,
tx_axis_tready=tx_axis_tready,
tx_axis_tlast=tx_axis_tlast,
tx_axis_tuser=tx_axis_tuser,
rx_axis_tdata=rx_axis_tdata,
rx_axis_tvalid=rx_axis_tvalid,
rx_axis_tlast=rx_axis_tlast,
rx_axis_tuser=rx_axis_tuser,
gmii_rxd=gmii_rxd,
gmii_rx_dv=gmii_rx_dv,
gmii_rx_er=gmii_rx_er,
gmii_txd=gmii_txd,
gmii_tx_en=gmii_tx_en,
gmii_tx_er=gmii_tx_er,
rx_clk_enable=rx_clk_enable,
tx_clk_enable=tx_clk_enable,
rx_mii_select=rx_mii_select,
tx_mii_select=tx_mii_select,
tx_start_packet=tx_start_packet,
tx_error_underflow=tx_error_underflow,
rx_start_packet=rx_start_packet,
rx_error_bad_frame=rx_error_bad_frame,
rx_error_bad_fcs=rx_error_bad_fcs,
ifg_delay=ifg_delay)
@always(delay(4))
def clkgen():
clk.next = not clk
tx_clk.next = not tx_clk
rx_clk.next = not rx_clk
rx_error_bad_frame_asserted = Signal(bool(0))
rx_error_bad_fcs_asserted = Signal(bool(0))
@always(clk.posedge)
def monitor():
if (rx_error_bad_frame):
rx_error_bad_frame_asserted.next = 1
if (rx_error_bad_fcs):
rx_error_bad_fcs_asserted.next = 1
clk_enable_rate = Signal(int(0))
clk_enable_div = Signal(int(0))
@always(clk.posedge)
def clk_enable_gen():
if clk_enable_div.next > 0:
rx_clk_enable.next = 0
tx_clk_enable.next = 0
clk_enable_div.next = clk_enable_div - 1
else:
rx_clk_enable.next = 1
tx_clk_enable.next = 1
clk_enable_div.next = clk_enable_rate - 1
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
tx_rst.next = 1
rx_rst.next = 1
yield clk.posedge
rst.next = 0
tx_rst.next = 0
rx_rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
ifg_delay.next = 12
# testbench stimulus
for rate, mii in [(1, 0), (10, 0), (5, 1)]:
clk_enable_rate.next = rate
rx_mii_select.next = mii
tx_mii_select.next = mii
yield clk.posedge
print("test 1: test rx packet")
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis_fcs()
gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' +
bytearray(axis_frame))
yield axis_sink.wait()
rx_frame = axis_sink.recv()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis(rx_frame)
eth_frame.update_fcs()
assert eth_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: test tx packet")
current_test.next = 2
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis()
axis_source.send(axis_frame)
yield gmii_sink.wait()
rx_frame = gmii_sink.recv()
assert rx_frame.data[0:8] == bytearray(
b'\x55\x55\x55\x55\x55\x55\x55\xD5')
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(rx_frame.data[8:])
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert len(eth_frame.payload.data) == 46
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame.eth_src_mac
assert eth_frame.eth_type == test_frame.eth_type
assert eth_frame.payload.data.index(test_frame.payload.data) == 0
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Parameters
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH > 8)
KEEP_WIDTH = (DATA_WIDTH / 8)
CACHE_ADDR_WIDTH = 2
REQUEST_RETRY_COUNT = 4
REQUEST_RETRY_INTERVAL = 150
REQUEST_TIMEOUT = 400
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_eth_hdr_valid = Signal(bool(0))
s_eth_dest_mac = Signal(intbv(0)[48:])
s_eth_src_mac = Signal(intbv(0)[48:])
s_eth_type = Signal(intbv(0)[16:])
s_eth_payload_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
s_eth_payload_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
s_eth_payload_axis_tvalid = Signal(bool(0))
s_eth_payload_axis_tlast = Signal(bool(0))
s_eth_payload_axis_tuser = Signal(bool(0))
m_eth_payload_axis_tready = Signal(bool(0))
m_eth_hdr_ready = Signal(bool(0))
arp_request_valid = Signal(bool(0))
arp_request_ip = Signal(intbv(0)[32:])
arp_response_ready = Signal(bool(0))
local_mac = Signal(intbv(0)[48:])
local_ip = Signal(intbv(0)[32:])
gateway_ip = Signal(intbv(0)[32:])
subnet_mask = Signal(intbv(0)[32:])
clear_cache = Signal(bool(0))
# Outputs
s_eth_hdr_ready = Signal(bool(0))
s_eth_payload_axis_tready = Signal(bool(0))
m_eth_hdr_valid = Signal(bool(0))
m_eth_dest_mac = Signal(intbv(0)[48:])
m_eth_src_mac = Signal(intbv(0)[48:])
m_eth_type = Signal(intbv(0)[16:])
m_eth_payload_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
m_eth_payload_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
m_eth_payload_axis_tvalid = Signal(bool(0))
m_eth_payload_axis_tlast = Signal(bool(0))
m_eth_payload_axis_tuser = Signal(bool(0))
arp_request_ready = Signal(bool(0))
arp_response_valid = Signal(bool(0))
arp_response_error = Signal(bool(0))
arp_response_mac = Signal(intbv(0)[48:])
# sources and sinks
eth_source_pause = Signal(bool(0))
eth_sink_pause = Signal(bool(0))
eth_source = eth_ep.EthFrameSource()
eth_source_logic = eth_source.create_logic(
clk,
rst,
eth_hdr_ready=s_eth_hdr_ready,
eth_hdr_valid=s_eth_hdr_valid,
eth_dest_mac=s_eth_dest_mac,
eth_src_mac=s_eth_src_mac,
eth_type=s_eth_type,
eth_payload_tdata=s_eth_payload_axis_tdata,
eth_payload_tkeep=s_eth_payload_axis_tkeep,
eth_payload_tvalid=s_eth_payload_axis_tvalid,
eth_payload_tready=s_eth_payload_axis_tready,
eth_payload_tlast=s_eth_payload_axis_tlast,
eth_payload_tuser=s_eth_payload_axis_tuser,
pause=eth_source_pause,
name='eth_source')
eth_sink = eth_ep.EthFrameSink()
eth_sink_logic = eth_sink.create_logic(
clk,
rst,
eth_hdr_ready=m_eth_hdr_ready,
eth_hdr_valid=m_eth_hdr_valid,
eth_dest_mac=m_eth_dest_mac,
eth_src_mac=m_eth_src_mac,
eth_type=m_eth_type,
eth_payload_tdata=m_eth_payload_axis_tdata,
eth_payload_tkeep=m_eth_payload_axis_tkeep,
eth_payload_tvalid=m_eth_payload_axis_tvalid,
eth_payload_tready=m_eth_payload_axis_tready,
eth_payload_tlast=m_eth_payload_axis_tlast,
eth_payload_tuser=m_eth_payload_axis_tuser,
pause=eth_sink_pause,
name='eth_sink')
arp_request_source = axis_ep.AXIStreamSource()
arp_request_source_logic = arp_request_source.create_logic(
clk,
rst,
tdata=(arp_request_ip, ),
tvalid=arp_request_valid,
tready=arp_request_ready,
name='arp_request_source')
arp_response_sink = axis_ep.AXIStreamSink()
arp_response_sink_logic = arp_response_sink.create_logic(
clk,
rst,
tdata=(arp_response_error, arp_response_mac),
tvalid=arp_response_valid,
tready=arp_response_ready,
name='arp_response_sink')
# DUT
if os.system(build_cmd):
raise Exception("Error running build command")
dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench,
clk=clk,
rst=rst,
current_test=current_test,
s_eth_hdr_valid=s_eth_hdr_valid,
s_eth_hdr_ready=s_eth_hdr_ready,
s_eth_dest_mac=s_eth_dest_mac,
s_eth_src_mac=s_eth_src_mac,
s_eth_type=s_eth_type,
s_eth_payload_axis_tdata=s_eth_payload_axis_tdata,
s_eth_payload_axis_tkeep=s_eth_payload_axis_tkeep,
s_eth_payload_axis_tvalid=s_eth_payload_axis_tvalid,
s_eth_payload_axis_tready=s_eth_payload_axis_tready,
s_eth_payload_axis_tlast=s_eth_payload_axis_tlast,
s_eth_payload_axis_tuser=s_eth_payload_axis_tuser,
m_eth_hdr_valid=m_eth_hdr_valid,
m_eth_hdr_ready=m_eth_hdr_ready,
m_eth_dest_mac=m_eth_dest_mac,
m_eth_src_mac=m_eth_src_mac,
m_eth_type=m_eth_type,
m_eth_payload_axis_tdata=m_eth_payload_axis_tdata,
m_eth_payload_axis_tkeep=m_eth_payload_axis_tkeep,
m_eth_payload_axis_tvalid=m_eth_payload_axis_tvalid,
m_eth_payload_axis_tready=m_eth_payload_axis_tready,
m_eth_payload_axis_tlast=m_eth_payload_axis_tlast,
m_eth_payload_axis_tuser=m_eth_payload_axis_tuser,
arp_request_valid=arp_request_valid,
arp_request_ready=arp_request_ready,
arp_request_ip=arp_request_ip,
arp_response_valid=arp_response_valid,
arp_response_ready=arp_response_ready,
arp_response_error=arp_response_error,
arp_response_mac=arp_response_mac,
local_mac=local_mac,
local_ip=local_ip,
gateway_ip=gateway_ip,
subnet_mask=subnet_mask,
clear_cache=clear_cache)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
local_mac.next = 0xDAD1D2D3D4D5
local_ip.next = 0xc0a80165
gateway_ip.next = 0xc0a80101
subnet_mask.next = 0xFFFFFF00
yield clk.posedge
print("test 1: ARP request")
current_test.next = 1
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 1
test_frame.arp_sha = 0x5A5152535455
test_frame.arp_spa = 0xc0a80164
test_frame.arp_tha = 0x000000000000
test_frame.arp_tpa = 0xc0a80165
eth_source.send(test_frame.build_eth())
yield eth_sink.wait()
rx_frame = eth_sink.recv()
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(rx_frame)
assert check_frame.eth_dest_mac == 0x5A5152535455
assert check_frame.eth_src_mac == 0xDAD1D2D3D4D5
assert check_frame.eth_type == 0x0806
assert check_frame.arp_htype == 0x0001
assert check_frame.arp_ptype == 0x0800
assert check_frame.arp_hlen == 6
assert check_frame.arp_plen == 4
assert check_frame.arp_oper == 2
assert check_frame.arp_sha == 0xDAD1D2D3D4D5
assert check_frame.arp_spa == 0xc0a80165
assert check_frame.arp_tha == 0x5A5152535455
assert check_frame.arp_tpa == 0xc0a80164
yield delay(100)
yield clk.posedge
print("test 2: Cached read")
current_test.next = 2
arp_request_source.send([(0xc0a80164, )])
yield arp_response_sink.wait()
err, mac = arp_response_sink.recv().data[0]
assert not err
assert mac == 0x5A5152535455
yield delay(100)
yield clk.posedge
print("test 3: Unached read")
current_test.next = 3
arp_request_source.send([(0xc0a80166, )])
# wait for ARP request packet
yield eth_sink.wait()
rx_frame = eth_sink.recv()
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(rx_frame)
assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF
assert check_frame.eth_src_mac == 0xDAD1D2D3D4D5
assert check_frame.eth_type == 0x0806
assert check_frame.arp_htype == 0x0001
assert check_frame.arp_ptype == 0x0800
assert check_frame.arp_hlen == 6
assert check_frame.arp_plen == 4
assert check_frame.arp_oper == 1
assert check_frame.arp_sha == 0xDAD1D2D3D4D5
assert check_frame.arp_spa == 0xc0a80165
assert check_frame.arp_tha == 0x000000000000
assert check_frame.arp_tpa == 0xc0a80166
# generate response
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x6A6162636465
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 2
test_frame.arp_sha = 0x6A6162636465
test_frame.arp_spa = 0xc0a80166
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
eth_source.send(test_frame.build_eth())
# wait for lookup
yield arp_response_sink.wait()
err, mac = arp_response_sink.recv().data[0]
assert not err
assert mac == 0x6A6162636465
yield delay(100)
yield clk.posedge
print("test 4: Unached read, outside of subnet")
current_test.next = 4
arp_request_source.send([(0x08080808, )])
# wait for ARP request packet
yield eth_sink.wait()
rx_frame = eth_sink.recv()
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(rx_frame)
assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF
assert check_frame.eth_src_mac == 0xDAD1D2D3D4D5
assert check_frame.eth_type == 0x0806
assert check_frame.arp_htype == 0x0001
assert check_frame.arp_ptype == 0x0800
assert check_frame.arp_hlen == 6
assert check_frame.arp_plen == 4
assert check_frame.arp_oper == 1
assert check_frame.arp_sha == 0xDAD1D2D3D4D5
assert check_frame.arp_spa == 0xc0a80165
assert check_frame.arp_tha == 0x000000000000
assert check_frame.arp_tpa == 0xc0a80101
# generate response
test_frame = arp_ep.ARPFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0xAABBCCDDEEFF
test_frame.eth_type = 0x0806
test_frame.arp_htype = 0x0001
test_frame.arp_ptype = 0x0800
test_frame.arp_hlen = 6
test_frame.arp_plen = 4
test_frame.arp_oper = 2
test_frame.arp_sha = 0xAABBCCDDEEFF
test_frame.arp_spa = 0xc0a80101
test_frame.arp_tha = 0xDAD1D2D3D4D5
test_frame.arp_tpa = 0xc0a80165
eth_source.send(test_frame.build_eth())
# wait for lookup
yield arp_response_sink.wait()
err, mac = arp_response_sink.recv().data[0]
assert not err
assert mac == 0xAABBCCDDEEFF
yield delay(100)
yield clk.posedge
print("test 5: Unached read, timeout")
current_test.next = 5
arp_request_source.send([(0xc0a80167, )])
yield arp_response_sink.wait()
err, mac = arp_response_sink.recv().data[0]
assert err
# check for 4 ARP requests
assert eth_sink.count() == 4
while not eth_sink.empty():
rx_frame = eth_sink.recv()
check_frame = arp_ep.ARPFrame()
check_frame.parse_eth(rx_frame)
assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF
assert check_frame.eth_src_mac == 0xDAD1D2D3D4D5
assert check_frame.eth_type == 0x0806
assert check_frame.arp_htype == 0x0001
assert check_frame.arp_ptype == 0x0800
assert check_frame.arp_hlen == 6
assert check_frame.arp_plen == 4
assert check_frame.arp_oper == 1
assert check_frame.arp_sha == 0xDAD1D2D3D4D5
assert check_frame.arp_spa == 0xc0a80165
assert check_frame.arp_tha == 0x000000000000
assert check_frame.arp_tpa == 0xc0a80167
yield delay(100)
yield clk.posedge
print("test 6: Broadcast")
current_test.next = 6
# subnet broadcast
arp_request_source.send([(0xc0a801ff, )])
yield arp_response_sink.wait()
err, mac = arp_response_sink.recv().data[0]
assert not err
assert mac == 0xffffffffffff
# general broadcast
arp_request_source.send([(0xffffffff, )])
yield arp_response_sink.wait()
err, mac = arp_response_sink.recv().data[0]
assert not err
assert mac == 0xffffffffffff
yield delay(100)
raise StopSimulation
return instances()
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
axis_tdata = Signal(intbv(0)[8:])
axis_tvalid = Signal(bool(0))
axis_tlast = Signal(bool(0))
ll_dst_rdy_in_n = Signal(bool(1))
# Outputs
ll_data_out = Signal(intbv(0)[8:])
ll_sof_out_n = Signal(bool(1))
ll_eof_out_n = Signal(bool(1))
ll_src_rdy_out_n = Signal(bool(1))
axis_tready = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=axis_tdata,
tvalid=axis_tvalid,
tready=axis_tready,
tlast=axis_tlast,
fifo=source_queue,
pause=source_pause,
name='source')
sink = ll_ep.LocalLinkSink(clk,
rst,
data_in=ll_data_out,
sof_in_n=ll_sof_out_n,
eof_in_n=ll_eof_out_n,
src_rdy_in_n=ll_src_rdy_out_n,
dst_rdy_out_n=ll_dst_rdy_in_n,
fifo=sink_queue,
pause=sink_pause,
name='sink')
# DUT
dut = dut_axis_ll_bridge(clk, rst, current_test, axis_tdata, axis_tvalid,
axis_tready, axis_tlast, ll_data_out,
ll_sof_out_n, ll_eof_out_n, ll_src_rdy_out_n,
ll_dst_rdy_in_n)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
source_queue.put(
bytearray(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
))
yield clk.posedge
yield ll_eof_out_n.negedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert bytearray(rx_frame) == (
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
yield delay(100)
yield clk.posedge
print("test 2: test packet with pauses")
current_test.next = 2
source_queue.put(
bytearray(
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
))
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
yield ll_eof_out_n.negedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert bytearray(rx_frame) == (
b'\xDA\xD1\xD2\xD3\xD4\xD5' + b'\x5A\x51\x52\x53\x54\x55' +
b'\x80\x00' +
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
)
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
