def run_main(prj):
config_file = 'bag_xbase_logic/specs/logic_parameters.yaml'
specs = read_yaml(config_file)
# lib and cells
temp_lib = specs['temp_lib']
impl_lib = specs['impl_lib']
tb_lib = specs['tb_lib']
cell_name = specs['nand_cell_name']
tb_cell = specs['nand_tb_cell']
# get directories
mdl_dir = specs['model_dir']
# parameters
grid_opts = specs['grid_opts']
sch_params = specs['nand_sch_params']
lay_params = specs['nand_lay_params']
mdl_params = specs['nand_mdl_params']
# testbench sweep parameters
sim_envs = specs['nand_sim_envs']
tb_params = specs['nand_tb_params'].copy()
nand_opts = specs['nand_opts'].copy()
run_dsn = nand_opts['run_dsn']
run_simulation = nand_opts['run_simulation']
run_extraction = nand_opts['run_extraction']
print('generating tdb')
if run_dsn:
generate(prj, temp_lib, impl_lib, cell_name, lay_params, sch_params,
mdl_params, grid_opts, mdl_dir)
if run_dsn and run_extraction:
extract(prj, impl_lib, cell_name)
if run_simulation:
simulate(prj)
def __init__(self,
bprj: BagProject,
spec_file: str = '',
spec_dict: Optional[Mapping[str, Any]] = None,
sch_db: Optional[ModuleDB] = None,
lay_db: Optional[TemplateDB] = None,
extract: bool = False) -> None:
if spec_dict:
params = spec_dict
else:
params = read_yaml(spec_file)
self.params = cast(Dict[str, Any], params)
self._root_dir = Path(self.params['root_dir']).resolve()
self._prj = bprj
if sch_db is None:
self._sch_db = ModuleDB(bprj.tech_info,
self.params['impl_lib'],
prj=bprj)
else:
self._sch_db = sch_db
if lay_db is None:
self._lay_db = TemplateDB(bprj.grid,
self.params['impl_lib'],
prj=bprj)
else:
self._lay_db = lay_db
self.extract = extract
self.data = {} # a dictionary to access package resources
self.designed_params = {} # the parameters after design has been done
self.designed_performance = {
} # the performance metrics that designed params satisfy
def run_main():
verilog_dir = 'verilog_models'
cell_map_fname = 'verilog_cell_map.yaml'
skill_read_fname = 'verilog_cell_list.txt'
lib_name = 'AAAMODEL_QDR_HYBRID3'
lib_loc = 'gen_libs'
view_name = 'systemVerilog'
model_fname = 'verilog.sv'
cell_map = read_yaml(cell_map_fname)
jinja_env = Environment(loader=FileSystemLoader(verilog_dir))
with open(skill_read_fname, 'w') as g:
for cell_name, fname in cell_map.items():
root_dir = os.path.join(lib_loc, lib_name, cell_name, view_name)
os.makedirs(root_dir, exist_ok=True)
content = jinja_env.get_template(fname).render(cell_name=cell_name)
with open(os.path.join(root_dir, model_fname), 'w') as f:
f.write(content)
g.write('%s %s %s\n' % (lib_name, cell_name, view_name))
async def async_generate_liberty(prj: BagProject, lib_config: Mapping[str, Any],
sim_config: Mapping[str, Any], cell_specs: Mapping[str, Any],
fake: bool = False, extract: bool = False,
force_sim: bool = False, force_extract: bool = False,
gen_all_env: bool = False, gen_sch: bool = False,
export_lay: bool = False, log_level: LogLevel = LogLevel.DEBUG
) -> None:
"""Generate liberty file for the given cells.
Parameters
----------
prj: BagProject
BagProject object to be able to generate things
lib_config : Mapping[str, Any]
library configuration dictionary.
sim_config : Mapping[str, Any]
simulation configuration dictionary.
cell_specs : Mapping[str, Any]
cell specification dictionary.
fake : bool
True to generate fake liberty file.
extract : bool
True to run extraction.
force_sim : bool
True to force simulation runs.
force_extract : bool
True to force extraction runs.
gen_all_env : bool
True to generate liberty files for all environments.
gen_sch : bool
True to generate schematics.
export_lay : bool
Use CAD tool to export layout.
log_level : LogLevel
stdout logging level.
"""
gen_specs_file: str = cell_specs['gen_specs_file']
scenario: str = cell_specs.get('scenario', '')
gen_specs: Mapping[str, Any] = read_yaml(gen_specs_file)
impl_lib: str = gen_specs['impl_lib']
impl_cell: str = gen_specs['impl_cell']
lay_cls: str = gen_specs['lay_class']
dut_params: Mapping[str, Any] = gen_specs['params']
name_prefix: str = gen_specs.get('name_prefix', '')
name_suffix: str = gen_specs.get('name_suffix', '')
gen_root_dir: Path = Path(gen_specs['root_dir'])
lib_root_dir = gen_root_dir / 'lib_gen'
sim_precision: int = sim_config['precision']
dsn_options = dict(
extract=extract,
force_extract=force_extract,
gen_sch=gen_sch,
log_level=log_level,
)
log_file = str(lib_root_dir / 'lib_gen.log')
sim_db = prj.make_sim_db(lib_root_dir / 'dsn', log_file, impl_lib, dsn_options=dsn_options,
force_sim=force_sim, precision=sim_precision, log_level=log_level)
dut = await sim_db.async_new_design(impl_cell, lay_cls, dut_params, export_lay=export_lay,
name_prefix=name_prefix, name_suffix=name_suffix)
environments: Mapping[str, Any] = lib_config['environments']
nom_voltage_type: str = environments['nom_voltage_type']
name_format: str = environments['name_format']
voltage_precision: int = environments['voltage_precision']
sim_env_list: List[Mapping[str, Any]] = environments['sim_envs']
if not gen_all_env:
sim_env_list = [sim_env_list[0]]
voltage_fmt = '{:.%df}' % voltage_precision
lib_file_base_name = f'{impl_cell}_{scenario}' if scenario else impl_cell
for sim_env_config in sim_env_list:
sim_env: str = sim_env_config['sim_env']
voltages: Mapping[str, float] = sim_env_config['voltages']
vstr_table = {k: voltage_fmt.format(v).replace('.', 'p') for k, v in voltages.items()}
sim_env_name = name_format.format(sim_env=sim_env, **vstr_table)
lib_file_name = f'{lib_file_base_name}_{sim_env_name}'
cur_lib_config = dict(**lib_config)
cur_lib_config.pop('environments')
# setup lib config
temperature = get_corner_temp(sim_env)[1]
env_config = dict(
name=sim_env_name,
bag_name=sim_env,
process=1.0,
temperature=temperature,
voltage=voltages[nom_voltage_type],
)
cur_lib_config['voltages'] = voltages
cur_lib_config['sim_envs'] = [env_config]
lib = Library(f'{impl_cell}_{sim_env_name}', cur_lib_config)
out_file = gen_root_dir / f'{lib_file_name}.lib'
lib_data, mm_specs, cur_work_dir = get_cell_info(lib, impl_cell, cell_specs,
lib_root_dir, voltage_fmt)
mm_specs['fake'] = fake
mm_specs['sim_env_name'] = sim_env_name
for key in ['tran_tbm_specs', 'buf_params', 'in_cap_search_params', 'out_cap_search_params',
'seq_search_params', 'seq_delay_thres']:
mm_specs[key] = sim_config[key]
mm = sim_db.make_mm(LibertyCharMM, mm_specs)
sim_db.log(f'Characterizing {lib_file_name}.lib')
char_results = await sim_db.async_simulate_mm_obj('lib_char', cur_work_dir, dut, mm)
pin_data = char_results.data
_add_cell(lib, lib_data, pin_data)
lib.generate(out_file)