def run_test(db: TemplateDB, lay_list: List[Tuple[TemplateBase, str]], fpath_list: List[Path]) -> None: for fpath in fpath_list: print(f'creating layout from file: {fpath.name}') specs = read_yaml(fpath) lay_cls = cast(Type[TemplateBase], import_class(specs['lay_class'])) params = specs['params'] master = db.new_template(lay_cls, params=params) lay_list.append((master, fpath.stem))
def run_main(prj: BagProject, gen_sch: bool = True, gen_cdl: bool = True, run_lvs: bool = True) \ -> None: lib_name = 'AAA_XBASE_TEST' fname = '00_mom_cap.yaml' impl_cell = 'MOMCap_core' fname_cdl = 'pvs_run/lvs_run_dir/' + lib_name + '/' + impl_cell + '/schematic.net' params = read_yaml(Path('specs_test', 'xbase', fname)) db = TemplateDB(prj.grid, lib_name, prj=prj) print('creating new template') master = db.new_template(MOMCapCore, params) print('creating batch layout') # db.batch_layout([(master, '')], DesignOutput.LAYOUT) db.batch_layout([(master, impl_cell)], DesignOutput.LAYOUT) print('done') if gen_sch or gen_cdl: sch_db = ModuleDB(prj.tech_info, lib_name, prj=prj) sch_master = sch_db.new_master(xbase__momcap_core, master.sch_params) cv_info_list = [] print('creating schematic') sch_db.batch_schematic([(sch_master, impl_cell)], cv_info_out=cv_info_list) print('schematic creation done') if gen_cdl: print('creating CDL netlist') sch_db.batch_schematic([(sch_master, impl_cell)], output=DesignOutput.CDL, fname=fname_cdl, cv_info_list=cv_info_list) print('netlist creation done') if run_lvs: print('Running LVS ...') lvs_passed, lvs_log = prj.run_lvs(lib_name, impl_cell, netlist=fname_cdl) print('LVS log file:' + lvs_log) if lvs_passed: print('LVS passed!') else: print('LVS failed :(')