def _setUpTest(self):
choices_mod = ChoicesModifier(self.genThread)
# TODO(Noah): Remove the restriction on SEW when a mechanism to skip instructions with
# illegal vector layouts is implemented. For now, ensure vector element width is set to no
# more than 32 bits.
choice_weights = {
'0x0': 10,
'0x1': 10,
'0x2': 10,
'0x3': 0,
'0x4': 0,
'0x5': 0,
'0x6': 0,
'0x7': 0
}
choices_mod.modifyRegisterFieldValueChoices('vtype.VSEW',
choice_weights)
# Ensure vector register group size is no more than 4, as larger values are not legal for
# widening and narrowing instructions
vlmul_choice_weights = {
'0x0': 10,
'0x1': 10,
'0x2': 10,
'0x3': 0,
'0x4': 0,
'0x5': 10,
'0x6': 10,
'0x7': 10
}
choices_mod.modifyRegisterFieldValueChoices('vtype.VLMUL',
vlmul_choice_weights)
choices_mod.commitSet()
def gen_thread_initialization(gen_thread):
# when satp csr width is 32 bits then Sv32 is only paging mode possible...
satp_info = gen_thread.getRegisterInfo("satp",
gen_thread.getRegisterIndex("satp"))
rv32 = satp_info["Width"] == 32
choices_mod = ChoicesModifier(gen_thread)
if rv32:
# Sv32 only choices...
choices_mod.modifyPagingChoices("Page size#4K granule#S#stage 1", {
"4K": 10,
"4M": 10
})
else:
# Sv48 otherwise...
choices_mod.modifyPagingChoices(
"Page size#4K granule#S#stage 1",
{
"4K": 10,
"2M": 10,
"1G": 0,
"512G": 0
},
)
choices_mod.commitSet()
def generate(self, **kwargs):
page_fault_mod = PageFaultModifier(
self.genThread, self.getGlobalState("AppRegisterWidth")
)
page_fault_mod.apply(**{"All": 1})
# The PageFaultModifier alters the page size choices, so we need to
# set the desired values after applying the page fault modifications
choices_mod = ChoicesModifier(self.genThread)
satp_info = self.getRegisterInfo("satp", self.getRegisterIndex("satp"))
if satp_info["Width"] == 32:
choices_mod.modifyPagingChoices(
"Page size#4K granule#S#stage 1", {"4K": 1, "4M": 10}
)
else:
choices_mod.modifyPagingChoices(
"Page size#4K granule#S#stage 1",
{"4K": 1, "2M": 10, "1G": 10, "512G": 10},
)
choices_mod.commitSet()
instruction_list = ("JAL##RISCV", "JALR##RISCV")
for _ in range(RandomUtils.random32(2, 5)):
self.genInstruction(self.choice(instruction_list))
page_fault_mod.revert()
if self.queryExceptionRecordsCount(1) != 0:
self.error("Unexpected instruction access fault.")
def gen_thread_initialization(gen_thread):
satp_info = gen_thread.getRegisterInfo("satp",
gen_thread.getRegisterIndex("satp"))
rv32 = satp_info["Width"] == 32
choices_mod = ChoicesModifier(gen_thread)
# Make the pages small, so it is easy to generate a mapping that crosses
# page boundaries
if rv32:
choices_mod.modifyPagingChoices("Page size#4K granule#S#stage 1", {
"4K": 25,
"4M": 25
})
else:
choices_mod.modifyPagingChoices(
"Page size#4K granule#S#stage 1",
{
"4K": 25,
"2M": 25,
"1G": 25,
"512G": 25
},
)
choices_mod.commitSet()
def _setUpTest(self):
# Ensure vector element size is set to 16 bits and vector register
# group size is set to 1
choices_mod = ChoicesModifier(self.genThread)
vsew_choice_weights = {
"0x0": 0,
"0x1": 10,
"0x2": 0,
"0x3": 0,
"0x4": 0,
"0x5": 0,
"0x6": 0,
"0x7": 0,
}
choices_mod.modifyRegisterFieldValueChoices(
"vtype.VSEW", vsew_choice_weights
)
vlmul_choice_weights = {
"0x0": 10,
"0x1": 0,
"0x2": 0,
"0x3": 0,
"0x4": 0,
"0x5": 0,
"0x6": 0,
"0x7": 0,
}
choices_mod.modifyRegisterFieldValueChoices(
"vtype.VLMUL", vlmul_choice_weights
)
choices_mod.commitSet()
self._initializeVectorRegisters()
def _setUpTest(self):
choices_mod = ChoicesModifier(self.genThread)
vsew_choice_weights = {
"0x0": 10,
"0x1": 10,
"0x2": 10,
"0x3": 0,
"0x4": 0,
"0x5": 0,
"0x6": 0,
"0x7": 0,
}
choices_mod.modifyRegisterFieldValueChoices("vtype.VSEW",
vsew_choice_weights)
# Ensure vector register group size is no more than 4, as larger values
# are not legal for widening and narrowing instructions
vlmul_choice_weights = {
"0x0": 10,
"0x1": 10,
"0x2": 10,
"0x3": 0,
"0x4": 0,
"0x5": 10,
"0x6": 10,
"0x7": 10,
}
choices_mod.modifyRegisterFieldValueChoices("vtype.VLMUL",
vlmul_choice_weights)
choices_mod.commitSet()
def _setUpTest(self):
# Allowing fractional VLMULs and any valid VSEW values
choices_mod = ChoicesModifier(self.genThread)
vsew_choice_weights = {
'0x0': 0,
'0x1': 10,
'0x2': 10,
'0x3': 10,
'0x4': 0,
'0x5': 0,
'0x6': 0,
'0x7': 0
}
choices_mod.modifyRegisterFieldValueChoices('vtype.VSEW',
vsew_choice_weights)
vlmul_choice_weights = {
'0x0': 10,
'0x1': 0,
'0x2': 0,
'0x3': 0,
'0x4': 0,
'0x5': 10,
'0x6': 10,
'0x7': 10
}
choices_mod.modifyRegisterFieldValueChoices('vtype.VLMUL',
vlmul_choice_weights)
choices_mod.commitSet()
(self._mRegIndex1,
self._mRegIndex2) = self.getRandomRegisters(2, 'VECREG', exclude='0')
self._initializeVectorRegister('v%d' % self._mRegIndex1)
self._initializeVectorRegister('v%d' % self._mRegIndex2)
def _setUpTest(self):
# Ensure vector element size is set to 32 bits and vector register group size is set to 1
choices_mod = ChoicesModifier(self.genThread)
vsew_choice_weights = {
'0x0': 0,
'0x1': 0,
'0x2': 10,
'0x3': 0,
'0x4': 0,
'0x5': 0,
'0x6': 0,
'0x7': 0
}
choices_mod.modifyRegisterFieldValueChoices('vtype.VSEW',
vsew_choice_weights)
vlmul_choice_weights = {
'0x0': 10,
'0x1': 0,
'0x2': 0,
'0x3': 0,
'0x4': 0,
'0x5': 0,
'0x6': 0,
'0x7': 0
}
choices_mod.modifyRegisterFieldValueChoices('vtype.VLMUL',
vlmul_choice_weights)
choices_mod.commitSet()
(self._mRegIndex1,
self._mRegIndex2) = self.getRandomRegisters(2, 'VECREG', exclude='0')
self._mElemVals1 = self._initializeVectorRegister('v%d' %
self._mRegIndex1)
self._mElemVals2 = self._initializeVectorRegister('v%d' %
self._mRegIndex2)
def _setUpTest(self):
# Ensure vector element size is set to 16 bits and vector register group size is set to 1
choices_mod = ChoicesModifier(self.genThread)
vsew_choice_weights = {
'0x0': 0,
'0x1': 10,
'0x2': 0,
'0x3': 0,
'0x4': 0,
'0x5': 0,
'0x6': 0,
'0x7': 0
}
choices_mod.modifyRegisterFieldValueChoices('vtype.VSEW',
vsew_choice_weights)
vlmul_choice_weights = {
'0x0': 10,
'0x1': 0,
'0x2': 0,
'0x3': 0,
'0x4': 0,
'0x5': 0,
'0x6': 0,
'0x7': 0
}
choices_mod.modifyRegisterFieldValueChoices('vtype.VLMUL',
vlmul_choice_weights)
choices_mod.commitSet()
self._initializeVectorRegisters()
def _setUpTest(self):
# Allowing fractional VLMULs and any valid VSEW values
choices_mod = ChoicesModifier(self.genThread)
vsew_choice_weights = {
"0x0": 0,
"0x1": 10,
"0x2": 10,
"0x3": 10,
"0x4": 0,
"0x5": 0,
"0x6": 0,
"0x7": 0,
}
choices_mod.modifyRegisterFieldValueChoices("vtype.VSEW",
vsew_choice_weights)
vlmul_choice_weights = {
"0x0": 10,
"0x1": 0,
"0x2": 0,
"0x3": 0,
"0x4": 0,
"0x5": 10,
"0x6": 10,
"0x7": 10,
}
choices_mod.modifyRegisterFieldValueChoices("vtype.VLMUL",
vlmul_choice_weights)
choices_mod.commitSet()
(self._mRegIndex1,
self._mRegIndex2) = self.getRandomRegisters(2, "VECREG", exclude="0")
self._initializeVectorRegister("v%d" % self._mRegIndex1)
self._initializeVectorRegister("v%d" % self._mRegIndex2)
def gen_thread_initialization(gen_thread):
(delegate_opt, valid) = gen_thread.getOption("DelegateExceptions")
if valid and delegate_opt == 1:
# enable exception delegation for some portion of the generated tests...
delegation_enables = ChoicesModifier(gen_thread)
weightDict = {"0x0": 0, "0x1": 50}
delegation_enables.modifyRegisterFieldValueChoices(
"medeleg.Load page fault", weightDict)
delegation_enables.modifyRegisterFieldValueChoices(
"medeleg.Store/AMO page fault", weightDict)
delegation_enables.commitSet()
def generate(self, **kwargs):
choices_mod = ChoicesModifier(self.genThread)
for _ in range(10):
# Generate instructions with the default choices settings
# except for the paging choices for "Page size#4K
# granule#S#stage 1" which was set before this generate was called
# via the GenThreadInitialization below.
for _ in range(20):
if self.getGlobalState("AppRegisterWidth") == 32:
instr = self.pickWeighted(RV32_G_instructions)
else:
instr = self.pickWeighted(RV_G_instructions)
self.genInstruction(instr)
# Modify the choices settings
choices_mod.modifyOperandChoices(
"Rounding mode",
{"RNE": 0, "RTZ": 0, "RDN": 50, "RUP": 0, "RMM": 0, "DYN": 50},
)
choices_mod.modifyOperandChoices(
"Read after write address reuse", {"No reuse": 50, "Reuse": 50}
)
choices_mod.commitSet()
# generate instructions
for _ in range(20):
if self.getGlobalState("AppRegisterWidth") == 32:
instr_mix = {RV32F_map: 10, LDST32_All_map: 10}
else:
instr_mix = {ALU_Float_All_map: 10, LDST_All_map: 10}
instr = self.pickWeighted(instr_mix)
self.genInstruction(instr)
# undo the choices settings - revert back to prior
choices_mod.revert()
def _setUpTest(self):
if RandomUtils.random32(0, 1) == 1:
choices_mod = ChoicesModifier(self.genThread)
choice_weights = {"Aligned": 80, "Unaligned": 20}
choices_mod.modifyOperandChoices("Data alignment", choice_weights)
choices_mod.commitSet()
self._mUnalignedAllowed = True
def gen_thread_initialization(gen_thread):
(delegate_opt, valid) = gen_thread.getOption("DelegateExceptions")
if valid and delegate_opt == 1:
delegation_enables = ChoicesModifier(gen_thread)
weightDict = {"0x0": 0, "0x1": 50}
delegation_enables.modifyRegisterFieldValueChoices(
'medeleg.Breakpoint', weightDict)
delegation_enables.modifyRegisterFieldValueChoices(
'medeleg.Environment call from U-mode', weightDict)
delegation_enables.commitSet()
(paging_opt, valid) = gen_thread.getOption("PagingDisabled")
if valid and paging_opt == 1:
gen_thread.initializeRegister(name='satp', value=0, field='MODE')
def _generateSystemCallParameters(self):
params = {}
function = self.choice(("SwitchPrivilegeLevel", None))
if function is not None:
params["Function"] = function
priv_level = self.choice(("U", "S", "M", 0, 1, 3, "Random", None))
if priv_level is not None:
params["PrivilegeLevel"] = priv_level
target_addr = self._generateTargetAddress(priv_level)
if target_addr is not None:
params["TargetAddr"] = target_addr
# Don't skip validation if no target address is specified
skip_addr_validation = self.choice((0, 1, None))
if (skip_addr_validation is not None) and (
("TargetAddr" in params) or (skip_addr_validation != 1)):
params["SkipAddrValidation"] = skip_addr_validation
if RandomUtils.random32(0, 4) == 4:
choices_mod = ChoicesModifier(self.genThread)
choices_mod.modifyPagingChoices(
"Page Allocation Scheme",
{
"RandomFreeAlloc": 0,
"FlatMapAlloc": 10
},
)
params["AddrChoicesModID"] = choices_mod.registerSet()
# for param_name in ('InterruptMask', 'SUM', 'MXR', 'MPRV'):
for param_name in ("InterruptMask", ):
param_val = self.choice((0, 1, "Same", "Flip", "Random", None))
if param_val is not None:
params[param_name] = param_val
return params
def generate(self, **kwargs):
choices_mod = ChoicesModifier(self.genThread)
for _ in range(10):
# Generate instructions with the default choices settings
# except for the paging choices for "Page size#4K
# granule#S#stage 1" which was set before this generate was called
# via the GenThreadInitialization below.
self._gen_rv_g_instructions()
# Modify the choices settings
choices_mod.modifyOperandChoices(
"Rounding mode",
{
"RNE": 0,
"RTZ": 0,
"RDN": 50,
"RUP": 0,
"RMM": 0,
"DYN": 50
},
)
choices_mod.modifyOperandChoices("Read after write address reuse",
{
"No reuse": 50,
"Reuse": 50
})
choices_mod.commitSet()
# generate instructions
self._gen_data_processing_and_load_store_instructions()
# undo the choices settings - revert back to prior
choices_mod.revert()
def _generateSystemCallParameters(self):
params = {}
function = self.choice(('SwitchPrivilegeLevel', None))
if function is not None:
params['Function'] = function
priv_level = self.choice(('U', 'S', 'M', 0, 1, 3, 'Random', None))
if priv_level is not None:
params['PrivilegeLevel'] = priv_level
target_addr = self._generateTargetAddress(priv_level)
if (target_addr is not None):
params['TargetAddr'] = target_addr
skip_addr_validation = self.choice((0, 1, None))
if skip_addr_validation is not None:
# Don't skip validation if no target address is specified
if ('TargetAddr' in params) or (skip_addr_validation != 1):
params['SkipAddrValidation'] = skip_addr_validation
if RandomUtils.random32(0, 4) == 4:
choices_mod = ChoicesModifier(self.genThread)
choices_mod.modifyPagingChoices('Page Allocation Scheme', {
'RandomFreeAlloc': 0,
'FlatMapAlloc': 10
})
params['AddrChoicesModID'] = choices_mod.registerSet()
# TODO(Noah): Add testing for SUM, MXR and MPRV when support for changing those fields is
# established.
#for param_name in ('InterruptMask', 'SUM', 'MXR', 'MPRV'):
for param_name in ('InterruptMask', ):
param_val = self.choice((0, 1, 'Same', 'Flip', 'Random', None))
if param_val is not None:
params[param_name] = param_val
return params
def gen_thread_initialization(gen_thread):
choices_mod = ChoicesModifier(gen_thread)
# Make the pages small, so it is easy to generate a mapping that crosses
# page boundaries
choices_mod.modifyPagingChoices('Page size#4K granule#S#stage 1',
{'4K': 25, '2M': 25, '1G': 25, '512G': 25})
choices_mod.commitSet()
def gen_thread_initialization(gen_thread):
choices_mod = ChoicesModifier(gen_thread)
# Increase the likelihood of using GPRs x10, x11, x12 and x13 by
# increasing the weighting. The default weighting in the
# operand_choices.xml file is 10 for each GPR.
choices_mod.modifyOperandChoices("GPRs", {"x10": 40, "x11": 40, "x12": 60, "x13": 60})
choices_mod.commitSet()
def _setUpTest(self):
choices_mod = ChoicesModifier(self.genThread)
# TODO(Noah): Remove the restriction on SEW when a mechanism to skip instructions with
# illegal vector layouts is implemented. For now, SEW = 64 ensures all applicable
# instructions can be legally generated.
choice_weights = {'0x0': 0, '0x1': 0, '0x2': 0, '0x3': 10, '0x4': 0, '0x5': 0, '0x6': 0, '0x7': 0}
choices_mod.modifyRegisterFieldValueChoices('vtype.VSEW', choice_weights)
choices_mod.commitSet()
def gen_thread_initialization(gen_thread):
(delegate_opt, valid) = gen_thread.getOption("DelegateExceptions")
if valid and delegate_opt == 1:
delegation_enables = ChoicesModifier(gen_thread)
weightDict = { "0x0":0, "0x1":50 }
delegation_enables.modifyRegisterFieldValueChoices( 'medeleg.Instruction address misaligned', weightDict )
delegation_enables.commitSet()
(paging_opt, valid) = gen_thread.getOption("PagingDisabled")
if valid and paging_opt == 1:
gen_thread.initializeRegister(name='satp', value=0, field='MODE')
def gen_thread_initialization(gen_thread):
gen_choices_mod = ChoicesModifier(gen_thread)
gen_choices_mod.modifyGeneralChoices(
"Privilege level switch to lower or same level",
{
"ECALL": 10,
"xRET": 0
},
)
gen_choices_mod.commitSet()
traps_modifier = TrapsRedirectModifier(gen_thread)
(delegate_opt, valid) = gen_thread.getOption("DelegateExceptions")
if valid and delegate_opt == 1:
traps_modifier.update(ExceptionCode="Breakpoint",
TrapChoice="Delegate",
Weight=50)
traps_modifier.update(
ExceptionCode="Environment call from U-mode",
TrapChoice="Delegate",
Weight=50,
)
traps_modifier.update(
ExceptionCode="Environment call from S-mode",
TrapChoice="Delegate",
Weight=50,
)
have_mods = True
(redirect_opt, valid) = gen_thread.getOption("RedirectTraps")
if valid and redirect_opt == 1:
traps_modifier.update(ExceptionCode="Breakpoint",
TrapChoice="Redirect",
Weight=100)
traps_modifier.update(
ExceptionCode="Environment call from U-mode",
TrapChoice="Redirect",
Weight=50,
)
traps_modifier.update(
ExceptionCode="Environment call from S-mode",
TrapChoice="Redirect",
Weight=50,
)
have_mods = True
traps_modifier.commit()
(paging_opt, valid) = gen_thread.getOption("PagingDisabled")
if valid and paging_opt == 1:
gen_thread.initializeRegister(name="satp", value=0, field="MODE")
def gen_thread_initialization(gen_thread):
choices_mod = ChoicesModifier(gen_thread)
# Increase the likelihood of using GPRs x10, x11, x12 and x13 by
# increasing the weighting. The default weighting in the operand_choices.xml
# file is 10 for each GPR.
choices_mod.modifyPagingChoices("Page size#4K granule#S#stage 1", {
"4K": 10,
"2M": 10,
"1G": 0,
"512G": 0
})
choices_mod.commitSet()
def _setUpTest(self):
# Ensure vector element size is set to 32 bits and vector register
# group size is set to 1
choices_mod = ChoicesModifier(self.genThread)
vsew_choice_weights = {
"0x0": 0,
"0x1": 0,
"0x2": 10,
"0x3": 0,
"0x4": 0,
"0x5": 0,
"0x6": 0,
"0x7": 0,
}
choices_mod.modifyRegisterFieldValueChoices("vtype.VSEW",
vsew_choice_weights)
vlmul_choice_weights = {
"0x0": 10,
"0x1": 0,
"0x2": 0,
"0x3": 0,
"0x4": 0,
"0x5": 0,
"0x6": 0,
"0x7": 0,
}
choices_mod.modifyRegisterFieldValueChoices("vtype.VLMUL",
vlmul_choice_weights)
choices_mod.commitSet()
(self._mRegIndex1,
self._mRegIndex2) = self.getRandomRegisters(2, "VECREG", exclude="0")
self._mElemVals1 = self._initializeVectorRegister("v%d" %
self._mRegIndex1)
self._mElemVals2 = self._initializeVectorRegister("v%d" %
self._mRegIndex2)
def _setUpTest(self):
choices_mod = ChoicesModifier(self.genThread)
choice_weights = {
"0x0": 0,
"0x1": 0,
"0x2": 0,
"0x3": 10,
"0x4": 0,
"0x5": 0,
"0x6": 0,
"0x7": 0,
}
choices_mod.modifyRegisterFieldValueChoices("vtype.VSEW",
choice_weights)
choices_mod.commitSet()
def _setUpTest(self):
choices_mod = ChoicesModifier(self.genThread)
# Ensure element size is at least 32 because smaller sizes are not legal
choice_weights = {
"0x0": 0,
"0x1": 0,
"0x2": 10,
"0x3": 10,
"0x4": 0,
"0x5": 0,
"0x6": 0,
"0x7": 0,
}
# 64-bit elements are illegal in 32-bit mode for vector atomic instructions
if self.getGlobalState("AppRegisterWidth") == 32:
choice_weights["0x3"] = 0
choices_mod.modifyRegisterFieldValueChoices("vtype.VSEW",
choice_weights)
choices_mod.commitSet()
