Пример #1
0
    def generate(self, **kargs):

        for _ in range(100):

            # define a single level instruction tree and choose an instruction
            random_iset1 = {
                "FMADD.S##RISCV": 10,
                "FMAX.S##RISCV": 20,
                "FMIN.S##RISCV": 30,
            }

            the_instruction = self.pickWeighted(random_iset1)
            self.genInstruction(the_instruction)

            # define a multilevel instruction tree and choose an instruction
            random_iset2 = {
                "ADD##RISCV": 10,
                # "SD##RISCV":10,
                "BEQ##RISCV": 10,
                "FMADD.D##RISCV": 10,
            }

            random_iset3 = {
                "JAL##RISCV": 70,
                "LUI##RISCV": 50,
                "FENCE##RISCV": 30,
                "ORI##RISCV": 10,
            }

            iset1_map = InstructionMap("random_iset1", random_iset1)
            iset2_map = InstructionMap("random_iset2", random_iset2)
            iset3_map = InstructionMap("random_iset3", random_iset3)

            random_itree = {iset1_map: 10, iset2_map: 20, iset3_map: 10}

            # pick an instruction from the hierarchical instruction tree
            picked_instr = self.pickWeighted(random_itree)
            self.genInstruction(picked_instr)

            # a hierarchical instruction tree using the maps in
            # py/DV/riscv/trees/instruction_tree.py
            random_itree = {
                LDST_All_map: 10,
                ALU_Float_Double_map: 10,
                ALU_Int_All_map: 10,
            }

            if self.getGlobalState("AppRegisterWidth") == 32:
                random_itree = {
                    LDST32_All_map: 10,
                    ALU_Float_Double_map: 10,
                    ALU_Int32_All_map: 10,
                }

            picked_instr = self.pickWeighted(random_itree)
            self.genInstruction(picked_instr)
Пример #2
0
    'VQMACC.VX##RISCV': 10,
    'VQMACCSU.VV##RISCV': 10,
    'VQMACCSU.VX##RISCV': 10,
    'VQMACCU.VV##RISCV': 10,
    'VQMACCU.VX##RISCV': 10,
    'VQMACCUS.VX##RISCV': 10,
    'VMERGE/VMV.VI##RISCV': 10,  # ISA has vmerge.vim
    'VMERGE/VMV.VV##RISCV': 10,  # ISA has vmerge.vvm
    'VMERGE/VMV.VX##RISCV': 10,  # ISA has vmerge.vxm
    # These move instructions are missing from v_instructions.xml.  Appears generation was corrupted.
    # vmv.v.v
    # vmv.v.x
    # vmv.v.i
}

vinteger_map = InstructionMap('vinteger_instructions', vinteger_instructions)

vpermutation_instructions = {
    'VMV.S.X##RISCV': 10,
    'VMV.X.S##RISCV': 10,
    'VFMV.F.S##RISCV': 10,
    'VFMV.S.F##RISCV': 10,
    'VSLIDEUP.VI##RISCV': 10,
    'VSLIDEUP.VX##RISCV': 10,
    'VSLIDEDOWN.VI##RISCV': 10,
    'VSLIDEDOWN.VX##RISCV': 10,
    'VSLIDE1DOWN.VX##RISCV': 10,
    'VSLIDE1UP.VX##RISCV': 10,
    'VRGATHER.VI##RISCV': 10,
    'VRGATHER.VV##RISCV': 10,
    'VRGATHER.VX##RISCV': 10,
Пример #3
0
    "SLLI#RV32I#RISCV": 10,
    "SLT##RISCV": 10,
    "SLTI##RISCV": 10,
    "SLTIU##RISCV": 10,
    "SLTU##RISCV": 10,
    "SRA##RISCV": 10,
    "SRAI#RV32I#RISCV": 10,
    "SRL##RISCV": 10,
    "SRLI#RV32I#RISCV": 10,
    "SUB##RISCV": 10,
    "SW##RISCV": 10,
    "XOR##RISCV": 10,
    "XORI##RISCV": 10,
}

RV32I_map = InstructionMap("RV32I_instructions", RV32I_instructions)

RV64I_instructions = {
    "ADDIW##RISCV": 10,
    "ADDW##RISCV": 10,
    "LD##RISCV": 10,
    "LWU##RISCV": 10,
    "SD##RISCV": 10,
    "SLLI#RV64I#RISCV": 10,
    "SLLIW##RISCV": 10,
    "SLLW##RISCV": 10,
    "SRAI#RV64I#RISCV": 10,
    "SRAIW##RISCV": 10,
    "SRAW##RISCV": 10,
    "SRLI#RV64I#RISCV": 10,
    "SRLIW##RISCV": 10,
Пример #4
0
    'SLLI#RV32I#RISCV': 10,
    'SLT##RISCV': 10,
    'SLTI##RISCV': 10,
    'SLTIU##RISCV': 10,
    'SLTU##RISCV': 10,
    'SRA##RISCV': 10,
    'SRAI#RV32I#RISCV': 10,
    'SRL##RISCV': 10,
    'SRLI#RV32I#RISCV': 10,
    'SUB##RISCV': 10,
    'SW##RISCV': 10,
    'XOR##RISCV': 10,
    'XORI##RISCV': 10
}

RV32I_map = InstructionMap('RV32I_instructions', RV32I_instructions)

RV64I_instructions = {
    'ADDIW##RISCV': 10,
    'ADDW##RISCV': 10,
    'LD##RISCV': 10,
    'LWU##RISCV': 10,
    'SD##RISCV': 10,
    'SLLI#RV64I#RISCV': 10,
    'SLLIW##RISCV': 10,
    'SLLW##RISCV': 10,
    'SRAI#RV64I#RISCV': 10,
    'SRAIW##RISCV': 10,
    'SRAW##RISCV': 10,
    'SRLI#RV64I#RISCV': 10,
    'SRLIW##RISCV': 10,
Пример #5
0
    "VQMACCSU.VV##RISCV": 10,
    "VQMACCSU.VX##RISCV": 10,
    "VQMACCU.VV##RISCV": 10,
    "VQMACCU.VX##RISCV": 10,
    "VQMACCUS.VX##RISCV": 10,
    "VMERGE/VMV.VI##RISCV": 10,  # ISA has vmerge.vim
    "VMERGE/VMV.VV##RISCV": 10,  # ISA has vmerge.vvm
    "VMERGE/VMV.VX##RISCV": 10,  # ISA has vmerge.vxm
    # These move instructions are missing from v_instructions.xml.
    # Appears generation was corrupted.
    # vmv.v.v
    # vmv.v.x
    # vmv.v.i
}

vinteger_map = InstructionMap("vinteger_instructions", vinteger_instructions)

vpermutation_instructions = {
    "VMV.S.X##RISCV": 10,
    "VMV.X.S##RISCV": 10,
    "VFMV.F.S##RISCV": 10,
    "VFMV.S.F##RISCV": 10,
    "VSLIDEUP.VI##RISCV": 10,
    "VSLIDEUP.VX##RISCV": 10,
    "VSLIDEDOWN.VI##RISCV": 10,
    "VSLIDEDOWN.VX##RISCV": 10,
    "VSLIDE1DOWN.VX##RISCV": 10,
    "VSLIDE1UP.VX##RISCV": 10,
    "VRGATHER.VI##RISCV": 10,
    "VRGATHER.VV##RISCV": 10,
    "VRGATHER.VX##RISCV": 10,