def visit_Load(self, op):
addr = self.run(op.idx)
mem = self.state.get_mem(addr, op.size / 8,
isinstance(op.endian, bil.LittleEndian))
if len(mem) == 0:
raise MemoryException(addr)
return ConcreteBitVector(op.size, int(mem.encode('hex'), 16))
def new_state_for_clnum(clnum, include_flags=True):
flags = cpu_flags if include_flags else []
flagvalues = [0 for f in flags]
varnames = registers + flags
initial_regs = trace.db.fetch_registers(clnum)
varvals = initial_regs + flagvalues
varvals = map(lambda x: ConcreteBitVector(regsize, x), varvals)
initial_vars = dict(zip(varnames, varvals))
initial_mem_get = partial(trace.fetch_raw_memory, clnum)
return State(initial_vars, initial_mem_get)
def visit_SIGNED(self, op):
return ConcreteBitVector(op.size, int(self.run(op.expr)))
def visit_SLE(self, op):
return ConcreteBitVector(
1, 1 if self.run(op.lhs).sle(self.run(op.rhs)) else 0)
def visit_LE(self, op):
return ConcreteBitVector(
1, 1 if self.run(op.lhs) <= self.run(op.rhs) else 0)
def visit_Move(self, op):
if isinstance(op.var.type, bil.Imm):
self.state[op.var.name] = ConcreteBitVector(
op.var.type.size, int(self.run(op.expr)))
else:
self.run(op.expr) # no need to store Mems
def visit_Unknown(self, op):
return ConcreteBitVector(1, 0)
def visit_Int(self, op):
return ConcreteBitVector(op.size, op.value)