def test_component(self): s = brica1.VirtualTimeSyncScheduler(1.0) ca = brica1.CognitiveArchitecture(s) zero = numpy.zeros(3, dtype=numpy.short) v = numpy.array([1, 2, 3], dtype=numpy.short) CompA = brica1.ConstantComponent() CompB = brica1.PipeComponent() CompC = brica1.NullComponent() ModA = brica1.Module() ModA.add_component("CompA", CompA) ModA.add_component("CompB", CompB) ModA.add_component("CompC", CompC) CompA.set_state("out", v) CompA.make_out_port("out", 3) CompB.make_in_port("in", 3) CompB.connect(CompA, "out", "in") CompB.make_out_port("out", 3) CompB.set_map("in", "out") CompC.make_in_port("in", 3) CompC.connect(CompB, "out", "in") ca.add_submodule("ModA", ModA) self.assertTrue((CompA.get_state("out") == v).all()) self.assertIsNot(CompA.get_state("out"), v) self.assertTrue((CompA.get_out_port("out").buffer == zero).all()) self.assertTrue((CompB.get_in_port("in").buffer == zero).all()) self.assertTrue((CompB.get_out_port("out").buffer == zero).all()) self.assertTrue((CompC.get_in_port("in").buffer == zero).all()) ca.step() self.assertTrue((CompA.get_out_port("out").buffer == v ).all()) self.assertTrue((CompB.get_in_port("in").buffer == zero).all()) self.assertTrue((CompB.get_out_port("out").buffer == zero).all()) self.assertTrue((CompC.get_in_port("in").buffer == zero).all()) ca.step() self.assertTrue((CompA.get_out_port("out").buffer == v ).all()) self.assertTrue((CompB.get_in_port("in").buffer == v ).all()) self.assertTrue((CompB.get_out_port("out").buffer == v ).all()) self.assertTrue((CompC.get_in_port("in").buffer == zero).all()) ca.step() self.assertTrue((CompA.get_out_port("out").buffer == v).all()) self.assertTrue((CompB.get_in_port("in").buffer == v).all()) self.assertTrue((CompB.get_out_port("out").buffer == v).all()) self.assertTrue((CompC.get_in_port("in").buffer == v).all())
def _(bm): s = brica1.VirtualTimeSyncScheduler(1.0) agent = brica1.Agent(s) compA = brica1.ConstantComponent() compB = brica1.NullComponent() mod = brica1.Module(); mod.add_component('compA', compA) mod.add_component('compB', compB) compA.make_out_port('out', 256*256*3) compB.make_in_port('in', 256*256*3) brica1.connect((compA, 'out'), (compB, 'in')) agent.add_submodule('mod', mod) for _ in bm: agent.step()
self.make_in_port("in1", n_in) self.make_out_port("out0", 1) def fire(self): x = self.inputs["in0"] y = self.inputs["in1"] self.results["out0"] = (x == y) # Load iris dataset iris = datasets.load_iris() X = iris.data[:, :2] y = iris.target # Setup data feeder component feeder = brica1.ConstantComponent() feeder.make_out_port("out0", 2) # Setup components svm = SVMComponent(2) svm.fit(X, y) RFC = RandomForestClassifierComponent(2) RFC.fit(X, y) SR = SVMvsRFC_Component(1) # Connect the components brica1.connect((feeder, "out0"), (svm, "in0")) brica1.connect((feeder, "out0"), (RFC, "in0")) brica1.connect((svm, "out0"), (SR, "in0"))
def test_nested(self): s = brica1.VirtualTimeScheduler() ca = brica1.CognitiveArchitecture(s) zero = numpy.zeros(3, dtype=numpy.short) v = numpy.array([1, 2, 3], dtype=numpy.short) CompA = brica1.ConstantComponent() CompB = brica1.PipeComponent() CompC = brica1.NullComponent() CompA.offset = 2.0 CompB.offset = 0.0 CompC.offset = 1.0 CompA.interval = 5.0 CompB.interval = 5.0 CompC.interval = 5.0 ModA = brica1.Module() ModB = brica1.Module() ModC = brica1.Module() SupA = brica1.Module() SupB = brica1.Module() SupC = brica1.Module() Top = brica1.Module() CompA.set_state("out", v) CompA.make_out_port("out", 3) CompB.make_in_port("in", 3) CompB.make_out_port("out", 3) CompB.set_map("in", "out") CompC.make_in_port("in", 3) ModA.make_out_port("out", 3) ModB.make_in_port("in", 3) ModB.make_out_port("out", 3) ModC.make_in_port("in", 3) SupA.make_out_port("out", 3) SupB.make_in_port("in", 3) SupB.make_out_port("out", 3) SupC.make_in_port("in", 3) SupA.add_submodule("ModA", ModA) SupB.add_submodule("ModB", ModB) SupC.add_submodule("ModC", ModC) ModA.add_component("CompA", CompA) ModB.add_component("CompB", CompB) ModC.add_component("CompC", CompC) # Out ports must be aliased inside-out CompA.alias_out_port(ModA, "out", "out") ModA.alias_out_port(SupA, "out", "out") # In ports must be aliased outside-in ModB.alias_in_port(SupB, "in", "in") CompB.alias_in_port(ModB, "in", "in") # Out ports must be aliased inside-out CompB.alias_out_port(ModB, "out", "out") ModB.alias_out_port(SupB, "out", "out") # In ports must be aliased outside-in ModC.alias_in_port(SupC, "in", "in") CompC.alias_in_port(ModC, "in", "in") SupB.connect(SupA, "out", "in") SupC.connect(SupB, "out", "in") Top.add_submodule("SupA", SupA) Top.add_submodule("SupB", SupB) Top.add_submodule("SupC", SupC) ca.add_submodule("Top", Top) self.assertTrue((CompA.get_state("out") == v).all()) self.assertIsNot(CompA.get_state("out"), v) self.assertTrue((CompA.get_out_port("out").buffer == zero).all()) self.assertTrue((CompB.get_in_port("in").buffer == zero).all()) self.assertTrue((CompB.get_out_port("out").buffer == zero).all()) self.assertTrue((CompC.get_in_port("in").buffer == zero).all()) self.assertTrue((ModA.get_out_port("out").buffer == zero).all()) self.assertTrue((ModB.get_in_port("in").buffer == zero).all()) self.assertTrue((ModB.get_out_port("out").buffer == zero).all()) self.assertTrue((ModC.get_in_port("in").buffer == zero).all()) self.assertTrue((SupA.get_out_port("out").buffer == zero).all()) self.assertTrue((SupB.get_in_port("in").buffer == zero).all()) self.assertTrue((SupB.get_out_port("out").buffer == zero).all()) self.assertTrue((SupC.get_in_port("in").buffer == zero).all()) time = ca.step() self.assertTrue((CompA.get_out_port("out").buffer == zero).all()) self.assertTrue((CompB.get_in_port("in").buffer == zero).all()) self.assertTrue((CompB.get_out_port("out").buffer == zero).all()) self.assertTrue((CompC.get_in_port("in").buffer == zero).all()) self.assertTrue((ModA.get_out_port("out").buffer == zero).all()) self.assertTrue((ModB.get_in_port("in").buffer == zero).all()) self.assertTrue((ModB.get_out_port("out").buffer == zero).all()) self.assertTrue((ModC.get_in_port("in").buffer == zero).all()) self.assertTrue((SupA.get_out_port("out").buffer == zero).all()) self.assertTrue((SupB.get_in_port("in").buffer == zero).all()) self.assertTrue((SupB.get_out_port("out").buffer == zero).all()) self.assertTrue((SupC.get_in_port("in").buffer == zero).all()) self.assertEquals(time, 5.0) time = ca.step() self.assertTrue((CompA.get_out_port("out").buffer == zero).all()) self.assertTrue((CompB.get_in_port("in").buffer == zero).all()) self.assertTrue((CompB.get_out_port("out").buffer == zero).all()) self.assertTrue((CompC.get_in_port("in").buffer == zero).all()) self.assertTrue((ModA.get_out_port("out").buffer == zero).all()) self.assertTrue((ModB.get_in_port("in").buffer == zero).all()) self.assertTrue((ModB.get_out_port("out").buffer == zero).all()) self.assertTrue((ModC.get_in_port("in").buffer == zero).all()) self.assertTrue((SupA.get_out_port("out").buffer == zero).all()) self.assertTrue((SupB.get_in_port("in").buffer == zero).all()) self.assertTrue((SupB.get_out_port("out").buffer == zero).all()) self.assertTrue((SupC.get_in_port("in").buffer == zero).all()) self.assertEquals(time, 6.0) time = ca.step() self.assertTrue((CompA.get_out_port("out").buffer == v ).all()) self.assertTrue((CompB.get_in_port("in").buffer == zero).all()) self.assertTrue((CompB.get_out_port("out").buffer == zero).all()) self.assertTrue((CompC.get_in_port("in").buffer == zero).all()) self.assertTrue((ModA.get_out_port("out").buffer == v ).all()) self.assertTrue((ModB.get_in_port("in").buffer == zero).all()) self.assertTrue((ModB.get_out_port("out").buffer == zero).all()) self.assertTrue((ModC.get_in_port("in").buffer == zero).all()) self.assertTrue((SupA.get_out_port("out").buffer == v ).all()) self.assertTrue((SupB.get_in_port("in").buffer == zero).all()) self.assertTrue((SupB.get_out_port("out").buffer == zero).all()) self.assertTrue((SupC.get_in_port("in").buffer == zero).all()) self.assertEquals(time, 7.0) time = ca.step() self.assertTrue((CompA.get_out_port("out").buffer == v ).all()) self.assertTrue((CompB.get_in_port("in").buffer == v ).all()) self.assertTrue((CompB.get_out_port("out").buffer == zero).all()) self.assertTrue((CompC.get_in_port("in").buffer == zero).all()) self.assertTrue((ModA.get_out_port("out").buffer == v ).all()) self.assertTrue((ModB.get_in_port("in").buffer == v ).all()) self.assertTrue((ModB.get_out_port("out").buffer == zero).all()) self.assertTrue((ModC.get_in_port("in").buffer == zero).all()) self.assertTrue((SupA.get_out_port("out").buffer == v ).all()) self.assertTrue((SupB.get_in_port("in").buffer == v ).all()) self.assertTrue((SupB.get_out_port("out").buffer == zero).all()) self.assertTrue((SupC.get_in_port("in").buffer == zero).all()) self.assertEquals(time, 10.0) time = ca.step() self.assertTrue((CompA.get_out_port("out").buffer == v ).all()) self.assertTrue((CompB.get_in_port("in").buffer == v ).all()) self.assertTrue((CompB.get_out_port("out").buffer == zero).all()) self.assertTrue((CompC.get_in_port("in").buffer == zero).all()) self.assertTrue((ModA.get_out_port("out").buffer == v ).all()) self.assertTrue((ModB.get_in_port("in").buffer == v ).all()) self.assertTrue((ModB.get_out_port("out").buffer == zero).all()) self.assertTrue((ModC.get_in_port("in").buffer == zero).all()) self.assertTrue((SupA.get_out_port("out").buffer == v ).all()) self.assertTrue((SupB.get_in_port("in").buffer == v ).all()) self.assertTrue((SupB.get_out_port("out").buffer == zero).all()) self.assertTrue((SupC.get_in_port("in").buffer == zero).all()) self.assertEquals(time, 11.0) time = ca.step() self.assertTrue((CompA.get_out_port("out").buffer == v ).all()) self.assertTrue((CompB.get_in_port("in").buffer == v ).all()) self.assertTrue((CompB.get_out_port("out").buffer == zero).all()) self.assertTrue((CompC.get_in_port("in").buffer == zero).all()) self.assertTrue((ModA.get_out_port("out").buffer == v ).all()) self.assertTrue((ModB.get_in_port("in").buffer == v ).all()) self.assertTrue((ModB.get_out_port("out").buffer == zero).all()) self.assertTrue((ModC.get_in_port("in").buffer == zero).all()) self.assertTrue((SupA.get_out_port("out").buffer == v ).all()) self.assertTrue((SupB.get_in_port("in").buffer == v ).all()) self.assertTrue((SupB.get_out_port("out").buffer == zero).all()) self.assertTrue((SupC.get_in_port("in").buffer == zero).all()) self.assertEquals(time, 12.0) time = ca.step() self.assertTrue((CompA.get_out_port("out").buffer == v ).all()) self.assertTrue((CompB.get_in_port("in").buffer == v ).all()) self.assertTrue((CompB.get_out_port("out").buffer == v ).all()) self.assertTrue((CompC.get_in_port("in").buffer == zero).all()) self.assertTrue((ModA.get_out_port("out").buffer == v ).all()) self.assertTrue((ModB.get_in_port("in").buffer == v ).all()) self.assertTrue((ModB.get_out_port("out").buffer == v ).all()) self.assertTrue((ModC.get_in_port("in").buffer == zero).all()) self.assertTrue((SupA.get_out_port("out").buffer == v ).all()) self.assertTrue((SupB.get_in_port("in").buffer == v ).all()) self.assertTrue((SupB.get_out_port("out").buffer == v ).all()) self.assertTrue((SupC.get_in_port("in").buffer == zero).all()) self.assertEquals(time, 15.0) time = ca.step() self.assertTrue((CompA.get_out_port("out").buffer == v).all()) self.assertTrue((CompB.get_in_port("in").buffer == v).all()) self.assertTrue((CompB.get_out_port("out").buffer == v).all()) self.assertTrue((CompC.get_in_port("in").buffer == v).all()) self.assertTrue((ModA.get_out_port("out").buffer == v).all()) self.assertTrue((ModB.get_in_port("in").buffer == v).all()) self.assertTrue((ModB.get_out_port("out").buffer == v).all()) self.assertTrue((ModC.get_in_port("in").buffer == v).all()) self.assertTrue((SupA.get_out_port("out").buffer == v).all()) self.assertTrue((SupB.get_in_port("in").buffer == v).all()) self.assertTrue((SupB.get_out_port("out").buffer == v).all()) self.assertTrue((SupC.get_in_port("in").buffer == v).all()) self.assertEquals(time, 16.0) time = ca.step() self.assertTrue((CompA.get_out_port("out").buffer == v).all()) self.assertTrue((CompB.get_in_port("in").buffer == v).all()) self.assertTrue((CompB.get_out_port("out").buffer == v).all()) self.assertTrue((CompC.get_in_port("in").buffer == v).all()) self.assertTrue((ModA.get_out_port("out").buffer == v).all()) self.assertTrue((ModB.get_in_port("in").buffer == v).all()) self.assertTrue((ModB.get_out_port("out").buffer == v).all()) self.assertTrue((ModC.get_in_port("in").buffer == v).all()) self.assertTrue((SupA.get_out_port("out").buffer == v).all()) self.assertTrue((SupB.get_in_port("in").buffer == v).all()) self.assertTrue((SupB.get_out_port("out").buffer == v).all()) self.assertTrue((SupC.get_in_port("in").buffer == v).all()) self.assertEquals(time, 17.0)