def load_comp_constants(roach, consts, bram_re, bram_im):
"""
Load complex constants into ROACH bram. Real and imaginary parts
are loaded in separated bram blocks.
:param roach: FpgaClient object to communicate with roach
:param consts: complex constants array.
:param bram_re: bram block name for real part.
:param bram_im: bram block name for imaginary part.
"""
# separate real and imaginary
consts_re = np.real(consts)
consts_im = np.imag(consts)
# convert data into fixed point representation
consts_re_fixed = cd.float2fixed(consts_re,
consts_nbits,
consts_binpt,
warn=True)
consts_im_fixed = cd.float2fixed(consts_im,
consts_nbits,
consts_binpt,
warn=True)
# load data
cd.write_interleaved_data(roach, bram_re, consts_re_fixed)
cd.write_interleaved_data(roach, bram_im, consts_im_fixed)
def msdft(data, N, k):
"""calculate the msdft using the structure in duda
data = smaples to calculate the dft, the len
should be larger than N
N = dft lenght
k = twiddle factor
"""
if (len(data) < N):
raise Exception('len(data) should be larger than N!')
twidd = np.exp(-1j * 2 * np.pi * k / N)
twidd_re = calan.float2fixed(twidd.real, nbits=16, binpt=14)
twidd_im = calan.float2fixed(twidd.imag, nbits=16, binpt=14)
twidd = twidd_re / 2.**14 + 1j * twidd_im / 2.**14
prev_data = np.zeros(N, dtype=complex)
actual_twidd = 1
resonator = 0
mult_1 = 0
out = np.zeros(len(data), dtype=complex)
twidd_values = np.zeros(len(data), dtype=complex)
for i in range(len(data)):
comb = data[i] - prev_data[i % N]
prev_data[i % N] = data[i]
mult_1 = comb * actual_twidd
twidd_values[i] = actual_twidd
phase_mult = np.conjugate(actual_twidd)
actual_twidd = actual_twidd * twidd #W_N**k(n+1)
resonator = resonator + mult_1
out[i] = resonator #*np.conjugate(twidd)
return [out, twidd_values]
def write_twidd(fpga, k, bram_name='twidd'):
N = 2**14
t = np.arange(N)
twidd = np.exp(-1j * 2 * np.pi * k / N * t)
twidd_re = twidd.real
twidd_im = twidd.imag
re_data = calan.float2fixed(twidd_re, nbits=16, binpt=14)
im_data = calan.float2fixed(twidd_im, nbits=16, binpt=14)
twidd_data = np.zeros(2 * len(re_data), dtype='int')
twidd_data[1::2] = re_data
twidd_data[::2] = im_data
twid_data = twidd_data.tolist()
raw_data = struct.pack('>32768h', *twidd_data)
fpga.write(bram_name, raw_data)
return 1
def write_phasor_reg(roach, phasor, addrs, phasor_regs, addr_regs, we_reg,
nbits, binpt):
"""
Writes a phasor (complex) constant into a register from a register bank
in the FPGA. The method to write the phasor is:
1. Write the complex value into software registers, one for the real
and other for the imaginary part.
2. Write the appropate value(s) into the address register(s).
This/these value(s) select the register in the register bank.
In some cases it also select the appropate bank if you have more
than one register bank.
3. Create a positive edge (0->1) in the we (write enable register).
This register is reseted to 0 before anything else in order to
avoid tampering with the rest of the bank.
:param roach: FpgaClient object for communication.
:param phasor: complex constant to write in the register bank.
:param addrs: list of addresses to set in the address registers to
properly select the register in the register bank. The number of
addresses must coincide with the number of address registers.
:param phasor_regs: list of two registers for the real and imaginary part
of the phasor constant. E.g.: ['real_reg', 'imag_reg'].
:param addr_regs: list of registers for the addresses in the bank.
:param we_reg: write enable register for the bank.
:param nbits: number of bits of the fixed point representation in the model.
:param binpt: binary point for the fixed point representation in the model.
"""
# 1. write phasor registers
phasor_re = cd.float2fixed(np.real([phasor]), nbits, binpt)
phasor_im = cd.float2fixed(np.imag([phasor]), nbits, binpt)
roach.write_int(phasor_regs[0], phasor_re)
roach.write_int(phasor_regs[1], phasor_im)
# 2. write address registers
for addr_reg, addr in zip(addr_regs, addrs):
roach.write_int(addr_reg, addr)
# 3. posedge in we register
roach.write_int(we_reg, 1)
roach.write_int(we_reg, 0)