def test_pond_config(run_tb):
# 1x1 interconnect with only PE tile
interconnect = create_cgra(1, 1, IOSide.None_, standalone=True,
mem_ratio=(0, 1),
add_pond=True)
# get pond core
pe_tile = interconnect.tile_circuits[0, 0]
pond_core = pe_tile.additional_cores[0]
pond_feat = pe_tile.features().index(pond_core)
sram_feat = pond_feat + pond_core.num_sram_features
circuit = interconnect.circuit()
tester = BasicTester(circuit, circuit.clk, circuit.reset)
tester.zero_inputs()
tester.reset()
config_data = []
# tile enable
reg_addr, value = pond_core.get_config_data("tile_en", 1)
config_data.append((interconnect.get_config_addr(reg_addr, pond_feat, 0, 0), value))
for i in range(32):
addr = interconnect.get_config_addr(i, sram_feat, 0, 0)
config_data.append((addr, i + 1))
for addr, data in config_data:
tester.configure(addr, data)
# read back
for addr, data in config_data:
tester.config_read(addr)
tester.expect(circuit.read_config_data, data)
run_tb(tester)
def test_config_register():
sides = IOSide.North
ic = create_cgra(2, 2, sides, global_signal_wiring=GlobalSignalWiring.Meso)
with tempfile.TemporaryDirectory() as tempdir:
filename = os.path.join(tempdir, "config.json")
result = get_interconnect_regs(ic)
with open(filename, "w+") as f:
json.dump(result, f)
def basic_tb(config_path,
stream_path,
run_tb,
in_file_name="input",
out_file_name="output",
cwd=None,
trace=False):
chip_size = 2
interconnect = create_cgra(chip_size, chip_size, io_sides(),
num_tracks=3,
add_pd=True,
mem_ratio=(1, 2))
netlist = {
"e0": [("I0", "io2f_16"), ("m0", "data_in_0")],
"e1": [("m0", "data_out_0"), ("I1", "f2io_16")]
}
bus = {"e0": 16, "e1": 16}
placement, routing, _ = pnr(interconnect, (netlist, bus))
config_data = interconnect.get_route_bitstream(routing)
# Regular Bootstrap
MCore = make_memory_core()
# Get configuration
configs_mem = MCore.get_static_bitstream(config_path=config_path,
in_file_name=in_file_name,
out_file_name=out_file_name)
config_final = []
for (f1, f2) in configs_mem:
config_final.append((f1, f2, 0))
mem_x, mem_y = placement["m0"]
memtile = interconnect.tile_circuits[(mem_x, mem_y)]
mcore = memtile.core
config_mem_tile(interconnect, config_data, config_final, mem_x, mem_y, mcore)
circuit = interconnect.circuit()
tester = BasicTester(circuit, circuit.clk, circuit.reset)
tester.reset()
tester.zero_inputs()
tester.poke(circuit.interface["stall"], 1)
for addr, index in config_data:
tester.configure(addr, index)
tester.config_read(addr)
tester.eval()
tester.done_config()
tester.poke(circuit.interface["stall"], 0)
tester.eval()
in_data, out_data, valids = generate_data_lists(csv_file_name=stream_path,
data_in_width=MCore.num_data_inputs(),
data_out_width=MCore.num_data_outputs())
data_in_x, data_in_y = placement["I0"]
data_in = f"glb2io_16_X{data_in_x:02X}_Y{data_in_y:02X}"
data_out_x, data_out_y = placement["I1"]
data_out = f"io2glb_16_X{data_out_x:02X}_Y{data_out_y:02X}"
for i in range(len(out_data)):
tester.poke(circuit.interface[data_in], in_data[0][i])
tester.eval()
tester.expect(circuit.interface[data_out], out_data[0][i])
# toggle the clock
tester.step(2)
run_tb(tester, cwd=cwd, trace=trace, disable_ndarray=True)
def test_pond_pe(verilator=True):
chip_size = 2
interconnect = create_cgra(chip_size,
chip_size,
io_sides(),
num_tracks=3,
add_pd=True,
add_pond=True,
mem_ratio=(1, 2))
netlist = {
"e0": [("I0", "io2f_16"), ("p0", "data_in_pond")],
"e1": [("I1", "io2f_16"), ("p0", "data1")],
"e2": [("p0", "alu_res"), ("I2", "f2io_16")],
"e3": [("p0", "data_out_pond"), ("p0", "data0")]
}
bus = {"e0": 16, "e1": 16, "e2": 16, "e3": 16}
placement, routing = pnr(interconnect, (netlist, bus))
config_data = interconnect.get_route_bitstream(routing)
pe_x, pe_y = placement["p0"]
petile = interconnect.tile_circuits[(pe_x, pe_y)]
pondcore = petile.additional_cores[0]
add_bs = petile.core.get_config_bitstream(asm.umult0())
for addr, data in add_bs:
config_data.append((interconnect.get_config_addr(addr, 0, pe_x,
pe_y), data))
# Ranges, Strides, Dimensionality, Starting Addr, Starting Addr - Schedule
ctrl_rd = [[16, 1], [1, 1], 2, 0, 16]
ctrl_wr = [[16, 1], [1, 1], 2, 0, 0]
generate_pond_api(interconnect, pondcore, ctrl_rd, ctrl_wr, pe_x, pe_y,
config_data)
config_data = compress_config_data(config_data)
circuit = interconnect.circuit()
tester = BasicTester(circuit, circuit.clk, circuit.reset)
tester.poke(circuit.interface["stall"], 1)
for addr, index in config_data:
tester.configure(addr, index)
tester.config_read(addr)
tester.eval()
tester.expect(circuit.read_config_data, index)
tester.done_config()
tester.poke(circuit.interface["stall"], 0)
tester.eval()
src_x0, src_y0 = placement["I0"]
src_x1, src_y1 = placement["I1"]
src_name0 = f"glb2io_16_X{src_x0:02X}_Y{src_y0:02X}"
src_name1 = f"glb2io_16_X{src_x1:02X}_Y{src_y1:02X}"
dst_x, dst_y = placement["I2"]
dst_name = f"io2glb_16_X{dst_x:02X}_Y{dst_y:02X}"
random.seed(0)
for i in range(32):
if i < 16:
tester.poke(circuit.interface[src_name0], i)
tester.eval()
if i >= 16:
num = random.randrange(0, 256)
tester.poke(circuit.interface[src_name1], num)
tester.eval()
tester.expect(circuit.interface[dst_name], (i - 16) * num)
tester.step(2)
tester.eval()
with tempfile.TemporaryDirectory() as tempdir:
for genesis_verilog in glob.glob("genesis_verif/*.*"):
shutil.copy(genesis_verilog, tempdir)
for filename in dw_files():
shutil.copy(filename, tempdir)
shutil.copy(os.path.join("tests", "test_memory_core", "sram_stub.v"),
os.path.join(tempdir, "sram_512w_16b.v"))
for aoi_mux in glob.glob("tests/*.sv"):
shutil.copy(aoi_mux, tempdir)
target = "verilator"
runtime_kwargs = {
"magma_output": "coreir-verilog",
"magma_opts": {
"coreir_libs": {"float_DW"}
},
"directory": tempdir,
"flags": ["-Wno-fatal", "--trace"]
}
if verilator is False:
target = "system-verilog"
runtime_kwargs["simulator"] = "vcs"
tester.compile_and_run(target=target, tmp_dir=False, **runtime_kwargs)
def test_pond_pe_acc(run_tb):
chip_size = 2
interconnect = create_cgra(chip_size, chip_size, io_sides(),
num_tracks=3,
add_pd=True,
add_pond=True,
mem_ratio=(1, 2))
netlist = {
"e0": [("I0", "io2f_16"), ("p0", "data0")],
"e1": [("p0", "data_out_pond"), ("p0", "data1")],
"e2": [("p0", "alu_res"), ("p0", "data_in_pond")],
"e3": [("p0", "data_out_pond"), ("I1", "f2io_16")]
}
bus = {"e0": 16, "e1": 16, "e2": 16, "e3": 16}
placement, routing = pnr(interconnect, (netlist, bus))
config_data = interconnect.get_route_bitstream(routing)
pe_x, pe_y = placement["p0"]
petile = interconnect.tile_circuits[(pe_x, pe_y)]
pondcore = petile.additional_cores[0]
add_bs = petile.core.get_config_bitstream(asm.add())
for addr, data in add_bs:
config_data.append((interconnect.get_config_addr(addr, 0, pe_x, pe_y), data))
# Ranges, Strides, Dimensionality, Starting Addr, Starting Addr - Schedule
ctrl_rd = [[16, 1], [0, 0], 2, 8, 0, [1, 0]]
ctrl_wr = [[16, 1], [0, 0], 2, 8, 0, [1, 0]]
generate_pond_api(interconnect, pondcore, ctrl_rd, ctrl_wr, pe_x, pe_y, config_data)
config_data = compress_config_data(config_data)
circuit = interconnect.circuit()
tester = BasicTester(circuit, circuit.clk, circuit.reset)
tester.zero_inputs()
tester.reset()
tester.poke(circuit.interface["stall"], 1)
for addr, index in config_data:
tester.configure(addr, index)
tester.config_read(addr)
tester.eval()
tester.expect(circuit.read_config_data, index)
tester.done_config()
tester.poke(circuit.interface["stall"], 0)
tester.eval()
src_x0, src_y0 = placement["I0"]
src_name0 = f"glb2io_16_X{src_x0:02X}_Y{src_y0:02X}"
dst_x, dst_y = placement["I1"]
dst_name = f"io2glb_16_X{dst_x:02X}_Y{dst_y:02X}"
random.seed(0)
total = 0
for i in range(16):
tester.poke(circuit.interface[src_name0], i + 1)
total = total + i
tester.eval()
tester.expect(circuit.interface[dst_name], total)
tester.step(2)
tester.eval()
run_tb(tester)
