def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = False
import sram
from characterizer import lib
debug.info(
1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram.sram(word_size=2,
num_words=OPTS.num_words,
num_banks=OPTS.num_banks,
name="sram_2_16_1_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = True
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
filename = s.name + "_analytical.lib"
libname = OPTS.openram_temp + filename
lib.lib(libname=libname, sram=s, spfile=tempspice, use_model=True)
# let's diff the result with a golden model
golden = "{0}/golden/{1}".format(
os.path.dirname(os.path.realpath(__file__)), filename)
self.isapproxdiff(libname, golden, 0.15)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = False
import sram
from characterizer import lib
debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram.sram(word_size=2,
num_words=16,
num_banks=1,
name="sram_2_16_1_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = True
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
lib.lib(out_dir=OPTS.openram_temp, sram=s, sp_file=tempspice, use_model=True)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
newname = filename.replace(".lib","_analytical.lib")
libname = "{0}/{1}".format(OPTS.openram_temp,filename)
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),newname)
self.isapproxdiff(libname,golden,0.15)
globals.end_openram()
def runTest(self):
globals.init_AMC("config_20_{0}".format(OPTS.tech_name))
# This is a hack to reload the characterizer __init__ with the spice version
import characterizer
reload(characterizer)
from characterizer import lib
import sram
import tech
#**** Setup synopsys' HSIM and VCS ***#
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=4,
words_per_row=1,
num_rows=32,
num_subanks=1,
branch_factors=(1, 1),
bank_orientations=("H", "H"),
name="sram")
tempspice = OPTS.AMC_temp + "sram.sp"
s.sp_write(tempspice)
lib.lib(OPTS.AMC_temp, s)
globals.end_AMC()
def save_output(self):
""" Save all the output files while reporting time to do it as well. """
# Save the spice file
start_time = datetime.datetime.now()
spname = OPTS.output_path + self.name + ".sp"
print("SP: Writing to {0}".format(spname))
self.sp_write(spname)
print_time("Spice writing", datetime.datetime.now(), start_time)
# Save the extracted spice file
if OPTS.use_pex:
start_time = datetime.datetime.now()
# Output the extracted design if requested
sp_file = OPTS.output_path + "temp_pex.sp"
verify.run_pex(self.name, gdsname, spname, output=sp_file)
print_time("Extraction", datetime.datetime.now(), start_time)
else:
# Use generated spice file for characterization
sp_file = spname
# Characterize the design
start_time = datetime.datetime.now()
from characterizer import lib
print("LIB: Characterizing... ")
if OPTS.analytical_delay:
print("Using analytical delay models (no characterization)")
else:
if OPTS.spice_name != "":
print("Performing simulation-based characterization with {}".
format(OPTS.spice_name))
if OPTS.trim_netlist:
print("Trimming netlist to speed up characterization.")
lib.lib(out_dir=OPTS.output_path, sram=self, sp_file=sp_file)
print_time("Characterization", datetime.datetime.now(), start_time)
# Write the layout
start_time = datetime.datetime.now()
gdsname = OPTS.output_path + self.name + ".gds"
print("GDS: Writing to {0}".format(gdsname))
self.gds_write(gdsname)
print_time("GDS", datetime.datetime.now(), start_time)
# Create a LEF physical model
start_time = datetime.datetime.now()
lefname = OPTS.output_path + self.name + ".lef"
print("LEF: Writing to {0}".format(lefname))
self.lef_write(lefname)
print_time("LEF", datetime.datetime.now(), start_time)
# Write a verilog model
start_time = datetime.datetime.now()
vname = OPTS.output_path + self.name + ".v"
print("Verilog: Writing to {0}".format(vname))
self.verilog_write(vname)
print_time("Verilog", datetime.datetime.now(), start_time)
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = False
OPTS.spice_name = "" # Unset to use any simulator
OPTS.analytical_delay = False
OPTS.trim_netlist = False
# This is a hack to reload the characterizer __init__ with the spice version
import characterizer
reload(characterizer)
from characterizer import lib
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),
-1)
import sram
debug.info(
1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram.sram(word_size=2,
num_words=16,
num_banks=1,
name="sram_2_16_1_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = True
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
lib.lib(out_dir=OPTS.openram_temp,
sram=s,
sp_file=tempspice,
use_model=False)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
libname = "{0}/{1}".format(OPTS.openram_temp, filename)
golden = "{0}/golden/{1}".format(
os.path.dirname(os.path.realpath(__file__)), filename)
self.isapproxdiff(libname, golden, 0.15)
OPTS.analytical_delay = True
OPTS.trim_netlist = True
reload(characterizer)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = False
OPTS.spice_name = "" # Unset to use any simulator
OPTS.analytical_delay = False
OPTS.trim_netlist = False
# This is a hack to reload the characterizer __init__ with the spice version
import characterizer
reload(characterizer)
from characterizer import lib
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),
-1)
import sram
debug.info(
1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram.sram(word_size=2,
num_words=OPTS.num_words,
num_banks=OPTS.num_banks,
name="sram_2_16_1_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = True
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
filename = s.name + ".lib"
libname = OPTS.openram_temp + filename
lib.lib(libname=libname, sram=s, spfile=tempspice, use_model=False)
# let's diff the result with a golden model
golden = "{0}/golden/{1}".format(
os.path.dirname(os.path.realpath(__file__)), filename)
self.isapproxdiff(libname, golden, 0.15)
OPTS.analytical_delay = True
OPTS.trim_netlist = True
reload(characterizer)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.analytical_delay = False
OPTS.trim_netlist = False
import characterizer
reload(characterizer)
from characterizer import lib
import sram
debug.info(
1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram.sram(word_size=2,
num_words=OPTS.config.num_words,
num_banks=OPTS.config.num_banks,
name="sram_2_16_1_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = True
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
filename = s.name + ".lib"
libname = OPTS.openram_temp + filename
lib.lib(libname=libname, sram=s, spfile=tempspice, use_model=False)
# let's diff the result with a golden model
golden = "{0}/golden/{1}".format(
os.path.dirname(os.path.realpath(__file__)), filename)
self.assertEqual(isapproxdiff(libname, golden, 0.25), True)
OPTS.analytical_delay = True
OPTS.trim_netlist = True
reload(characterizer)
globals.end_openram()
sram_file = OPTS.output_path + "temp_pex.sp"
verify.run_pex(s.name, gdsname, spname, output=sram_file)
# Characterize the design
from characterizer import lib
libname = OPTS.output_path + s.name + ".lib"
print("LIB: Writing to {0}".format(libname))
if OPTS.analytical_delay:
print("Using analytical delay models (no characterization)")
else:
if OPTS.spice_name != "":
print("Performing simulation-based characterization with {}".format(
OPTS.spice_name))
if OPTS.trim_netlist:
print("Trimming netlist to speed up characterization.")
lib.lib(libname, s, sram_file)
last_time = print_time("Characterization", datetime.datetime.now(), last_time)
# Write the layout
gdsname = OPTS.output_path + s.name + ".gds"
print("GDS: Writing to {0}".format(gdsname))
s.gds_write(gdsname)
last_time = print_time("GDS", datetime.datetime.now(), last_time)
# Create a LEF physical model
lefname = OPTS.output_path + s.name + ".lef"
print("LEF: Writing to {0}".format(lefname))
s.lef_write(lefname)
last_time = print_time("LEF", datetime.datetime.now(), last_time)
# Write a verilog model
