def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.netlist_only = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=1,
num_words=16,
num_banks=1)
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.s.addr_size
probe_data = s.s.word_size - 1
debug.info(1, "Probe address {0} probe data bit {1}".format(probe_address, probe_data))
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["dff_in_cap"]*4]
slews = [tech.spice["rise_time"]*2]
# Run a spice characterization
spice_data, port_data = d.analyze(probe_address, probe_data, slews, loads)
spice_data.update(port_data[0])
# Run analytical characterization
model_data, port_data = d.analytical_delay(slews, loads)
model_data.update(port_data[0])
# Only compare the delays
spice_delays = {key:value for key, value in spice_data.items() if 'delay' in key}
model_delays = {key:value for key, value in model_data.items() if 'delay' in key}
debug.info(1,"Spice Delays={}".format(spice_delays))
debug.info(1,"Model Delays={}".format(model_delays))
if OPTS.tech_name == "freepdk45":
error_tolerance = 0.25
elif OPTS.tech_name == "scn4m_subm":
error_tolerance = 0.25
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(spice_delays.keys())==len(model_delays.keys()))
self.assertTrue(self.check_golden_data(spice_delays,model_delays,error_tolerance))
globals.end_openram()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram_config import sram_config
c = sram_config(word_size=4, num_words=256, num_banks=1)
c.words_per_row = 4
c.recompute_sizes()
debug.info(
1,
"Functional test for sram with {} bit words, {} words, {} words per row, {} banks"
.format(c.word_size, c.num_words, c.words_per_row, c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
d = delay(s.s, tempspice, corner)
feasible_period = self.find_feasible_test_period(
d, s.s, f.load, f.slew)
f.num_cycles = 10
(fail, error) = f.run()
self.assertTrue(fail, error)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.spice_name = "ngspice"
OPTS.analytical_delay = False
OPTS.trim_netlist = False
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import delay
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),
-1)
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=1, num_words=16, num_banks=1)
c.words_per_row = 1
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.s.addr_size
probe_data = s.s.word_size - 1
debug.info(
1, "Probe address {0} probe data bit {1}".format(
probe_address, probe_data))
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["msflop_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data = d.analyze(probe_address, probe_data, slews, loads)
if OPTS.tech_name == "freepdk45":
golden_data = {
'delay_hl0': [2.584251],
'delay_lh0': [0.22870469999999998],
'leakage_power': 0.0009567935,
'min_period': 4.844,
'read0_power0': [0.0547588],
'read1_power0': [0.051159970000000006],
'slew_hl0': [0.08164099999999999],
'slew_lh0': [0.025474979999999998],
'write0_power0': [0.06513271999999999],
'write1_power0': [0.058057000000000004]
}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {
'delay_hl0': [3.644147],
'delay_lh0': [1.629815],
'leakage_power': 0.0009299118999999999,
'min_period': 4.688,
'read0_power0': [16.28732],
'read1_power0': [15.75155],
'slew_hl0': [0.6722473],
'slew_lh0': [0.3386347],
'write0_power0': [18.545450000000002],
'write1_power0': [16.81084]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
self.assertTrue(self.check_golden_data(data, golden_data, 0.25))
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.spice_name = "ngspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=1, num_words=16, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.s.addr_size
probe_data = s.s.word_size - 1
debug.info(
1, "Probe address {0} probe data bit {1}".format(
probe_address, probe_data))
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["msflop_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data, port_data = d.analyze(probe_address, probe_data, slews, loads)
#Combine info about port into all data
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {
'delay_hl': [0.221699],
'delay_lh': [0.221699],
'leakage_power': 0.001467648,
'min_period': 0.605,
'read0_power': [0.3879335],
'read1_power': [0.3662724],
'slew_hl': [0.08562444999999999],
'slew_lh': [0.08562444999999999],
'write0_power': [0.3362456],
'write1_power': [0.3372035]
}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {
'delay_hl': [1.7951730000000001],
'delay_lh': [1.7951730000000001],
'leakage_power': 0.001669513,
'min_period': 3.594,
'read0_power': [17.03022],
'read1_power': [16.55897],
'slew_hl': [0.7079951],
'slew_lh': [0.7079951],
'write0_power': [15.16726],
'write1_power': [16.13527]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
self.assertTrue(self.check_golden_data(data, golden_data, 0.25))
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.spice_name = "hspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import delay
from sram_config import sram_config
c = sram_config(word_size=1, num_words=16, num_banks=1)
c.words_per_row = 1
# c = sram_config(word_size=32,
# num_words=256,
# num_banks=1)
# c.words_per_row=2
# OPTS.use_tech_delay_chain_size = True
c.recompute_sizes()
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = factory.create(module_type="sram", sram_config=c)
#import sys
#sys.exit(1)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.s.addr_size
probe_data = s.s.word_size - 1
debug.info(
1, "Probe address {0} probe data bit {1}".format(
probe_address, probe_data))
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["dff_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data, port_data = d.analyze(probe_address, probe_data, slews, loads)
#Combine info about port into all data
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {
'min_period': 0.898,
'write1_power': [0.2659137999999999],
'disabled_write0_power': [0.1782495],
'disabled_read0_power': [0.14490679999999997],
'write0_power': [0.3330119],
'disabled_write1_power': [0.1865223],
'leakage_power': 0.0014532,
'disabled_read1_power': [0.1627516],
'slew_lh': [0.25367799999999996],
'slew_hl': [0.25367799999999996],
'delay_lh': [0.23820930000000004],
'delay_hl': [0.23820930000000004],
'read1_power': [0.3005756],
'read0_power': [0.3005888]
}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {
'leakage_power': 0.0006356576000000001,
'write1_power': [11.292700000000002],
'read0_power': [12.98],
'disabled_write1_power': [8.3707],
'write0_power': [14.4447],
'delay_hl': [1.7445000000000002],
'disabled_read0_power': [6.4325],
'slew_hl': [1.7437],
'disabled_write0_power': [8.1307],
'slew_lh': [1.7437],
'read1_power': [12.9869],
'disabled_read1_power': [7.706],
'min_period': 6.25,
'delay_lh': [1.7445000000000002]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
self.assertTrue(self.check_golden_data(data, golden_data, 0.25))
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.spice_name = "ngspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=1, num_words=16, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.s.addr_size
probe_data = s.s.word_size - 1
debug.info(
1, "Probe address {0} probe data bit {1}".format(
probe_address, probe_data))
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["msflop_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data, port_data = d.analyze(probe_address, probe_data, slews, loads)
#Combine info about port into all data
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {
'delay_bl': [0.2003652],
'delay_br': [0.198698],
'delay_hl': [0.2108836],
'delay_lh': [0.2108836],
'leakage_power': 0.001564799,
'min_period': 0.508,
'read0_power': [0.43916689999999997],
'read1_power': [0.4198608],
'slew_hl': [0.0455126],
'slew_lh': [0.0455126],
'volt_bl': [0.6472883],
'volt_br': [1.114024],
'write0_power': [0.40681890000000004],
'write1_power': [0.4198608]
}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {
'delay_bl': [1.3937359999999999],
'delay_br': [1.2596429999999998],
'delay_hl': [1.5747600000000002],
'delay_lh': [1.5747600000000002],
'leakage_power': 0.00195795,
'min_period': 3.281,
'read0_power': [14.92874],
'read1_power': [14.369810000000001],
'slew_hl': [0.49631959999999997],
'slew_lh': [0.49631959999999997],
'volt_bl': [4.132618],
'volt_br': [5.573099],
'write0_power': [13.79953],
'write1_power': [14.369810000000001]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
self.assertTrue(self.check_golden_data(data, golden_data, 0.25))
globals.end_openram()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.spice_name = "hspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import delay
from sram_config import sram_config
c = sram_config(word_size=1, num_words=16, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.s.addr_size
probe_data = s.s.word_size - 1
debug.info(
1, "Probe address {0} probe data bit {1}".format(
probe_address, probe_data))
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["msflop_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data, port_data = d.analyze(probe_address, probe_data, slews, loads)
#Combine info about port into all data
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {
'delay_hl': [0.2121267],
'delay_lh': [0.2121267],
'leakage_power': 0.0023761999999999998,
'min_period': 0.43,
'read0_power': [0.5139368],
'read1_power': [0.48940979999999995],
'slew_hl': [0.0516745],
'slew_lh': [0.0516745],
'write0_power': [0.46267169999999996],
'write1_power': [0.4670826]
}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {
'delay_hl': [1.288],
'delay_lh': [1.288],
'leakage_power': 0.0273896,
'min_period': 2.578,
'read0_power': [16.9996],
'read1_power': [16.2616],
'slew_hl': [0.47891700000000004],
'slew_lh': [0.47891700000000004],
'write0_power': [16.0656],
'write1_power': [16.2616]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
self.assertTrue(self.check_golden_data(data, golden_data, 0.25))
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.spice_name = "hspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import delay, bitline_delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=1, num_words=16, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.s.addr_size
probe_data = s.s.word_size - 1
debug.info(
1, "Probe address {0} probe data bit {1}".format(
probe_address, probe_data))
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
bl = bitline_delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["msflop_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data, port_data = d.analyze(probe_address, probe_data, slews, loads)
#bitline_swing = bl.analyze(probe_address, probe_data, slews, loads)
#Combine info about port into all data
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {
'delay_hl': [0.2152017],
'delay_lh': [0.2152017],
'leakage_power': 0.0022907,
'min_period': 0.488,
'read0_power': [0.47437749999999995],
'read1_power': [0.45026109999999997],
'slew_hl': [0.0846786],
'slew_lh': [0.0846786],
'write0_power': [0.40809259999999997],
'write1_power': [0.4078904]
}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {
'delay_hl': [1.4333000000000002],
'delay_lh': [1.4333000000000002],
'leakage_power': 0.0271847,
'min_period': 2.891,
'read0_power': [15.714200000000002],
'read1_power': [14.9848],
'slew_hl': [0.6819276999999999],
'slew_lh': [0.6819276999999999],
'write0_power': [13.9658],
'write1_power': [14.8422]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
self.assertTrue(self.check_golden_data(data, golden_data, 0.25))
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.spice_name = "ngspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import delay
from sram_config import sram_config
c = sram_config(word_size=1, num_words=16, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.s.addr_size
probe_data = s.s.word_size - 1
debug.info(
1, "Probe address {0} probe data bit {1}".format(
probe_address, probe_data))
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["dff_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data, port_data = d.analyze(probe_address, probe_data, slews, loads)
#Combine info about port into all data
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {
'delay_hl': [0.2264205],
'delay_lh': [0.2264205],
'leakage_power': 0.0021017429999999997,
'min_period': 0.859,
'read0_power': [0.3339161],
'read1_power': [0.31329440000000003],
'slew_hl': [0.2590786],
'slew_lh': [0.2590786],
'write0_power': [0.36360849999999995],
'write1_power': [0.3486931]
}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {
'delay_hl': [1.85985],
'delay_lh': [1.85985],
'leakage_power': 0.008613619,
'min_period': 6.875,
'read0_power': [12.656310000000001],
'read1_power': [12.11682],
'slew_hl': [1.868942],
'slew_lh': [1.868942],
'write0_power': [13.978110000000001],
'write1_power': [11.437930000000001]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
self.assertTrue(self.check_golden_data(data, golden_data, 0.25))
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.spice_name = "ngspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import delay
from sram_config import sram_config
OPTS.local_array_size = 2
c = sram_config(word_size=4, num_words=16, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
# c = sram_config(word_size=8,
# num_words=32,
# num_banks=1)
# c.words_per_row=2
# c.recompute_sizes()
debug.info(1, "Testing timing for global hierarchical array")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.s.addr_size
probe_data = s.s.word_size - 1
debug.info(
1, "Probe address {0} probe data bit {1}".format(
probe_address, probe_data))
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["dff_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data, port_data = d.analyze(probe_address, probe_data, slews, loads)
#Combine info about port into all data
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {
'delay_hl': [0.26308339999999997],
'delay_lh': [0.26308339999999997],
'disabled_read0_power': [0.1829355],
'disabled_read1_power': [0.1962055],
'disabled_write0_power': [0.2130763],
'disabled_write1_power': [0.2349011],
'leakage_power': 0.002509793,
'min_period': 0.977,
'read0_power': [0.4028693],
'read1_power': [0.4055884],
'slew_hl': [0.27116019999999996],
'slew_lh': [0.27116019999999996],
'write0_power': [0.44159149999999997],
'write1_power': [0.3856132]
}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {
'delay_hl': [2.0149939999999997],
'delay_lh': [2.0149939999999997],
'disabled_read0_power': [7.751129],
'disabled_read1_power': [9.025803],
'disabled_write0_power': [9.546656],
'disabled_write1_power': [10.2449],
'leakage_power': 0.004770704,
'min_period': 7.188,
'read0_power': [17.68452],
'read1_power': [18.24353],
'slew_hl': [1.942796],
'slew_lh': [1.942796],
'write0_power': [20.02101],
'write1_power': [15.389470000000001]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
self.assertTrue(self.check_golden_data(data, golden_data, 0.25))
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.spice_name = "ngspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import delay
from sram_config import sram_config
c = sram_config(word_size=1,
num_words=16,
num_banks=1,
num_spare_rows=3)
c.words_per_row = 1
c.recompute_sizes()
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "0" + ("1" * (s.s.addr_size - 1))
probe_data = s.s.word_size - 1
debug.info(
1, "Probe address {0} probe data bit {1}".format(
probe_address, probe_data))
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["dff_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data, port_data = d.analyze(probe_address, probe_data, slews, loads)
#Combine info about port into all data
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {
'slew_lh': [0.2592187],
'slew_hl': [0.2592187],
'delay_lh': [0.2465583],
'disabled_write0_power': [0.1924678],
'disabled_read0_power': [0.152483],
'write0_power': [0.3409064],
'disabled_read1_power': [0.1737818],
'read0_power': [0.3096708],
'read1_power': [0.3107916],
'delay_hl': [0.2465583],
'write1_power': [0.26915849999999997],
'leakage_power': 0.002044307,
'min_period': 0.898,
'disabled_write1_power': [0.201411]
}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {
'read1_power': [12.11658],
'write1_power': [10.52653],
'read0_power': [11.956710000000001],
'disabled_write0_power': [7.673665],
'disabled_write1_power': [7.981922000000001],
'slew_lh': [1.868836],
'slew_hl': [1.868836],
'delay_hl': [1.8598510000000001],
'delay_lh': [1.8598510000000001],
'leakage_power': 0.005457728,
'disabled_read0_power': [5.904712],
'min_period': 6.875,
'disabled_read1_power': [7.132159],
'write0_power': [13.406400000000001]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
self.assertTrue(self.check_golden_data(data, golden_data, 0.25))
globals.end_openram()
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.spice_name = "hspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import delay
from sram_config import sram_config
c = sram_config(word_size=1, num_words=16, num_banks=1)
c.words_per_row = 1
# c = sram_config(word_size=32,
# num_words=256,
# num_banks=1)
# c.words_per_row=2
# OPTS.use_tech_delay_chain_size = True
c.recompute_sizes()
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = factory.create(module_type="sram", sram_config=c)
#import sys
#sys.exit(1)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.s.addr_size
probe_data = s.s.word_size - 1
debug.info(
1, "Probe address {0} probe data bit {1}".format(
probe_address, probe_data))
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["dff_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data, port_data = d.analyze(probe_address, probe_data, slews, loads)
#Combine info about port into all data
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {
'delay_hl': [0.2383338],
'delay_lh': [0.2383338],
'leakage_power': 0.0014532999999999998,
'min_period': 0.898,
'read0_power': [0.30059800000000003],
'read1_power': [0.30061810000000005],
'slew_hl': [0.25358420000000004],
'slew_lh': [0.25358420000000004],
'write0_power': [0.34616749999999996],
'write1_power': [0.2792924]
}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {
'delay_hl': [1.7448],
'delay_lh': [1.7448],
'leakage_power': 0.0006356744000000001,
'min_period': 6.25,
'read0_power': [12.9846],
'read1_power': [12.9722],
'slew_hl': [1.7433],
'slew_lh': [1.7433],
'write0_power': [14.8772],
'write1_power': [11.7217]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
self.assertTrue(self.check_golden_data(data, golden_data, 0.25))
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.spice_name = "hspice"
OPTS.analytical_delay = False
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import delay
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),
-1)
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=1, num_words=16, num_banks=1)
c.words_per_row = 1
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.s.addr_size
probe_data = s.s.word_size - 1
debug.info(
1, "Probe address {0} probe data bit {1}".format(
probe_address, probe_data))
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0],
OPTS.temperatures[0])
d = delay(s.s, tempspice, corner)
import tech
loads = [tech.spice["msflop_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data = d.analyze(probe_address, probe_data, slews, loads)
#Assumes single rw port (6t sram)
if OPTS.tech_name == "freepdk45":
golden_data = {
'delay_hl0': [2.5829000000000004],
'delay_lh0': [0.2255964],
'leakage_power': 0.0019498999999999996,
'min_period': 4.844,
'read0_power0': [0.055371399999999994],
'read1_power0': [0.0520225],
'slew_hl0': [0.0794261],
'slew_lh0': [0.0236264],
'write0_power0': [0.06545659999999999],
'write1_power0': [0.057846299999999996]
}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {
'delay_hl0': [3.452],
'delay_lh0': [1.3792000000000002],
'leakage_power': 0.0257065,
'min_period': 4.688,
'read0_power0': [15.0755],
'read1_power0': [14.4526],
'slew_hl0': [0.6137363],
'slew_lh0': [0.3381045],
'write0_power0': [16.9203],
'write1_power0': [15.367]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
self.assertTrue(self.check_golden_data(data, golden_data, 0.25))
globals.end_openram()
