def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from characterizer import lib
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2, num_words=16, num_banks=1)
c.words_per_row = 1
debug.info(
1,
"Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank"
)
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
lib(out_dir=OPTS.openram_temp,
sram=s.s,
sp_file=tempspice,
use_model=True)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
newname = filename.replace(".lib", "_analytical.lib")
libname = "{0}/{1}".format(OPTS.openram_temp, filename)
golden = "{0}/golden/{1}".format(
os.path.dirname(os.path.realpath(__file__)), newname)
self.assertTrue(self.isapproxdiff(libname, golden, 0.15))
globals.end_openram()
def save(self):
""" Save all the output files while reporting time to do it as well. """
# Save the spice file
start_time = datetime.datetime.now()
spname = OPTS.output_path + self.s.name + ".sp"
print("SP: Writing to {0}".format(spname))
self.s.sp_write(spname)
print_time("Spice writing", datetime.datetime.now(), start_time)
# Save the extracted spice file
if OPTS.use_pex:
start_time = datetime.datetime.now()
# Output the extracted design if requested
sp_file = OPTS.output_path + "temp_pex.sp"
verify.run_pex(self.s.name, gdsname, spname, output=sp_file)
print_time("Extraction", datetime.datetime.now(), start_time)
else:
# Use generated spice file for characterization
sp_file = spname
# Characterize the design
start_time = datetime.datetime.now()
from characterizer import lib
print("LIB: Characterizing... ")
if OPTS.analytical_delay:
print("Using analytical delay models (no characterization)")
else:
if OPTS.spice_name != "":
print("Performing simulation-based characterization with {}".
format(OPTS.spice_name))
if OPTS.trim_netlist:
print("Trimming netlist to speed up characterization.")
lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
print_time("Characterization", datetime.datetime.now(), start_time)
if not OPTS.netlist_only:
# Write the layout
start_time = datetime.datetime.now()
gdsname = OPTS.output_path + self.s.name + ".gds"
print("GDS: Writing to {0}".format(gdsname))
self.s.gds_write(gdsname)
print_time("GDS", datetime.datetime.now(), start_time)
# Create a LEF physical model
start_time = datetime.datetime.now()
lefname = OPTS.output_path + self.s.name + ".lef"
print("LEF: Writing to {0}".format(lefname))
self.s.lef_write(lefname)
print_time("LEF", datetime.datetime.now(), start_time)
# Write a verilog model
start_time = datetime.datetime.now()
vname = OPTS.output_path + self.s.name + ".v"
print("Verilog: Writing to {0}".format(vname))
self.s.verilog_write(vname)
print_time("Verilog", datetime.datetime.now(), start_time)
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import lib
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),
-1)
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2, num_words=16, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
debug.info(
1,
"Testing pruned timing for sample 2 bit, 16 words SRAM with 1 bank"
)
# This doesn't have to use the factory since worst case
# it will just replaece the top-level module of the same name
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
lib(out_dir=OPTS.openram_temp,
sram=s.s,
sp_file=tempspice,
use_model=False)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
newname = filename.replace(".lib", "_pruned.lib")
libname = "{0}/{1}".format(OPTS.openram_temp, filename)
golden = "{0}/golden/{1}".format(
os.path.dirname(os.path.realpath(__file__)), newname)
self.assertTrue(self.isapproxdiff(libname, golden, 0.40))
reload(characterizer)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.nominal_corner_only = False
OPTS.netlist_only = True
from characterizer import lib
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2, num_words=16, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
debug.info(
1,
"Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank"
)
# This doesn't have to use the factory since worst case
# it will just replaece the top-level module of the same name
s = sram(c, name="sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
#Set the corners. Lib will create a power set of the lists.
if OPTS.tech_name == "scn4m_subm":
OPTS.process_corners = ["TT", "SS", "FF"]
OPTS.supply_voltages = [5.0]
OPTS.temperatures = [25]
elif OPTS.tech_name == "freepdk45":
OPTS.process_corners = ["TT", "SS", "FF"]
OPTS.supply_voltages = [1.0]
OPTS.temperatures = [25]
lib(out_dir=OPTS.openram_temp,
sram=s.s,
sp_file=tempspice,
use_model=True)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
newname = filename.replace(".lib", "_analytical.lib")
libname = "{0}/{1}".format(OPTS.openram_temp, filename)
golden = "{0}/golden/{1}".format(
os.path.dirname(os.path.realpath(__file__)), newname)
self.assertTrue(self.isapproxdiff(libname, golden, 0.15))
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.trim_netlist = False
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import lib
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),
-1)
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2, num_words=16, num_banks=1)
c.words_per_row = 1
debug.info(
1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
lib(out_dir=OPTS.openram_temp,
sram=s.s,
sp_file=tempspice,
use_model=False)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
libname = "{0}/{1}".format(OPTS.openram_temp, filename)
golden = "{0}/golden/{1}".format(
os.path.dirname(os.path.realpath(__file__)), filename)
self.assertTrue(self.isapproxdiff(libname, golden, 0.40))
reload(characterizer)
globals.end_openram()
def save(self):
""" Save all the output files while reporting time to do it as well. """
# Save the spice file
start_time = datetime.datetime.now()
spname = OPTS.output_path + self.s.name + ".sp"
debug.print_raw("SP: Writing to {0}".format(spname))
self.sp_write(spname)
functional(self.s,
os.path.basename(spname),
cycles=200,
output_path=OPTS.output_path)
print_time("Spice writing", datetime.datetime.now(), start_time)
if not OPTS.netlist_only:
# Write the layout
start_time = datetime.datetime.now()
gdsname = OPTS.output_path + self.s.name + ".gds"
debug.print_raw("GDS: Writing to {0}".format(gdsname))
self.gds_write(gdsname)
if OPTS.check_lvsdrc:
verify.write_drc_script(cell_name=self.s.name,
gds_name=os.path.basename(gdsname),
extract=True,
final_verification=True,
output_path=OPTS.output_path)
print_time("GDS", datetime.datetime.now(), start_time)
# Create a LEF physical model
start_time = datetime.datetime.now()
lefname = OPTS.output_path + self.s.name + ".lef"
debug.print_raw("LEF: Writing to {0}".format(lefname))
self.lef_write(lefname)
print_time("LEF", datetime.datetime.now(), start_time)
# Save the LVS file
start_time = datetime.datetime.now()
lvsname = OPTS.output_path + self.s.name + ".lvs.sp"
debug.print_raw("LVS: Writing to {0}".format(lvsname))
self.lvs_write(lvsname)
if not OPTS.netlist_only and OPTS.check_lvsdrc:
verify.write_lvs_script(cell_name=self.s.name,
gds_name=os.path.basename(gdsname),
sp_name=os.path.basename(lvsname),
final_verification=True,
output_path=OPTS.output_path)
print_time("LVS writing", datetime.datetime.now(), start_time)
# Save the extracted spice file
if OPTS.use_pex:
start_time = datetime.datetime.now()
# Output the extracted design if requested
pexname = OPTS.output_path + self.s.name + ".pex.sp"
spname = OPTS.output_path + self.s.name + ".sp"
verify.run_pex(self.s.name, gdsname, spname, output=pexname)
sp_file = pexname
print_time("Extraction", datetime.datetime.now(), start_time)
else:
# Use generated spice file for characterization
sp_file = spname
# Save a functional simulation file
# Characterize the design
start_time = datetime.datetime.now()
from characterizer import lib
debug.print_raw("LIB: Characterizing... ")
lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
print_time("Characterization", datetime.datetime.now(), start_time)
# Write the config file
start_time = datetime.datetime.now()
from shutil import copyfile
copyfile(OPTS.config_file, OPTS.output_path + OPTS.output_name + '.py')
debug.print_raw(
"Config: Writing to {0}".format(OPTS.output_path +
OPTS.output_name + '.py'))
print_time("Config", datetime.datetime.now(), start_time)
# Write the datasheet
start_time = datetime.datetime.now()
from datasheet_gen import datasheet_gen
dname = OPTS.output_path + self.s.name + ".html"
debug.print_raw("Datasheet: Writing to {0}".format(dname))
datasheet_gen.datasheet_write(dname)
print_time("Datasheet", datetime.datetime.now(), start_time)
# Write a verilog model
start_time = datetime.datetime.now()
vname = OPTS.output_path + self.s.name + ".v"
debug.print_raw("Verilog: Writing to {0}".format(vname))
self.verilog_write(vname)
print_time("Verilog", datetime.datetime.now(), start_time)
# Write out options if specified
if OPTS.output_extended_config:
start_time = datetime.datetime.now()
oname = OPTS.output_path + OPTS.output_name + "_extended.py"
debug.print_raw("Extended Config: Writing to {0}".format(oname))
self.extended_config_write(oname)
print_time("Extended Config", datetime.datetime.now(), start_time)
def save(self):
""" Save all the output files while reporting time to do it as well. """
if not OPTS.netlist_only:
# Create a LEF physical model
start_time = datetime.datetime.now()
lefname = OPTS.output_path + self.s.name + ".lef"
debug.print_raw("LEF: Writing to {0}".format(lefname))
self.lef_write(lefname)
print_time("LEF", datetime.datetime.now(), start_time)
# Write the layout
start_time = datetime.datetime.now()
gdsname = OPTS.output_path + self.s.name + ".gds"
debug.print_raw("GDS: Writing to {0}".format(gdsname))
self.gds_write(gdsname)
print_time("GDS", datetime.datetime.now(), start_time)
# Save the spice file
start_time = datetime.datetime.now()
spname = OPTS.output_path + self.s.name + ".sp"
debug.print_raw("SP: Writing to {0}".format(spname))
self.sp_write(spname)
print_time("Spice writing", datetime.datetime.now(), start_time)
# Save the LVS file
start_time = datetime.datetime.now()
spname = OPTS.output_path + self.s.name + ".lvs"
debug.print_raw("LVS: Writing to {0}".format(spname))
self.lvs_write(spname)
print_time("LVS writing", datetime.datetime.now(), start_time)
# Save the extracted spice file
if OPTS.use_pex:
import verify
start_time = datetime.datetime.now()
# Output the extracted design if requested
sp_file = OPTS.output_path + "temp_pex.sp"
verify.run_pex(self.s.name, gdsname, spname, output=sp_file)
print_time("Extraction", datetime.datetime.now(), start_time)
else:
# Use generated spice file for characterization
sp_file = spname
# Characterize the design
start_time = datetime.datetime.now()
from characterizer import lib
debug.print_raw("LIB: Characterizing... ")
lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
print_time("Characterization", datetime.datetime.now(), start_time)
# Write the config file
start_time = datetime.datetime.now()
from shutil import copyfile
copyfile(OPTS.config_file, OPTS.output_path + OPTS.output_name + '.py')
debug.print_raw(
"Config: Writing to {0}".format(OPTS.output_path +
OPTS.output_name + '.py'))
print_time("Config", datetime.datetime.now(), start_time)
# Write the datasheet
start_time = datetime.datetime.now()
from datasheet_gen import datasheet_gen
dname = OPTS.output_path + self.s.name + ".html"
debug.print_raw("Datasheet: Writing to {0}".format(dname))
datasheet_gen.datasheet_write(dname)
print_time("Datasheet", datetime.datetime.now(), start_time)
# Write a verilog model
start_time = datetime.datetime.now()
vname = OPTS.output_path + self.s.name + ".v"
debug.print_raw("Verilog: Writing to {0}".format(vname))
self.verilog_write(vname)
print_time("Verilog", datetime.datetime.now(), start_time)
