def make_ckt(self):
f = StringIO(dedent(
"""\
.macromodel pch_mac pmos d g s b m=1
+cga='1fF/(1um * 20nm)'
+cg="m * w * l * cga"
.macromodel nch_mac nmos d g s b m=1
+cga='1fF/(1um * 20nm)'
+cg="m * w * l * cga"
.subckt pinv a y vdd vss wp=1 wn=1
xmp y a vdd vdd pch_mac w=wp l=1
xmn y a vss vss nch_mac W=wn l=1
.ends
.subckt inv a y vdd vss wp=1 wn=1
xi0 a y vdd vss pinv wp=wp wn=wn
.ends
.subckt buf a y vdd vss wp=2 wn=2
xi0 a n vdd vss inv wp=wp wn=wn
xi1 n y vdd vss inv wp="2*wp" wn="2*wn"
.ends
"""))
f.name = "<string>"
ckt = Ckt()
ckt.read_spice(f)
return ckt
def make_ckt(self):
f = StringIO(dedent(
"""\
.macromodel pch_mac pmos d g s b m=1
+cga='1fF/(1um * 20nm)'
+cg="m * w * l * cga"
.macromodel nch_mac nmos d g s b m=1
+cga='1fF/(1um * 20nm)'
+cg="m * w * l * cga"
.subckt pinv a y vdd vss w=2 l=2.0
xmp y a vdd vdd pch_mac w="2*W" l=1.0
xmn y a vss vss nch_mac W=w l=1.0
.ends
.subckt buf a y vdd vss w1=0 w2=3 w3=5
xi1 a n vdd vss pinv
xi2 n y vdd vss pinv w='(w2)'
xi3 n y vdd vss pinv w=w3 l=5
.ends
"""))
f.name = "<string>"
ckt = Ckt()
ckt.read_spice(f)
return ckt
def test_simple(self):
f = StringIO(dedent(
"""\
.macromodel nch_mac nmos d g s b w=1 l=1
+ cg="w * l * 0.05" $ gate cap (F)
"""))
f.name = "<string>"
ckt = Ckt()
ckt.read_spice(f)
assert ckt.prims.get('nch_mac').name == 'nch_mac'
assert ckt.prims.get('nch_mac').type == 'nmos'
assert ckt.prims.get('nch_mac').portnames == ['d', 'g', 's', 'b']
def make_ckt(self):
f = StringIO(dedent(
"""\
.macromodel pch_mac pmos d g s b m=1 cg="m*w*l*0.05"
.macromodel nch_mac nmos d g s b m=1 cg="m*w*l*0.05"
.subckt pinv a y vdd vss w=2 l=2.0
xmp y a vdd vdd pch_mac w="2*W" l=1.0
xmn y a vss vss nch_mac W=w l=1.0
.ends
"""))
f.name = "<string>"
ckt = Ckt()
ckt.read_spice(f)
return ckt