def sim_snk_bfm(): reset = Signal(bool(0)) clk = Signal(bool(0)) elapsed_time = Signal(0) snk_bfm_inst = snk_bfm(reset, clk, ready_i_pattern, asi_snk, src_bfm_o) clkgen = clk_driver(elapsed_time, clk, period=20) @always(clk.posedge) def stimulus(): if elapsed_time > 40: reset.next = 0 if elapsed_time > 80: asi_snk.valid_i.next = 1 asi_snk.data_i.next = 0xab if elapsed_time > 220: asi_snk.valid_i.next = 0 asi_snk.data_i.next = 0xab if elapsed_time > 320: asi_snk.valid_i.next = 1 asi_snk.data_i.next = 0x1e @always(clk.posedge) def receive_data_process(): global nb2 global recv_data if (src_bfm_o.valid_o == 1): nb2 += 1 print(str(nb2) + ". Received data:", ": ", src_bfm_o.data_o) recv_data.append(int(src_bfm_o.data_o)) return snk_bfm_inst, clkgen, stimulus, receive_data_process
def sim_src_bfm(): reset = Signal(bool(1)) clk = Signal(bool(0)) src_bfm_i.data_i = Signal(intbv(0x0a)[DATA_WIDTH:]) elapsed_time = Signal(0) src_bfm_inst = src_bfm(reset, clk, valid_i_pattern, src_bfm_i, aso_src) class num_counter: nb = 0 clkgen = clk_driver(elapsed_time, clk, period=20) @always(clk.posedge) def stimulus(): if elapsed_time > 40: reset.next = 0 if elapsed_time > 100: aso_src.ready_i.next = 1 if elapsed_time > 140: aso_src.ready_i.next = 0 if elapsed_time > 220: aso_src.ready_i.next = 1 if elapsed_time > 240: aso_src.ready_i.next = 0 if elapsed_time > 400: aso_src.ready_i.next = 1 @always(clk.posedge) def data_increment(): if aso_src.ready_i == 1 and aso_src.valid_o == 1: src_bfm_i.data_i.next = src_bfm_i.data_i + 1 num_counter.nb += 1 print( str(num_counter.nb) + ". Prepared data:", hex(src_bfm_i.data_i), ": ", src_bfm_i.data_i) return src_bfm_inst, clkgen, stimulus, data_increment
def sim_streaming_chain_adder(pars_obj): # removing the files if already available for i in range(NB_CHAIN_ADDERS): txdata0_filename[i] = "transmit_data_inpA_adder{:d}.log".format(i) if (os.path.exists(txdata0_filename[i])): os.remove(txdata0_filename[i]) txdata1_filename[i] = "transmit_data_inpB_adder{:d}.log".format(i) if (os.path.exists(txdata1_filename[i])): os.remove(txdata1_filename[i]) rxdata_filename[i] = "receive_data_adder{:d}.log".format(i) if (os.path.exists(rxdata_filename[i])): os.remove(rxdata_filename[i]) reset = Signal(bool(1)) clk = Signal(bool(0)) elapsed_time = Signal(0) nb_transmit = [Signal(int(0)) for i in range(NB_CHAIN_ADDERS)] nb_transmit0 = [Signal(int(0)) for i in range(NB_CHAIN_ADDERS)] nb_transmit1 = [Signal(int(0)) for i in range(NB_CHAIN_ADDERS)] nb_receive = [Signal(int(0)) for i in range(NB_CHAIN_ADDERS)] av_src0_bfm = [ AvalonST_SRC(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_ADDERS) ] av_src1_bfm = [ AvalonST_SRC(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_ADDERS) ] av_snk0 = [AvalonST_SNK(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_ADDERS)] av_snk1 = [AvalonST_SNK(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_ADDERS)] av_src = [AvalonST_SRC(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_ADDERS)] av_snk_bfm = [ AvalonST_SNK(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_ADDERS) ] src_bfm_i = [ AvalonST_SNK(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_ADDERS) ] src_bfm_0 = [ AvalonST_SNK(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_ADDERS) ] src_bfm_1 = [ AvalonST_SNK(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_ADDERS) ] src_bfm_o = [ AvalonST_SRC(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_ADDERS) ] clkgen = clk_driver(elapsed_time, clk, period=20) add_i = [None for i in range(NB_CHAIN_ADDERS)] src0_bfm_inst = [None for i in range(NB_CHAIN_ADDERS)] src1_bfm_inst = [None for i in range(NB_CHAIN_ADDERS)] streaming_chain_adder_inst = None snk_bfm_inst = [None for i in range(NB_CHAIN_ADDERS)] VALID_PATTERN0 = [ random.randint(0x0100, 0xffff) for i in range(NB_CHAIN_ADDERS) ] VALID_PATTERN1 = [ random.randint(0x0100, 0xffff) for i in range(NB_CHAIN_ADDERS) ] READY_PATTERN = [ random.randint(0x0100, 0xffff) for i in range(NB_CHAIN_ADDERS) ] for i in range(NB_CHAIN_ADDERS): print("Chain Adder: " + str(i) + " Valid0: " + str(VALID_PATTERN0[i]) + " Valid1: " + str(VALID_PATTERN1[i]) + " Ready: " + str(READY_PATTERN[i])) src0_bfm_inst[i] = src_bfm(reset, clk, VALID_PATTERN0[i], src_bfm_0[i], av_src0_bfm[i]) src1_bfm_inst[i] = src_bfm(reset, clk, VALID_PATTERN1[i], src_bfm_1[i], av_src1_bfm[i]) snk_bfm_inst[i] = snk_bfm(reset, clk, READY_PATTERN[i], av_snk_bfm[i], src_bfm_o[i]) add_pars = StreamingChainAdderPars() add_pars.SNK0_DATAWIDTH = STREAM_DATA_WIDTH add_pars.SNK1_DATAWIDTH = STREAM_DATA_WIDTH add_pars.SRCD_ATAWIDTH = STREAM_DATA_WIDTH add_pars.NB_CHAIN_ADDERS = NB_CHAIN_ADDERS add_pars(add_pars) add_i = StreamingChainAdder() streaming_chain_adder_inst = add_i.block_connect(add_pars, reset, clk, av_snk0, av_snk1, av_src) snk0_valid_inst = [None for i in range(NB_CHAIN_ADDERS)] snk0_data_inst = [None for i in range(NB_CHAIN_ADDERS)] snk0_ready_inst = [None for i in range(NB_CHAIN_ADDERS)] snk1_valid_inst = [None for i in range(NB_CHAIN_ADDERS)] snk1_data_inst = [None for i in range(NB_CHAIN_ADDERS)] snk1_ready_inst = [None for i in range(NB_CHAIN_ADDERS)] src_valid_inst = [None for i in range(NB_CHAIN_ADDERS)] src_data_inst = [None for i in range(NB_CHAIN_ADDERS)] src_ready_inst = [None for i in range(NB_CHAIN_ADDERS)] for i in range(NB_CHAIN_ADDERS): snk0_valid_inst[i] = simple_wire_assign(av_snk0[i].valid_i, av_src0_bfm[i].valid_o) snk0_data_inst[i] = simple_wire_assign(av_snk0[i].data_i, av_src0_bfm[i].data_o) snk0_ready_inst[i] = simple_wire_assign(av_src0_bfm[i].ready_i, av_snk0[i].ready_o) snk1_valid_inst[i] = simple_wire_assign(av_snk1[i].valid_i, av_src1_bfm[i].valid_o) snk1_data_inst[i] = simple_wire_assign(av_snk1[i].data_i, av_src1_bfm[i].data_o) snk1_ready_inst[i] = simple_wire_assign(av_src1_bfm[i].ready_i, av_snk1[i].ready_o) src_valid_inst[i] = simple_wire_assign(av_snk_bfm[i].valid_i, av_src[i].valid_o) src_data_inst[i] = simple_wire_assign(av_snk_bfm[i].data_i, av_src[i].data_o) src_ready_inst[i] = simple_wire_assign(av_src[i].ready_i, av_snk_bfm[i].ready_o) @always(clk.posedge) def stimulus(): if elapsed_time == 40: reset.next = 0 INIT_DATA0 = [random.randint(1, RANDRANGE) for i in range(NB_CHAIN_ADDERS)] INIT_DATA1 = [random.randint(1, RANDRANGE) for i in range(NB_CHAIN_ADDERS)] data_in0 = [Signal(int(0)) for i in range(NB_CHAIN_ADDERS)] data_in1 = [Signal(int(0)) for i in range(NB_CHAIN_ADDERS)] src_bfm_0_valid_inst = [None for i in range(NB_CHAIN_ADDERS)] src_bfm_1_valid_inst = [None for i in range(NB_CHAIN_ADDERS)] src_bfm_0_data_inst = [None for i in range(NB_CHAIN_ADDERS)] src_bfm_1_data_inst = [None for i in range(NB_CHAIN_ADDERS)] for i in range(NB_CHAIN_ADDERS): src_bfm_0_data_inst[i] = conditional_wire_assign( src_bfm_0[i].data_i, (av_src0_bfm[i].ready_i and av_src0_bfm[i].valid_o), data_in0[i], src_bfm_0[i].data_i) src_bfm_1_data_inst[i] = conditional_wire_assign( src_bfm_1[i].data_i, (av_src1_bfm[i].ready_i and av_src1_bfm[i].valid_o), data_in1[i], src_bfm_1[i].data_i) for i in range(NB_CHAIN_ADDERS): src_bfm_0_valid_inst[i] = conditional_wire_assign_lt( src_bfm_0[i].valid_i, nb_transmit0[i], Signal(MAX_NB_TRANSFERS), 1, 0) src_bfm_1_valid_inst[i] = conditional_wire_assign_lt( src_bfm_1[i].valid_i, nb_transmit1[i], Signal(MAX_NB_TRANSFERS), 1, 0) data_in0_inst = [None for i in range(NB_CHAIN_ADDERS)] data_in1_inst = [None for i in range(NB_CHAIN_ADDERS)] nb_transmit0_inst = [None for i in range(NB_CHAIN_ADDERS)] nb_transmit1_inst = [None for i in range(NB_CHAIN_ADDERS)] transmit_data0_append_inst = [None for i in range(NB_CHAIN_ADDERS)] transmit_data1_append_inst = [None for i in range(NB_CHAIN_ADDERS)] receive_data_append_inst = [None for i in range(NB_CHAIN_ADDERS)] #Datain is randomized values (for next valid data) for i in range(NB_CHAIN_ADDERS): data_in0_inst[i] = conditional_random_generator( reset, clk, data_in0[i], int(INIT_DATA0[i]), (av_src0_bfm[i].ready_i and av_src0_bfm[i].valid_o and src_bfm_0[i].valid_i), RANDRANGE) data_in1_inst[i] = conditional_random_generator( reset, clk, data_in1[i], int(INIT_DATA1[i]), (av_src1_bfm[i].ready_i and av_src1_bfm[i].valid_o and src_bfm_1[i].valid_i), RANDRANGE) nb_transmit0_inst[i] = conditional_reg_counter( reset, clk, nb_transmit0[i], Reset.LOW, (av_src0_bfm[i].ready_i and av_src0_bfm[i].valid_o and src_bfm_0[i].valid_i)) nb_transmit1_inst[i] = conditional_reg_counter( reset, clk, nb_transmit1[i], Reset.LOW, (av_src1_bfm[i].ready_i and av_src1_bfm[i].valid_o and src_bfm_1[i].valid_i)) transmit_data0_append_inst[i] = conditional_clocked_appendfile( reset, clk, (av_src0_bfm[i].ready_i and av_src0_bfm[i].valid_o and src_bfm_0[i].valid_i), data_in0[i], txdata0_filename[i]) transmit_data1_append_inst[i] = conditional_clocked_appendfile( reset, clk, (av_src1_bfm[i].ready_i and av_src1_bfm[i].valid_o and src_bfm_1[i].valid_i), data_in1[i], txdata1_filename[i]) receive_data_append_inst[i] = conditional_clocked_appendfile( reset, clk, (src_bfm_o[i].valid_o), src_bfm_o[i].data_o, rxdata_filename[i]) recv_inst = [None for i in range(NB_CHAIN_ADDERS)] for i in range(NB_CHAIN_ADDERS): recv_inst[i] = conditional_reg_counter(reset, clk, nb_receive[i], Reset.LOW, src_bfm_o[i].valid_o) @always(clk.posedge) def receive_data_process(): TIME_SHUTDOWN = 5000 nb_recv = 0 sim_time_now = now() for i in range(NB_CHAIN_ADDERS): nb_recv += nb_receive[i] if (nb_recv == NB_CHAIN_ADDERS * (MAX_NB_TRANSFERS)): for i in range(NB_CHAIN_ADDERS): print("INF242: adder: " + str(i) + " Num ready pulses: " + str(int(ready_pulses[i]))) raise StopSimulation("Simulation Finished in %d clks: In total " % now() + str(nb_recv) + " data words received") @always(clk.posedge) def simulation_time_check(): sim_time_now = now() if (sim_time_now > MAX_SIM_TIME): raise StopSimulation( "Warning! Simulation Exited upon reaching max simulation time of " + str(MAX_SIM_TIME) + " clocks") ready_pulse_cnt_inst = [None for i in range(NB_CHAIN_ADDERS)] for i in range(NB_CHAIN_ADDERS): ready_pulse_cnt_inst[i] = conditional_reg_counter( reset, clk, ready_pulses[i], Reset.LOW, (av_snk_bfm[i].ready_o)) return instances()
def sim_streaming_ip_comb(pars_obj): PATTERN_WIDTH = 16 DATA_WIDTH = 8 reset = Signal(bool(1)) clk = Signal(bool(0)) elapsed_time=Signal(0) data_enable = Signal(bool(0)) asi_snk_bfm = AvalonST_SNK(DATA_WIDTH) av_snk_dut = AvalonST_SNK(DATA_WIDTH) aso_src_bfm = AvalonST_SRC(DATA_WIDTH) av_src_dut = AvalonST_SRC(DATA_WIDTH) src_bfm_i = AvalonST_SNK(DATA_WIDTH) src_bfm_o = AvalonST_SRC(DATA_WIDTH) clkgen=clk_driver(elapsed_time,clk,period=20) src_bfm_inst = src_bfm(reset, clk, pars_obj.valid, src_bfm_i, aso_src_bfm) streaming_ip_comb_inst = streaming_ip_comb(reset, clk, av_snk_dut, av_src_dut, data_enable ) snk_bfm_inst = snk_bfm(reset, clk, pars_obj.ready, asi_snk_bfm, src_bfm_o) print("Ready Pattern: ", str(hex(pars_obj.ready))) print("Valid Pattern: ", str(hex(pars_obj.valid))) @always_comb def beh_comb_logic(): # Streaming Input Interface av_snk_dut.valid_i.next = aso_src_bfm.valid_o av_snk_dut.data_i.next = aso_src_bfm.data_o aso_src_bfm.ready_i.next = av_snk_dut.ready_o #Streaming Output interface asi_snk_bfm.valid_i.next = av_src_dut.valid_o asi_snk_bfm.data_i.next = av_src_dut.data_o av_src_dut.ready_i.next = asi_snk_bfm.ready_o src_bfm_i.valid_i.next = 1 if (nb1 < MAX_NB_TRANSFERS) else 0 @always_comb def beh_comb_logic_enable(): #data_enable av_src_dut.data_o.next = av_snk_dut.data_i @always(clk.posedge) def stimulus(): if elapsed_time > 40: reset.next = 0 INIT_DATA=1 data_in=Signal(int(0)) @always_comb def transmit_data_process(): if (aso_src_bfm.ready_i == 1 and aso_src_bfm.valid_o == 1): src_bfm_i.data_i.next = data_in #Dataout is just an increment (for next valid data) @always(clk.posedge, reset.posedge) def transmit_data_clk_process(): global trans_data,nb1 if reset==1: data_in.next = int(INIT_DATA) elif (aso_src_bfm.ready_i == 1 and aso_src_bfm.valid_o == 1 and src_bfm_i.valid_i == 1): nb1+=1 #print str(nb1) + ". Transmitted data to src bfm:", ": ", src_bfm_i.data_i trans_data.append(int(data_in)) data_in.next = data_in + 1 @always(clk.posedge) def receive_data_process(): global recv_data,nb2 if (src_bfm_o.valid_o == 1): nb2+=1 #print str(nb2) + ". Received data from sink bfm:", ": ", src_bfm_o.data_o recv_data.append(int(src_bfm_o.data_o)) sim_time_now=now() if (nb2 == MAX_NB_TRANSFERS): raise StopSimulation("Simulation Finished in %d clks: In total " %now() + str(MAX_NB_TRANSFERS) + " data words received") @always(clk.posedge) def simulation_time_check(): sim_time_now=now() if(sim_time_now>MAX_SIM_TIME): raise StopSimulation("Warning! Simulation Exited upon reaching max simulation time of " + str(MAX_SIM_TIME) + " clocks") @always(clk.posedge) def cnt_ready_pulses(): global ready_pulses if (asi_snk_bfm.ready_o == 1): ready_pulses+=1 #print "ready received from bfm" return instances()
def sim_command_pipeline(pars_obj): global test_decimal_shift, theta_decimal_shift #------------------ Initializing Pipeline depths --------------- NB_PIPELINE_STAGES = 5 DATAWIDTH = 32 #-------------- Simulation Initialisations --------------------- reset = Signal(bool(1)) clk = Signal(bool(0)) elapsed_time = Signal(0) clkgen = clk_driver(elapsed_time, clk, period=20) #---------------------------------------------------------------- #----------------- Initializing Pipeline Streams ---------------- # --- Pipeline Pars pars = OperandPipelinePars() pars.NB_PIPELINE_STAGES = NB_PIPELINE_STAGES pars.DATAWIDTH = DATAWIDTH pars.CHANNEL_WIDTH = 2 global floatDataBus if (True == floatDataBus): pars.INIT_DATA = 0.0 # requires floating point computation else: pars.INIT_DATA = 0 # requires intbv computation # --- Initializing Pipeline A pipe_inpA = PipelineST(pars.DATAWIDTH, pars.CHANNEL_WIDTH, pars.INIT_DATA) pipe_outA = PipelineST(pars.DATAWIDTH, pars.CHANNEL_WIDTH, pars.INIT_DATA) operand_a = OperandPipeline() ioA = OperandPipelineIo() ioA(pars) # --- Initializing Pipeline B pipe_inpB = PipelineST(pars.DATAWIDTH, pars.CHANNEL_WIDTH, pars.INIT_DATA) pipe_outB = PipelineST(pars.DATAWIDTH, pars.CHANNEL_WIDTH, pars.INIT_DATA) operand_b = OperandPipeline() ioB = OperandPipelineIo() ioB(pars) # --- Initializing Command Pipeline pipe_multRes = PipelineST(pars.DATAWIDTH, pars.CHANNEL_WIDTH, pars.INIT_DATA) multcmdFile = '../tests/mult_pipeline.list' parsMult = CommandPipelinePars() parsMult.DATAWIDTH = pars.DATAWIDTH parsMult.CHANNEL_WIDTH = pars.CHANNEL_WIDTH parsMult.INIT_DATA = pars.INIT_DATA parsMult.STAGE_NB = 1 parsMult(parsMult, multcmdFile) multPipe = CommandPipeline() ioMult = CommandPipelineIo() ioMult(pars) # ---- Initializing Accumulator Block pipe_out_acc = PipelineST(pars.DATAWIDTH, pars.CHANNEL_WIDTH, pars.INIT_DATA) parsAcc = AccumulatorPars() parsAcc.DATAWIDTH = pars.DATAWIDTH parsAcc.CHANNEL_WIDTH = pars.CHANNEL_WIDTH parsAcc.INIT_DATA = pars.INIT_DATA global LEN_THETA parsAcc.NB_ACCUMULATIONS = LEN_THETA accuPipe = Accumulator() accuPipe(parsAcc) # ---- Initializing Activation Block parsActiv = ActivationPars() parsActiv.DATAWIDTH = 3 # 0 or 1 for classification parsActiv.CHANNEL_WIDTH = pars.CHANNEL_WIDTH parsActiv.INIT_DATA = pars.INIT_DATA pipe_out_activ = PipelineST(pars.DATAWIDTH, pars.CHANNEL_WIDTH, pars.INIT_DATA) activPipe = Activation() activPipe(parsActiv) #---------------------------------------------------------------- #----------------- Connecting Pipeline Blocks ------------------- inst = [] inst.append( operand_a.block_connect(pars, reset, clk, pipe_inpA, pipe_outA, ioA)) inst.append( operand_b.block_connect(pars, reset, clk, pipe_inpB, pipe_outB, ioB)) #---------------------------------------------------------------- #----------------- Connecting Command Pipeline ------------------- # Mult Pipeline inst.append( multPipe.block_connect(parsMult, reset, clk, ioA, ioB, pipe_multRes, ioMult)) #---------------------------------------------------------------- #----------------- Connecting Accumulator -------------- # Accu inst.append( accuPipe.block_connect(parsAcc, reset, clk, 0, pipe_multRes, pipe_out_acc)) #---------------------------------------------------------------- #----------------- Connecting Activation -------------- # Simple Step Activation function inst.append( activPipe.block_step_connect(parsActiv, reset, clk, pipe_out_acc, pipe_out_activ)) #---------------------------------------------------------------- #----------------- Logistic Regression Test File ------------------- lr_test_file = "../tests/ex2data1.txt" lr_theta_file = "../tests/theta1.txt" #--- Loading Test and Theta Values test_file_list = [] theta_file_list = [] nb_training_examples = 0 # Loading test data with open(lr_test_file, 'r') as f: d0 = 1.0 # Always first element is 1 for line in f: #print line d1, d2, y = line.split(',') d0 = round(float(d0), DEF_ROUND) d1 = round(float(d1), DEF_ROUND) d2 = round(float(d2), DEF_ROUND) test_file_list.extend([d0, d1, d2]) label.extend([int(y)]) nb_training_examples += 1 #loading theta with open(lr_theta_file, 'r') as f: t0, t1, t2 = (f.read().split('\n')[0]).split(',') t0 = round(float(t0), DEF_ROUND) t1 = round(float(t1), DEF_ROUND) t2 = round(float(t2), DEF_ROUND) for i in range(nb_training_examples): theta_file_list.extend([t0, t1, t2]) # exp10 shifts done for theta and test data as per requirements when intbv used if (False == floatDataBus): test_file_list = [ int(i * (10**test_decimal_shift)) for i in test_file_list ] theta_file_list = [ int(i * (10**theta_decimal_shift)) for i in theta_file_list ] #print test_file_list #print theta_file_list #---------------------------------------------------------------- #----------------- Shift Enable for pipeData ------------------- shiftEn_i = Signal(bool(0)) @always(clk.posedge, reset.posedge) def shift_signal(): if reset: shiftEn_i.next = 1 else: shiftEn_i.next = not shiftEn_i @always_comb def shiftOperand_signal(): ioB.shiftEn_i.next = shiftEn_i ioA.shiftEn_i.next = shiftEn_i #---------------------------------------------------------------- #----------------- Reset For the Module -------------------- @always(clk.posedge) def stimulus(): if elapsed_time == 40: reset.next = 0 #---------------------------------------------------------------- #----------------- Input Data for the Modules -------------------- @always_comb def transmit_data_process(): global line_nb if (shiftEn_i == 1 and nbTA == nbTB and nbTA < MAX_NB_TRANSFERS): pipe_inpA.data.next = (test_file_list[line_nb]) pipe_inpA.valid.next = 1 pipe_inpB.data.next = (theta_file_list[line_nb]) pipe_inpB.valid.next = 1 line_nb += 1 else: pipe_inpA.valid.next = 0 pipe_inpB.valid.next = 0 #---------------------------------------------------------------- #----------------- Storing Transmitted Data -------------------- @always(clk.posedge, reset.posedge) def trans_dataA_process(): global trans_dataA, trans_dataB, nbTA if reset == 1: pass elif (pipe_inpA.valid == 1 and nbTA < MAX_NB_TRANSFERS): nbTA += 1 trans_dataA.extend([pipe_inpA.data]) @always(clk.posedge, reset.posedge) def trans_dataB_process(): global trans_dataA, trans_dataB, nbTB if reset == 1: pass elif (pipe_inpB.valid == 1 and nbTB < MAX_NB_TRANSFERS): nbTB += 1 trans_dataB.extend([pipe_inpB.data]) #---------------------------------------------------------------- #----------------- Storing Received Data ----------------------- @always(clk.posedge) def receive_data_process(): global recv_data, nbR, acc_out # Collecting multiplier data if (pipe_multRes.valid == 1): if (False == floatDataBus): mult_out = pipe_multRes.data else: mult_out = (round(pipe_multRes.data, DEF_ROUND)) recv_data.extend([mult_out]) # Collecting Activation Data if (pipe_out_activ.valid == 1): nbR += LEN_THETA predict = int(pipe_out_activ.data) prediction_res.extend([predict]) if __debug__: print(" prediction: {:d}".format(predict)) if (nbR == MAX_NB_TRANSFERS): raise StopSimulation( "Simulation Finished in %d clks: In total " % now() + str(MAX_NB_TRANSFERS) + " data words received") # Collecting Accumulator Data if (pipe_out_acc.valid == 1): acc_out = pipe_out_acc.data #prob=(1.0/(1+ (math.exp(-1.0*acc_out) ))) # Sigmoid activation Function if __debug__: if (False == floatDataBus): print("{0:d} Acc: {1:d} ".format(int(nbR / LEN_THETA + 1), int(acc_out), i=DEF_ROUND), end=' ') else: print("{0:d} Acc: {1:0.{i}f}".format(int(nbR / LEN_THETA + 1), float(acc_out), i=DEF_ROUND), end=' ') if (False == floatDataBus): acc_out_list.extend([int(acc_out)]) else: acc_out_list.extend([round(acc_out, DEF_ROUND)]) #print "nbR:" + str(nbR) #---------------------------------------------------------------- #----------------- Max Simulation Time Exit Condition ----------- @always(clk.posedge) def simulation_time_check(): sim_time_now = now() if (sim_time_now > MAX_SIM_TIME): raise StopSimulation( "Warning! Simulation Exited upon reaching max simulation time of " + str(MAX_SIM_TIME) + " clocks") #---------------------------------------------------------------- return instances()
from clk_driver import clk_driver from sdram_cntl import * clk_i = Signal(bool(0)) rst_i = ResetSignal(0, active=1, async=True) clkDriver_Inst = clk_driver(clk_i) sd_intf_Inst = SdramIntf() host_intf_Inst = HostIntf() sdramCntl_Inst = sdram_cntl(clk_i, host_intf_Inst, sd_intf_Inst) toVerilog(sdram_cntl, clk_i, host_intf_Inst, sd_intf_Inst) toVHDL(sdram_cntl, clk_i, host_intf_Inst, sd_intf_Inst)
yield sd_intf.nop(clk) yield delay(10000) yield sd_intf.load_mode(clk) yield sd_intf.nop(clk) yield sd_intf.activate(clk, 17) yield sd_intf.nop(clk) yield delay(10000) yield sd_intf.write(clk, driver, 20, 31) yield sd_intf.nop(clk) yield delay(100) yield sd_intf.read(clk, 20) yield sd_intf.nop(clk) yield delay(4) print("sd_intf dq = ", sd_intf.dq.val, " @ ", now()) return test clk = Signal(bool(0)) clk_driver_Inst = clk_driver(clk) sd_intf_Inst = SdramIntf() sdram_Inst = sdram(clk, sd_intf_Inst) test_readWrite_Inst = test_readwrite(clk, sd_intf_Inst) sim = Simulation(clk_driver_Inst, sdram_Inst, test_readWrite_Inst) sim.run(25000)
def sim_operand_pipeline(pars_obj): NB_PIPELINE_STAGES = 10 DATAWIDTH = 32 reset = Signal(bool(1)) clk = Signal(bool(0)) elapsed_time = Signal(0) clkgen = clk_driver(elapsed_time, clk, period=20) pipe_inpA = PipelineST(DATAWIDTH) pipe_outA = PipelineST(DATAWIDTH) pipe_inpB = PipelineST(DATAWIDTH) pipe_outB = PipelineST(DATAWIDTH) operand_a = OperandPipeline() pars = OperandPipelinePars() pars.NB_PIPELINE_STAGES = NB_PIPELINE_STAGES pars.DATAWIDTH = DATAWIDTH pars(pars) ioA = OperandPipelineIo() ioA(pars) inst = [] inst.append( operand_a.block_connect(pars, reset, clk, pipe_inpA, pipe_outA, ioA)) operand_b = OperandPipeline() ioB = OperandPipelineIo() ioB(pars) inst.append( operand_b.block_connect(pars, reset, clk, pipe_inpB, pipe_outB, ioB)) mult = Signal(intbv(DATAWIDTH + DATAWIDTH)) @always(clk.posedge, reset.posedge) def mult_process(): if reset == 1: mult.next = intbv(0) elif (ioA.stage_o[5].valid == 1 and ioB.stage_o[5].valid == 1): mult.next = mult + ioA.stage_o[5].data * ioB.stage_o[5].data shiftEn_i = Signal(bool(0)) @always(clk.posedge) def shift_signal(): shiftEn_i.next = not shiftEn_i @always_comb def shiftOperand_signal(): ioB.shiftEn_i.next = shiftEn_i ioA.shiftEn_i.next = shiftEn_i @always(clk.posedge) def stimulus(): if elapsed_time == 40: reset.next = 0 INIT_DATA = 1 data_in = Signal(int(0)) @always_comb def transmit_data_process(): if (shiftEn_i == 1 and nb1 < MAX_NB_TRANSFERS): pipe_inpA.data.next = data_in pipe_inpA.valid.next = 1 pipe_inpB.data.next = data_in pipe_inpB.valid.next = 1 else: pipe_inpA.valid.next = 0 pipe_inpB.valid.next = 0 #Dataout is just an increment (for next valid data) @always(clk.posedge, reset.posedge) def transmit_data_clk_process(): global trans_data, nb1 if reset == 1: data_in.next = int(INIT_DATA) elif (shiftEn_i == 1 and nb1 < MAX_NB_TRANSFERS): nb1 += 1 #print str(nb1) + ". Transmitted data to src bfm:", ": ", src_bfm_i.data_i trans_data.append(int(data_in)) data_in.next = data_in + 1 @always(clk.posedge) def receive_data_process(): global recv_data, nb2 if (pipe_outA.valid == 1): nb2 += 1 #print str(nb2) + ". Received data from sink bfm:", ": ", src_bfm_o.data_o recv_data.append(int(pipe_outA.data)) sim_time_now = now() if (nb2 == MAX_NB_TRANSFERS + NB_PIPELINE_STAGES): raise StopSimulation( "Simulation Finished in %d clks: In total " % now() + str(MAX_NB_TRANSFERS) + " data words received") @always(clk.posedge) def simulation_time_check(): sim_time_now = now() if (sim_time_now > MAX_SIM_TIME): raise StopSimulation( "Warning! Simulation Exited upon reaching max simulation time of " + str(MAX_SIM_TIME) + " clocks") return instances()
sd_intf.cke.next = 1 yield sd_intf.nop(clk) yield delay(10000) yield sd_intf.load_mode(clk) yield sd_intf.nop(clk) yield sd_intf.activate(clk, 17) yield sd_intf.nop(clk) yield delay(10000) yield sd_intf.write(clk, driver, 20, 31) yield sd_intf.nop(clk) yield delay(100) yield sd_intf.read(clk, 20) yield sd_intf.nop(clk) yield delay(4) print "sd_intf dq = ", sd_intf.dq.val, " @ ", now() return test clk = Signal(bool(0)) clk_driver_Inst = clk_driver(clk) sd_intf_Inst = SdramIntf() sdram_Inst = sdram(clk, sd_intf_Inst) test_readWrite_Inst = test_readwrite(clk, sd_intf_Inst) sim = Simulation(clk_driver_Inst, sdram_Inst, test_readWrite_Inst) sim.run(25000)
def sim_streaming_chain_mult(pars_obj): global rxdata_filename global txdata0_filename global txdata1_filename # removing the files if already available for i in range(NB_CHAIN_MULTIPLIERS): txdata0_filename[i] = "transmit_data_inpA_mult{:d}.log".format(i) if (os.path.exists(txdata0_filename[i])): os.remove(txdata0_filename[i]) txdata1_filename[i] = "transmit_data_inpB_mult{:d}.log".format(i) if (os.path.exists(txdata1_filename[i])): os.remove(txdata1_filename[i]) if (os.path.exists(rxdata_filename)): os.remove(rxdata_filename) reset = Signal(bool(1)) clk = Signal(bool(0)) elapsed_time = Signal(0) nb_transmit = [Signal(int(0)) for i in range(NB_CHAIN_MULTIPLIERS)] nb_transmit0 = [Signal(int(0)) for i in range(NB_CHAIN_MULTIPLIERS)] nb_transmit1 = [Signal(int(0)) for i in range(NB_CHAIN_MULTIPLIERS)] nb_receive = Signal(int(0)) av_src0_bfm = [ AvalonST_SRC(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_MULTIPLIERS) ] av_src1_bfm = [ AvalonST_SRC(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_MULTIPLIERS) ] av_snk0 = [ AvalonST_SNK(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_MULTIPLIERS) ] av_snk1 = [ AvalonST_SNK(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_MULTIPLIERS) ] av_snk_bfm = AvalonST_SNK(STREAM_DATA_WIDTH) src_bfm_i = [ AvalonST_SNK(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_MULTIPLIERS) ] src_bfm_0 = [ AvalonST_SNK(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_MULTIPLIERS) ] src_bfm_1 = [ AvalonST_SNK(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_MULTIPLIERS) ] src_bfm_o = AvalonST_SRC(STREAM_DATA_WIDTH) clkgen = clk_driver(elapsed_time, clk, period=20) src0_bfm_inst = [None for i in range(NB_CHAIN_MULTIPLIERS)] src1_bfm_inst = [None for i in range(NB_CHAIN_MULTIPLIERS)] snk_bfm_inst = None VALID_PATTERN0 = [ random.randint(0x0100, 0xffff) for i in range(NB_CHAIN_MULTIPLIERS) ] VALID_PATTERN1 = [ random.randint(0x0100, 0xffff) for i in range(NB_CHAIN_MULTIPLIERS) ] READY_PATTERN = [ random.randint(0x0100, 0xffff) for i in range(NB_CHAIN_MULTIPLIERS) ] for i in range(NB_CHAIN_MULTIPLIERS): print("Chain Mult: " + str(i) + " Valid0: " + str(VALID_PATTERN0[i]) + " Valid1: " + str(VALID_PATTERN1[i]) + " Ready: " + str(READY_PATTERN[i])) src0_bfm_inst[i] = src_bfm(reset, clk, VALID_PATTERN0[i], src_bfm_0[i], av_src0_bfm[i]) src1_bfm_inst[i] = src_bfm(reset, clk, VALID_PATTERN1[i], src_bfm_1[i], av_src1_bfm[i]) snk_bfm_inst = snk_bfm(reset, clk, READY_PATTERN[0], av_snk_bfm, src_bfm_o) i = NB_CHAIN_MULTIPLIERS * 2 nb_chain_mults = 0 nb_chain_mults_list = [] mod_list = [] nb_mult_stages = 0 while i > 1: mod_val = 0 if (i % 2 == 0 or i == 1) else 1 mod_list.append(mod_val) i = i / 2 if (i % 2 == 0) else i / 2 + 1 nb_chain_mults += i nb_chain_mults_list.append(i) nb_mult_stages += 1 print("nb_chain_mults: " + str(nb_chain_mults)) print("nb_mult_stages: " + str(nb_mult_stages)) print("mod_list: " + str(mod_list)) print("nb_chain_mults_list: " + str(nb_chain_mults_list)) av_snk0_cmb = [[ AvalonST_SNK(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_MULTIPLIERS) ] for j in range(nb_mult_stages)] av_snk1_cmb = [[ AvalonST_SNK(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_MULTIPLIERS) ] for j in range(nb_mult_stages)] av_src = [[ AvalonST_SRC(STREAM_DATA_WIDTH) for i in range(NB_CHAIN_MULTIPLIERS) ] for j in range(nb_mult_stages)] snk0_valid_inst = [None for i in range(NB_CHAIN_MULTIPLIERS)] snk0_data_inst = [None for i in range(NB_CHAIN_MULTIPLIERS)] snk0_ready_inst = [None for i in range(NB_CHAIN_MULTIPLIERS)] snk1_valid_inst = [None for i in range(NB_CHAIN_MULTIPLIERS)] snk1_data_inst = [None for i in range(NB_CHAIN_MULTIPLIERS)] snk1_ready_inst = [None for i in range(NB_CHAIN_MULTIPLIERS)] src_valid_inst = None src_data_inst = None src_ready_inst = None streaming_chain_mult_inst = [None for i in range(nb_mult_stages)] add_i = [None for i in range(nb_mult_stages)] add_pars = [None for i in range(nb_mult_stages)] snk0_inst = [] snk1_inst = [] for i in range(nb_mult_stages): add_pars[i] = StreamingChainMultPars() add_pars[i].SNK0_DATAWIDTH = STREAM_DATA_WIDTH add_pars[i].SNK1_DATAWIDTH = STREAM_DATA_WIDTH add_pars[i].SRC_DATAWIDTH = STREAM_DATA_WIDTH add_pars[i].NB_CHAIN_MULTIPLIERS = NB_CHAIN_MULTIPLIERS add_pars[i](add_pars[i]) add_i[i] = StreamingChainMult() if (i != 0 and i <= nb_mult_stages - 1): for j in range(nb_chain_mults_list[i]): k = j * 2 snk0_inst.append( simple_wire_assign(av_snk0_cmb[i][j].valid_i, av_src[i - 1][k].valid_o)) snk0_inst.append( simple_wire_assign(av_snk0_cmb[i][j].data_i, av_src[i - 1][k].data_o)) snk0_inst.append( simple_wire_assign(av_src[i - 1][k].ready_i, av_snk0_cmb[i][j].ready_o)) if (mod_list[i] == 1 and j == (nb_chain_mults_list[i]) - 1): snk1_inst.append( simple_wire_assign(av_snk1_cmb[i][j].valid_i, Signal(1))) snk1_inst.append( simple_wire_assign(av_snk1_cmb[i][j].data_i, Signal(1))) snk1_inst.append( simple_wire_assign(Signal(1), av_snk1_cmb[i][j].ready_o)) else: snk1_inst.append( simple_wire_assign(av_snk1_cmb[i][j].valid_i, av_src[i - 1][k + 1].valid_o)) snk1_inst.append( simple_wire_assign(av_snk1_cmb[i][j].data_i, av_src[i - 1][k + 1].data_o)) snk1_inst.append( simple_wire_assign(av_src[i - 1][k + 1].ready_i, av_snk1_cmb[i][j].ready_o)) elif (i == 0): for k in range(NB_CHAIN_MULTIPLIERS): snk0_valid_inst[k] = simple_wire_assign( av_snk0_cmb[0][k].valid_i, av_src0_bfm[k].valid_o) snk0_data_inst[k] = simple_wire_assign( av_snk0_cmb[0][k].data_i, av_src0_bfm[k].data_o) snk0_ready_inst[k] = simple_wire_assign( av_src0_bfm[k].ready_i, av_snk0_cmb[0][k].ready_o) snk1_valid_inst[k] = simple_wire_assign( av_snk1_cmb[0][k].valid_i, av_src1_bfm[k].valid_o) snk1_data_inst[k] = simple_wire_assign( av_snk1_cmb[0][k].data_i, av_src1_bfm[k].data_o) snk1_ready_inst[k] = simple_wire_assign( av_src1_bfm[k].ready_i, av_snk1_cmb[0][k].ready_o) streaming_chain_mult_inst[i] = add_i[i].block_connect( add_pars[i], reset, clk, av_snk0_cmb[i], av_snk1_cmb[i], av_src[i]) src_valid_inst = simple_wire_assign(av_snk_bfm.valid_i, av_src[nb_mult_stages - 1][0].valid_o) src_data_inst = simple_wire_assign(av_snk_bfm.data_i, av_src[nb_mult_stages - 1][0].data_o) src_ready_inst = simple_wire_assign(av_src[nb_mult_stages - 1][0].ready_i, av_snk_bfm.ready_o) @always(clk.posedge) def stimulus(): if elapsed_time == 40: reset.next = 0 INIT_DATA0 = [ random.randint(1, RANDRANGE) for i in range(NB_CHAIN_MULTIPLIERS) ] INIT_DATA1 = [ random.randint(1, RANDRANGE) for i in range(NB_CHAIN_MULTIPLIERS) ] data_in0 = [Signal(int(0)) for i in range(NB_CHAIN_MULTIPLIERS)] data_in1 = [Signal(int(0)) for i in range(NB_CHAIN_MULTIPLIERS)] src_bfm_0_valid_inst = [] src_bfm_1_valid_inst = [] src_bfm_0_data_inst = [] src_bfm_1_data_inst = [] for i in range(NB_CHAIN_MULTIPLIERS): src_bfm_0_data_inst.append( conditional_wire_assign( src_bfm_0[i].data_i, (av_src0_bfm[i].ready_i and av_src0_bfm[i].valid_o), data_in0[i], src_bfm_0[i].data_i)) src_bfm_1_data_inst.append( conditional_wire_assign( src_bfm_1[i].data_i, (av_src1_bfm[i].ready_i and av_src1_bfm[i].valid_o), data_in1[i], src_bfm_1[i].data_i)) for i in range(NB_CHAIN_MULTIPLIERS): src_bfm_0_valid_inst.append( conditional_wire_assign_lt(src_bfm_0[i].valid_i, nb_transmit0[i], Signal(MAX_NB_TRANSFERS), 1, 0)) src_bfm_1_valid_inst.append( conditional_wire_assign_lt(src_bfm_1[i].valid_i, nb_transmit1[i], Signal(MAX_NB_TRANSFERS), 1, 0)) data_in0_inst = [] data_in1_inst = [] nb_transmit0_inst = [] nb_transmit1_inst = [] transmit_data0_append_inst = [] transmit_data1_append_inst = [] receive_data_append_inst = [] for i in range(NB_CHAIN_MULTIPLIERS): data_in0_inst.append( conditional_random_generator( reset, clk, data_in0[i], int(INIT_DATA0[i]), (av_src0_bfm[i].ready_i and av_src0_bfm[i].valid_o and src_bfm_0[i].valid_i), RANDRANGE)) data_in1_inst.append( conditional_random_generator( reset, clk, data_in1[i], int(INIT_DATA1[i]), (av_src1_bfm[i].ready_i and av_src1_bfm[i].valid_o and src_bfm_1[i].valid_i), RANDRANGE)) nb_transmit0_inst.append( conditional_reg_counter( reset, clk, nb_transmit0[i], Reset.LOW, (av_src0_bfm[i].ready_i and av_src0_bfm[i].valid_o and src_bfm_0[i].valid_i))) nb_transmit1_inst.append( conditional_reg_counter( reset, clk, nb_transmit1[i], Reset.LOW, (av_src1_bfm[i].ready_i and av_src1_bfm[i].valid_o and src_bfm_1[i].valid_i))) transmit_data0_append_inst.append( conditional_clocked_appendfile( reset, clk, (av_src0_bfm[i].ready_i and av_src0_bfm[i].valid_o and src_bfm_0[i].valid_i), data_in0[i], txdata0_filename[i])) transmit_data1_append_inst.append( conditional_clocked_appendfile( reset, clk, (av_src1_bfm[i].ready_i and av_src1_bfm[i].valid_o and src_bfm_1[i].valid_i), data_in1[i], txdata1_filename[i])) receive_data_append_inst.append( conditional_clocked_appendfile(reset, clk, (src_bfm_o.valid_o), src_bfm_o.data_o, rxdata_filename)) recv_inst = None recv_inst = conditional_reg_counter(reset, clk, nb_receive, Reset.LOW, src_bfm_o.valid_o) @always(clk.posedge) def receive_data_process(): TIME_SHUTDOWN = 5000 nb_recv = 0 sim_time_now = now() nb_recv += nb_receive if (nb_recv == (MAX_NB_TRANSFERS)): print("INF242: Num ready pulses: " + str(int(ready_pulses))) raise StopSimulation("Simulation Finished in %d clks: In total " % now() + str(nb_recv) + " data words received") @always(clk.posedge) def simulation_time_check(): sim_time_now = now() if (sim_time_now > MAX_SIM_TIME): raise StopSimulation( "Warning! Simulation Exited upon reaching max simulation time of " + str(MAX_SIM_TIME) + " clocks") ready_pulse_cnt_inst = None ready_pulse_cnt_inst = conditional_reg_counter(reset, clk, ready_pulses, Reset.LOW, (av_snk_bfm.ready_o)) return instances()
def sim_streaming_simple_square(pars_obj): PATTERN_WIDTH = 16 INP_DATA_WIDTH = 8 OP_DATA_WIDTH = INP_DATA_WIDTH + INP_DATA_WIDTH reset = Signal(bool(1)) clk = Signal(bool(0)) elapsed_time = Signal(0) av_src0_bfm = AvalonST_SRC(INP_DATA_WIDTH) av_src1_bfm = AvalonST_SRC(INP_DATA_WIDTH) av_snk0 = AvalonST_SNK(INP_DATA_WIDTH) av_snk1 = AvalonST_SNK(INP_DATA_WIDTH) av_src = AvalonST_SRC(OP_DATA_WIDTH) av_snk_bfm = AvalonST_SNK(OP_DATA_WIDTH) src_bfm_i = AvalonST_SNK(INP_DATA_WIDTH) src_bfm_o = AvalonST_SRC(OP_DATA_WIDTH) clkgen = clk_driver(elapsed_time, clk, period=20) square_pars = StreamingSimpleSquarePars() square_pars.SNK0_DATA_WIDTH = INP_DATA_WIDTH square_pars.SNK1_DATA_WIDTH = INP_DATA_WIDTH square_pars.SRC_DATA_WIDTH = OP_DATA_WIDTH square_pars(square_pars) square_i = StreamingSimpleSquare() src0_bfm_inst = src_bfm(reset, clk, pars_obj.valid.pattern0, src_bfm_i, av_src0_bfm) src1_bfm_inst = src_bfm(reset, clk, pars_obj.valid.pattern1, src_bfm_i, av_src1_bfm) streaming_simple_square_inst = square_i.block_connect( square_pars, reset, clk, av_snk0, av_snk1, av_src) snk_bfm_inst = snk_bfm(reset, clk, pars_obj.ready, av_snk_bfm, src_bfm_o) print("Ready Pattern: ", str(hex(pars_obj.ready))) print("Valid Pattern0: ", str(hex(pars_obj.valid.pattern0))) print("Valid Pattern1: ", str(hex(pars_obj.valid.pattern1))) @always_comb def beh_comb_logic(): # Streaming Input Interface av_snk0.valid_i.next = av_src0_bfm.valid_o av_snk0.data_i.next = av_src0_bfm.data_o av_src0_bfm.ready_i.next = av_snk0.ready_o av_snk1.valid_i.next = av_src1_bfm.valid_o av_snk1.data_i.next = av_src1_bfm.data_o av_src1_bfm.ready_i.next = av_snk1.ready_o #Streaming Output interface av_snk_bfm.valid_i.next = av_src.valid_o av_snk_bfm.data_i.next = av_src.data_o av_src.ready_i.next = av_snk_bfm.ready_o src_bfm_i.valid_i.next = 1 if (nb1 < MAX_NB_TRANSFERS) else 0 @always(clk.posedge) def stimulus(): if elapsed_time == 40: reset.next = 0 INIT_DATA = 1 data_in = Signal(int(0)) @always_comb def transmit_data_process(): if (av_src0_bfm.ready_i == 1 and av_src0_bfm.valid_o == 1): src_bfm_i.data_i.next = data_in #Dataout is just an increment (for next valid data) @always(clk.posedge, reset.posedge) def transmit_data_clk_process(): global trans_data, nb1 if reset == 1: data_in.next = int(INIT_DATA) elif (av_src0_bfm.ready_i == 1 and av_src0_bfm.valid_o == 1 and src_bfm_i.valid_i == 1): nb1 += 1 #print str(nb1) + ". Transmitted data to src bfm:", ": ", src_bfm_i.data_i trans_data.append(int(data_in)) data_in.next = data_in + 1 @always(clk.posedge) def receive_data_process(): global recv_data, nb2 if (src_bfm_o.valid_o == 1): nb2 += 1 #print str(nb2) + ". Received data from sink bfm:", ": ", src_bfm_o.data_o recv_data.append(int(src_bfm_o.data_o)) sim_time_now = now() if (nb2 == MAX_NB_TRANSFERS): raise StopSimulation( "Simulation Finished in %d clks: In total " % now() + str(MAX_NB_TRANSFERS) + " data words received") @always(clk.posedge) def simulation_time_check(): sim_time_now = now() if (sim_time_now > MAX_SIM_TIME): raise StopSimulation( "Warning! Simulation Exited upon reaching max simulation time of " + str(MAX_SIM_TIME) + " clocks") @always(clk.posedge) def cnt_ready_pulses(): global ready_pulses if (av_snk_bfm.ready_o == 1): ready_pulses += 1 #print "ready received from bfm" return instances()
def sim_logistic_regression_2(pars_obj): global test_decimal_shift, theta_decimal_shift # ------------------ Initializing Pipeline depths --------------- NB_PIPELINE_STAGES = 5 DATAWIDTH = 32 # -------------- Simulation Initialisations --------------------- reset = myhdl.Signal(bool(1)) clk = myhdl.Signal(bool(0)) elapsed_time = myhdl.Signal(0) clkgen = clk_driver(elapsed_time, clk, period=20) # ---------------------------------------------------------------- # ----------------- Initializing Pipeline Streams ---------------- # --- Pipeline Pars CHANNEL_WIDTH = 2 FLOAT_INIT_DATA = 0.0 INT_INIT_DATA = 0 global floatDataBus if True == floatDataBus: INIT_DATA = FLOAT_INIT_DATA # requires floating point computation else: INIT_DATA = INT_INIT_DATA # requires myhdl.intbv computation CMD_FILE = "../tests/mult_pipeline.list" moduleLR0 = LogisticRegression(NB_PIPELINE_STAGES, DATAWIDTH, CHANNEL_WIDTH, INIT_DATA, LEN_THETA, CMD_FILE) moduleLR1 = LogisticRegression(NB_PIPELINE_STAGES, DATAWIDTH, CHANNEL_WIDTH, INIT_DATA, LEN_THETA, CMD_FILE) moduleLR2 = LogisticRegression(NB_PIPELINE_STAGES, DATAWIDTH, CHANNEL_WIDTH, INIT_DATA, LEN_THETA, CMD_FILE) moduleLR3 = LogisticRegression(NB_PIPELINE_STAGES, DATAWIDTH, CHANNEL_WIDTH, INIT_DATA, LEN_THETA, CMD_FILE) moduleLR4 = LogisticRegression(NB_PIPELINE_STAGES, DATAWIDTH, CHANNEL_WIDTH, INIT_DATA, LEN_THETA, CMD_FILE) moduleLR5 = LogisticRegression(NB_PIPELINE_STAGES, DATAWIDTH, CHANNEL_WIDTH, INIT_DATA, LEN_THETA, CMD_FILE) moduleLR6 = LogisticRegression(NB_PIPELINE_STAGES, DATAWIDTH, CHANNEL_WIDTH, INIT_DATA, LEN_THETA, CMD_FILE) moduleLR7 = LogisticRegression(NB_PIPELINE_STAGES, DATAWIDTH, CHANNEL_WIDTH, INIT_DATA, LEN_THETA, CMD_FILE) moduleLR8 = LogisticRegression(NB_PIPELINE_STAGES, DATAWIDTH, CHANNEL_WIDTH, INIT_DATA, LEN_THETA, CMD_FILE) moduleLR9 = LogisticRegression(NB_PIPELINE_STAGES, DATAWIDTH, CHANNEL_WIDTH, INIT_DATA, LEN_THETA, CMD_FILE) # --- Initializing Pipeline A pipe_inpA = moduleLR0.pipeST_A_i # --- Initializing Pipeline B pipe_theta0 = moduleLR0.pipeST_B_i pipe_theta1 = moduleLR1.pipeST_B_i pipe_theta2 = moduleLR2.pipeST_B_i pipe_theta3 = moduleLR3.pipeST_B_i pipe_theta4 = moduleLR4.pipeST_B_i pipe_theta5 = moduleLR5.pipeST_B_i pipe_theta6 = moduleLR6.pipeST_B_i pipe_theta7 = moduleLR7.pipeST_B_i pipe_theta8 = moduleLR8.pipeST_B_i pipe_theta9 = moduleLR9.pipeST_B_i # --- Initializing Activation Out pipe_out_activ0 = moduleLR0.pipeST_o pipe_out_activ1 = moduleLR1.pipeST_o pipe_out_activ2 = moduleLR2.pipeST_o pipe_out_activ3 = moduleLR3.pipeST_o pipe_out_activ4 = moduleLR4.pipeST_o pipe_out_activ5 = moduleLR5.pipeST_o pipe_out_activ6 = moduleLR6.pipeST_o pipe_out_activ7 = moduleLR7.pipeST_o pipe_out_activ8 = moduleLR8.pipeST_o pipe_out_activ9 = moduleLR9.pipeST_o # ----------------- Connecting Logistic Regression Block-------------- # Simple Step Activation function inst0 = moduleLR0.top(reset, clk, pipe_inpA, pipe_theta0, pipe_out_activ0) inst1 = moduleLR1.top(reset, clk, pipe_inpA, pipe_theta1, pipe_out_activ1) inst2 = moduleLR2.top(reset, clk, pipe_inpA, pipe_theta2, pipe_out_activ2) inst3 = moduleLR3.top(reset, clk, pipe_inpA, pipe_theta3, pipe_out_activ3) inst4 = moduleLR4.top(reset, clk, pipe_inpA, pipe_theta4, pipe_out_activ4) inst5 = moduleLR5.top(reset, clk, pipe_inpA, pipe_theta5, pipe_out_activ5) inst6 = moduleLR6.top(reset, clk, pipe_inpA, pipe_theta6, pipe_out_activ6) inst7 = moduleLR7.top(reset, clk, pipe_inpA, pipe_theta7, pipe_out_activ7) inst8 = moduleLR8.top(reset, clk, pipe_inpA, pipe_theta8, pipe_out_activ8) inst9 = moduleLR9.top(reset, clk, pipe_inpA, pipe_theta9, pipe_out_activ9) # ---------------------------------------------------------------- # ----------------- Logistic Regression Test File ------------------- lr_test_file = "../../model/ex3data1.mat" lr_theta_file = "../../model/lR_weights.mat" model = LogisticRegression1vsAllModel() imgArray, label, theta, modelPredict = model.get( nbClassifyImages=NB_TRAINING_SAMPLES) # --- Loading Test and Theta Values test_file_list = (imgArray.flatten() ) # Flattenning all the rows for pipelines operation # exp10 shifts done for theta and test data as per requirements when myhdl.intbv used if False == floatDataBus: test_file_list *= 10**test_decimal_shift theta *= 10**theta_decimal_shift test_file_list = test_file_list.astype(int) theta = theta.astype(int) theta_file0_list = [] theta_file1_list = [] theta_file2_list = [] theta_file3_list = [] theta_file4_list = [] theta_file5_list = [] theta_file6_list = [] theta_file7_list = [] theta_file8_list = [] theta_file9_list = [] for i in range(NB_TRAINING_SAMPLES): theta_file0_list.extend(theta[0, :]) theta_file1_list.extend(theta[1, :]) theta_file2_list.extend(theta[2, :]) theta_file3_list.extend(theta[3, :]) theta_file4_list.extend(theta[4, :]) theta_file5_list.extend(theta[5, :]) theta_file6_list.extend(theta[6, :]) theta_file7_list.extend(theta[7, :]) theta_file8_list.extend(theta[8, :]) theta_file9_list.extend(theta[9, :]) # print test_file_list # print theta_file_list # ---------------------------------------------------------------- # ----------------- Shift Enable for pipeData ------------------- shiftEn_i = myhdl.Signal(bool(1)) @myhdl.always(clk.posedge, reset.posedge) def shift_Signal(): if reset: shiftEn_i.next = 1 else: shiftEn_i.next = not shiftEn_i # ---------------------------------------------------------------- # ----------------- Reset For the Module -------------------- @myhdl.always(clk.posedge) def stimulus(): if elapsed_time == 40: reset.next = 0 # ---------------------------------------------------------------- # ----------------- Input Data for the Modules -------------------- @myhdl.always_comb def transmit_data_process(): global line_nb if shiftEn_i == 1 and nbTA == nbTB and nbTA < MAX_NB_TRANSFERS: pipe_inpA.data.next = test_file_list[ line_nb] if floatDataBus == True else int( test_file_list[line_nb]) pipe_inpA.valid.next = 1 pipe_theta0.data.next = theta_file0_list[ line_nb] if floatDataBus == True else int( theta_file0_list[line_nb]) pipe_theta0.valid.next = 1 pipe_theta1.data.next = theta_file1_list[ line_nb] if floatDataBus == True else int( theta_file1_list[line_nb]) pipe_theta1.valid.next = 1 pipe_theta2.data.next = theta_file2_list[ line_nb] if floatDataBus == True else int( theta_file2_list[line_nb]) pipe_theta2.valid.next = 1 pipe_theta3.data.next = theta_file3_list[ line_nb] if floatDataBus == True else int( theta_file3_list[line_nb]) pipe_theta3.valid.next = 1 pipe_theta4.data.next = theta_file4_list[ line_nb] if floatDataBus == True else int( theta_file4_list[line_nb]) pipe_theta4.valid.next = 1 pipe_theta5.data.next = theta_file5_list[ line_nb] if floatDataBus == True else int( theta_file5_list[line_nb]) pipe_theta5.valid.next = 1 pipe_theta6.data.next = theta_file6_list[ line_nb] if floatDataBus == True else int( theta_file6_list[line_nb]) pipe_theta6.valid.next = 1 pipe_theta7.data.next = theta_file7_list[ line_nb] if floatDataBus == True else int( theta_file7_list[line_nb]) pipe_theta7.valid.next = 1 pipe_theta8.data.next = theta_file8_list[ line_nb] if floatDataBus == True else int( theta_file8_list[line_nb]) pipe_theta8.valid.next = 1 pipe_theta9.data.next = theta_file9_list[ line_nb] if floatDataBus == True else int( theta_file9_list[line_nb]) pipe_theta9.valid.next = 1 line_nb += 1 else: pipe_inpA.valid.next = 0 pipe_theta0.valid.next = 0 pipe_theta1.valid.next = 0 pipe_theta2.valid.next = 0 pipe_theta3.valid.next = 0 pipe_theta4.valid.next = 0 pipe_theta5.valid.next = 0 pipe_theta6.valid.next = 0 pipe_theta7.valid.next = 0 pipe_theta8.valid.next = 0 pipe_theta9.valid.next = 0 # ---------------------------------------------------------------- # ----------------- Storing Transmitted Data -------------------- @myhdl.always(clk.posedge, reset.posedge) def trans_dataA_process(): global trans_dataA, trans_dataB, nbTA if reset == 1: pass elif pipe_inpA.valid == 1 and nbTA < MAX_NB_TRANSFERS: nbTA += 1 trans_dataA.extend([pipe_inpA.data]) @myhdl.always(clk.posedge, reset.posedge) def trans_dataB_process(): global trans_dataA, trans_dataB, nbTB if reset == 1: pass elif pipe_theta0.valid == 1 and nbTB < MAX_NB_TRANSFERS: nbTB += 1 trans_dataB.extend([pipe_theta0.data]) # ---------------------------------------------------------------- # ----------------- Storing Received Data ----------------------- @myhdl.always(clk.posedge) def receive_data_process(): global recv_data, tap_data_mmult, nbR, acc_out, prediction_res ## Collecting multiplier data # if (moduleLR0.pipe_multRes.valid == 1): # if (False == floatDataBus): # pipe_multRes= moduleLR0.pipe_multRes.data # else: # pipe_multRes= (round(float(moduleLR0.pipe_multRes.data),DEF_ROUND)) # tap_mult.extend([pipe_multRes]) displayAccOut(nbR, moduleLR0.pipe_out_acc, 0) displayAccOut(nbR, moduleLR1.pipe_out_acc, 1) displayAccOut(nbR, moduleLR2.pipe_out_acc, 2) displayAccOut(nbR, moduleLR3.pipe_out_acc, 3) displayAccOut(nbR, moduleLR4.pipe_out_acc, 4) displayAccOut(nbR, moduleLR5.pipe_out_acc, 5) displayAccOut(nbR, moduleLR6.pipe_out_acc, 6) displayAccOut(nbR, moduleLR7.pipe_out_acc, 7) displayAccOut(nbR, moduleLR8.pipe_out_acc, 8) displayAccOut(nbR, moduleLR9.pipe_out_acc, 9) if moduleLR9.pipe_out_acc.valid == 1: nbR += 1 if nbR == NB_TRAINING_SAMPLES: prediction_res = ( np.argmax(resY, axis=1) + 1 ) # +1 to correct indexing due to speciality of the example. See docs ex3.pdf for i in range(len(prediction_res)): prediction_res[i] = (0 if prediction_res[i] == 10 else prediction_res[i]) print("label: {} prediction: {}".format(label, prediction_res)) raise myhdl.StopSimulation( "Simulation Finished in %d clks: In total " % myhdl.now() + str(MAX_NB_TRANSFERS) + " data words transfered") # ---------------------------------------------------------------- # ----------------- Max Simulation Time Exit Condition ----------- @myhdl.always(clk.posedge) def simulation_time_check(): sim_time_now = myhdl.now() if sim_time_now > MAX_SIM_TIME: raise myhdl.StopSimulation( "Warning! Simulation Exited upon reaching max simulation time of " + str(MAX_SIM_TIME) + " clocks") # ---------------------------------------------------------------- return myhdl.instances()
def sim_logistic_regression(pars_obj): global test_decimal_shift, theta_decimal_shift #------------------ Initializing Pipeline depths --------------- NB_PIPELINE_STAGES = 5 DATAWIDTH = 32 #-------------- Simulation Initialisations --------------------- reset = Signal(bool(1)) clk = Signal(bool(0)) elapsed_time = Signal(0) clkgen = clk_driver(elapsed_time, clk, period=20) #---------------------------------------------------------------- #----------------- Initializing Pipeline Streams ---------------- # --- Pipeline Pars pars.CHANNEL_WIDTH = 2 global floatDataBus if (True == floatDataBus): pars.INIT_DATA = 0.0 # requires floating point computation else: pars.INIT_DATA = 0 # requires intbv computation pars.CMD_FILE = '../tests/mult_pipeline.list' pars.LEN_THETA = LEN_THETA moduleLR = LogisticRegression(NB_PIPELINE_STAGES, DATAWIDTH, CHANNEL_WIDTH, INIT_DATA, LEN_THETA, CMD_FILE) ioLR = moduleLR0.Io # --- Initializing Pipeline A pipe_inpA = ioLR.pipe_inpA # --- Initializing Pipeline B pipe_inpB = ioLR.pipe_inpB # --- Initializing Activation Out pipe_out_activ = ioLR.pipe_out_activ inst = [] #----------------- Connecting Logistic Regression Block-------------- # Simple Step Activation function inst.append( moduleLR.block_connect(pars, reset, clk, pipe_inpA, pipe_inpB, pipe_out_activ)) #---------------------------------------------------------------- #----------------- Logistic Regression Test File ------------------- lr_test_file = "../tests/ex2data1.txt" lr_theta_file = "../tests/theta1.txt" #--- Loading Test and Theta Values test_file_list = [] theta_file_list = [] nb_training_examples = 0 # Loading test data with open(lr_test_file, 'r') as f: d0 = 1.0 # Always first element is 1 for line in f: #print line d1, d2, y = line.split(',') d0 = round(float(d0), DEF_ROUND) d1 = round(float(d1), DEF_ROUND) d2 = round(float(d2), DEF_ROUND) test_file_list.extend([d0, d1, d2]) label.extend([int(y)]) nb_training_examples += 1 #loading theta with open(lr_theta_file, 'r') as f: t0, t1, t2 = (f.read().split('\n')[0]).split(',') t0 = round(float(t0), DEF_ROUND) t1 = round(float(t1), DEF_ROUND) t2 = round(float(t2), DEF_ROUND) for i in range(nb_training_examples): theta_file_list.extend([t0, t1, t2]) # exp10 shifts done for theta and test data as per requirements when intbv used if (False == floatDataBus): test_file_list = [ int(i * (10**test_decimal_shift)) for i in test_file_list ] theta_file_list = [ int(i * (10**theta_decimal_shift)) for i in theta_file_list ] #print test_file_list #print theta_file_list #---------------------------------------------------------------- #----------------- Shift Enable for pipeData ------------------- shiftEn_i = Signal(bool(1)) @always(clk.posedge, reset.posedge) def shift_signal(): if reset: shiftEn_i.next = 1 else: shiftEn_i.next = not shiftEn_i #---------------------------------------------------------------- #----------------- Reset For the Module -------------------- @always(clk.posedge) def stimulus(): if elapsed_time == 40: reset.next = 0 #---------------------------------------------------------------- #----------------- Input Data for the Modules -------------------- @always_comb def transmit_data_process(): global line_nb if (shiftEn_i == 1 and nbTA == nbTB and nbTA < MAX_NB_TRANSFERS): pipe_inpA.data.next = (test_file_list[line_nb]) pipe_inpA.valid.next = 1 pipe_inpB.data.next = (theta_file_list[line_nb]) pipe_inpB.valid.next = 1 line_nb += 1 else: pipe_inpA.valid.next = 0 pipe_inpB.valid.next = 0 #---------------------------------------------------------------- #----------------- Storing Transmitted Data -------------------- @always(clk.posedge, reset.posedge) def trans_dataA_process(): global trans_dataA, trans_dataB, nbTA if reset == 1: pass elif (pipe_inpA.valid == 1 and nbTA < MAX_NB_TRANSFERS): nbTA += 1 trans_dataA.extend([pipe_inpA.data]) @always(clk.posedge, reset.posedge) def trans_dataB_process(): global trans_dataA, trans_dataB, nbTB if reset == 1: pass elif (pipe_inpB.valid == 1 and nbTB < MAX_NB_TRANSFERS): nbTB += 1 trans_dataB.extend([pipe_inpB.data]) #---------------------------------------------------------------- #----------------- Storing Received Data ----------------------- @always(clk.posedge) def receive_data_process(): global recv_data, tap_data_mmult, nbR, acc_out # Collecting multiplier data if (moduleLR.mult_out.valid == 1): if (False == floatDataBus): mult_out = moduleLR.mult_out.data else: mult_out = (round(float(moduleLR.mult_out.data), DEF_ROUND)) tap_mult.extend([mult_out]) # Collecting Accumulator Data if (moduleLR.accu_out.valid == 1): acc_out = moduleLR.accu_out.data #prob=(1.0/(1+ (math.exp(-1.0*acc_out) ))) # Sigmoid activation Function if __debug__: if (False == floatDataBus): print("{0:d} acc_out: {1:d} ".format(int(nbR / LEN_THETA + 1), int(acc_out), i=DEF_ROUND)) else: print("{0:d} acc_out: {1:0.{i}f}".format( int(nbR / LEN_THETA + 1), float(acc_out), i=DEF_ROUND)) if (False == floatDataBus): tap_accu.extend([int(acc_out)]) else: tap_accu.extend([round(float(acc_out), DEF_ROUND)]) # Collecting Activation Data if (pipe_out_activ.valid == 1): nbR += LEN_THETA predict = int(pipe_out_activ.data) recv_data.extend([predict]) fp = open("predict_op.log", 'a') fp.write("{:d}\n".format(predict)) fp.close() if __debug__: print("Prediction: {:d}".format(predict)) if (nbR == MAX_NB_TRANSFERS): raise StopSimulation( "Simulation Finished in %d clks: In total " % now() + str(MAX_NB_TRANSFERS) + " data words transfered") #---------------------------------------------------------------- #----------------- Max Simulation Time Exit Condition ----------- @always(clk.posedge) def simulation_time_check(): sim_time_now = now() if (sim_time_now > MAX_SIM_TIME): raise StopSimulation( "Warning! Simulation Exited upon reaching max simulation time of " + str(MAX_SIM_TIME) + " clocks") #---------------------------------------------------------------- return instances()