def setup_interfaces(self):
"""
Setup the DUT interfaces.
"""
# coefficients interface
self.coefficients_in_clk_gen = cocotb.fork(
Clock(self.dut.coefficients_in_aclk, self.CLK_PERIOD).start())
self.axism_coeffs_in = AXI4StreamMaster(self.dut, "coefficients_in",
self.dut.coefficients_in_aclk)
# input data interface
self.data_in_clk_gen = cocotb.fork(
Clock(self.dut.data_in_aclk, self.CLK_PERIOD).start())
self.axism_data_in = AXI4StreamMaster(self.dut, "data_in",
self.dut.data_in_aclk)
# output data interface
self.data_out_clk_gen = cocotb.fork(
Clock(self.dut.data_out_aclk, self.CLK_PERIOD).start())
self.axiss_data_out = AXI4StreamSlave(self.dut, "data_out",
self.dut.data_out_aclk)
# use the input data clock
self.data_in_clk_rising = yield RisingEdge(self.dut.data_out_aclk)
yield Timer(0)
async def setup_interfaces(self):
"""
Setup the DUT interfaces.
"""
# coefficients interface
if self.COEFF_STREAM:
self.coefficients_in_clk_gen = cocotb.fork(
Clock(self.dut.coefficients_in_aclk, self.CLK_PERIOD).start())
self.axism_coeffs_in = AXI4StreamMaster(
self.dut, "coefficients_in", self.dut.coefficients_in_aclk)
else:
self.coeffs_clk_gen = cocotb.fork(
Clock(self.dut.coeffs_axi_aclk, self.CLK_PERIOD).start())
self.axim_coeffs_in = AxiLiteMaster(self.dut, "coeffs_axi",
self.dut.coeffs_axi_aclk)
# input data interface
self.data_in_clk_gen = cocotb.fork(
Clock(self.dut.data_in_aclk, self.CLK_PERIOD).start())
self.axism_data_in = AXI4StreamMaster(self.dut, "data_in",
self.dut.data_in_aclk)
# output data interface
self.data_out_clk_gen = cocotb.fork(
Clock(self.dut.data_out_aclk, self.CLK_PERIOD).start())
self.axiss_data_out = AXI4StreamSlave(self.dut, "data_out",
self.dut.data_out_aclk)
# use the input data clock
self.data_in_clk_rising = await RisingEdge(self.dut.data_out_aclk)
await Timer(0)
def first_test(dut):
"""
Description:
Very Basic Functionality
Startup Nysa
Test ID: 0
Expected Results:
Write to all registers
"""
dut.rst <= 1
axim = AXI4StreamMaster(dut, "AXIMS", dut.clk)
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
yield Timer(CLK_PERIOD * 10)
dut.log.info("Write 2 32-bits of data")
data = [0x00000000, 0x00000001]
yield axim.write(data)
yield Timer(CLK_PERIOD * 100)
dut.log.info("Done")
def __init__(self, dut, debug=False):
self.dut = dut
self.csrBase = 0x79040000
self.stream_in = STDriver(dut,
"adc_0",
dut.clock,
big_endian=False,
**stream_names)
self.csr = MemMaster(dut, "s_axi", dut.s_axi_aclk, **lower_axil)
self.memory = np.arange(1024 * 1024 * 1024, dtype=np.dtype('b'))
self.mem = MemSlave(dut,
"m_axi",
dut.s_axi_aclk,
memory=self.memory,
**lower_axi)
# self.stream_in_recovered = STMonitor(dut, "adc_0", dut.clock, **stream_names)
self.stream_out = STMonitor(
dut, "dac_0", dut.clock,
**stream_names) #, callback = self.append_channel)
self.expected_output = []
self.txdata = []
self.write_monitor = WriteMonitor(dut, "m_axi", dut.s_axi_aclk,
**lower_axi)
eq_block = dut.sAxiIsland.freqRx.freqRx.eq
# self.eq_monitor_in = DecoupledMonitor(eq_block, "in", eq_block.clock, reset=eq_block.reset)
fft_block = dut.sAxiIsland.freqRx.freqRx.fft
# self.fft_mon = FFTMonitor(fft_block, fft_block.clock)
self.scoreboard = Scoreboard(dut)
# self.scoreboard.add_interface(self.stream_out, self.expected_output)
# self.scoreboard.add_interface(self.write_monitor, self.txdata)
level = logging.DEBUG if debug else logging.WARNING
self.stream_in.log.setLevel(level)
self.csr.log.setLevel(level)
self.mem.log.setLevel(level)
# self.stream_in_recovered.log.setLevel(level)
self.channel_model = SISOChannel()
def read_all_registers(dut):
"""
Description:
Read all registers from the core
Test ID: 0
Expected Results:
A value is successfully written to the
the register of the controller.
This value should be readable from the test bench
"""
dut.rst <= 1
dut.test_id <= 0
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
video_out = AXI4StreamMaster(dut, "AXIMS", dut.clk, width=24)
video_in = AXI4StreamSlave(dut, "AXISS", dut.clk, width=24)
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
yield Timer(CLK_PERIOD * 10)
dut.rst <= 1
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
yield Timer(CLK_PERIOD * 10)
dut.log.info("Ready")
control = 0x02
#Reset the LCD
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
control = 0x01
#Reset the LCD
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
yield Timer(CLK_PERIOD * 100)
#Read Back All the registers, make sure they make sense
data = yield axim.read(REG_STATUS)
yield Timer(CLK_PERIOD * 10)
if data != control:
raise TestFailure(
"REG_STATUS Register was not correct, should be: 0x%08 but read: 0x%08X"
% control, data)
data = yield axim.read(REG_VIDEO_IN_SIZE)
yield Timer(CLK_PERIOD * 10)
if data != (1280 * 720):
raise TestFailure(
"REG_VIDEO_IN_SIZE Register was not correct, should be: 0x%08 but read: 0x%08X"
% ((1280 * 720), data))
data = yield axim.read(REG_VIDEO_IN_WIDTH)
yield Timer(CLK_PERIOD * 10)
if data != 1280:
raise TestFailure(
"REG_VIDEO_IN_WIDTH Register was not correct, should be: 0x%08 but read: 0x%08X"
% (1280, data))
data = yield axim.read(REG_VIDEO_IN_HEIGHT)
yield Timer(CLK_PERIOD * 10)
if data != 720:
raise TestFailure(
"REG_VIDEO_IN_HEIGHT Register was not correct, should be: 0x%08 but read: 0x%08X"
% (720, data))
data = yield axim.read(REG_VIDEO_OUT_SIZE)
yield Timer(CLK_PERIOD * 10)
if data != (1280 * 720):
raise TestFailure(
"REG_VIDEO_OUT_SIZE Register was not correct, should be: 0x%08 but read: 0x%08X"
% ((1280 * 720), data))
data = yield axim.read(REG_VIDEO_OUT_WIDTH)
yield Timer(CLK_PERIOD * 10)
if data != 1280:
raise TestFailure(
"REG_VIDEO_OUT_WIDTH Register was not correct, should be: 0x%08 but read: 0x%08X"
% (1280, data))
data = yield axim.read(REG_VIDEO_OUT_HEIGHT)
yield Timer(CLK_PERIOD * 10)
if data != 720:
raise TestFailure(
"REG_VIDEO_OUT_HEIGHT Register was not correct, should be: 0x%08 but read: 0x%08X"
% (720, data))
data = yield axim.read(REG_VIDEO_IN_START_X)
yield Timer(CLK_PERIOD * 10)
if data != 0:
raise TestFailure(
"REG_VIDEO_IN_START_X Register was not correct, should be: 0x%08 but read: 0x%08X"
% (0, data))
data = yield axim.read(REG_VIDEO_IN_START_Y)
yield Timer(CLK_PERIOD * 10)
if data != 0:
raise TestFailure(
"REG_VIDEO_IN_START_Y Register was not correct, should be: 0x%08 but read: 0x%08X"
% (0, data))
data = yield axim.read(REG_IN_FILL_PIXEL)
yield Timer(CLK_PERIOD * 10)
if data != 0:
raise TestFailure(
"REG_IN_FILL_PIXEL Register was not correct, should be: 0x%08 but read: 0x%08X"
% (0, data))
def write_center_frame(dut):
"""
Description:
Write a single frame
Test ID: 4
Expected Results:
A value is successfully written to the
the register of the controller.
This value should be readable from the test bench
"""
dut.test_id <= 4
IMAGE_IN_WIDTH = 4
IMAGE_IN_HEIGHT = 4
IMAGE_IN_SIZE = IMAGE_IN_WIDTH * IMAGE_IN_HEIGHT
IMAGE_OUT_WIDTH = 2
IMAGE_OUT_HEIGHT = 2
IMAGE_OUT_SIZE = IMAGE_OUT_WIDTH * IMAGE_OUT_HEIGHT
IMAGE_IN_START_X = 1
IMAGE_IN_START_Y = 1
video = []
for y in range(IMAGE_IN_HEIGHT):
for x in range(IMAGE_IN_WIDTH):
video.append((IMAGE_IN_WIDTH * y) + x)
dut.rst <= 1
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
video_out = AXI4StreamMaster(dut, "AXIMS", dut.clk, width=24)
video_in = AXI4StreamSlave(dut, "AXISS", dut.clk, width=24)
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
yield Timer(CLK_PERIOD * 10)
dut.rst <= 1
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
yield Timer(CLK_PERIOD * 10)
dut.log.info("Ready")
cocotb.fork(axis_slave_listener(video_in))
control = 0x02
#Reset the LCD
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_VIDEO_IN_WIDTH, IMAGE_IN_WIDTH)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_VIDEO_IN_HEIGHT, IMAGE_IN_HEIGHT)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_VIDEO_IN_SIZE, IMAGE_IN_SIZE)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_VIDEO_OUT_WIDTH, IMAGE_OUT_WIDTH)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_VIDEO_OUT_HEIGHT, IMAGE_OUT_HEIGHT)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_VIDEO_OUT_SIZE, IMAGE_OUT_SIZE)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_VIDEO_IN_START_X, IMAGE_IN_START_X)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_VIDEO_IN_START_Y, IMAGE_IN_START_Y)
yield Timer(CLK_PERIOD * 10)
control = 0x01
#Reset the LCD
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
yield video_out.write(video)
yield Timer(CLK_PERIOD * 500)
class BasebandTB(object):
def __init__(self, dut, debug=False):
self.dut = dut
self.csrBase = 0x79040000
self.stream_in = STDriver(dut,
"adc_0",
dut.clock,
big_endian=False,
**stream_names)
self.csr = MemMaster(dut, "s_axi", dut.s_axi_aclk, **lower_axil)
self.memory = np.arange(1024 * 1024 * 1024, dtype=np.dtype('b'))
self.mem = MemSlave(dut,
"m_axi",
dut.s_axi_aclk,
memory=self.memory,
**lower_axi)
# self.stream_in_recovered = STMonitor(dut, "adc_0", dut.clock, **stream_names)
self.stream_out = STMonitor(
dut, "dac_0", dut.clock,
**stream_names) #, callback = self.append_channel)
self.expected_output = []
self.txdata = []
self.write_monitor = WriteMonitor(dut, "m_axi", dut.s_axi_aclk,
**lower_axi)
eq_block = dut.sAxiIsland.freqRx.freqRx.eq
# self.eq_monitor_in = DecoupledMonitor(eq_block, "in", eq_block.clock, reset=eq_block.reset)
fft_block = dut.sAxiIsland.freqRx.freqRx.fft
# self.fft_mon = FFTMonitor(fft_block, fft_block.clock)
self.scoreboard = Scoreboard(dut)
# self.scoreboard.add_interface(self.stream_out, self.expected_output)
# self.scoreboard.add_interface(self.write_monitor, self.txdata)
level = logging.DEBUG if debug else logging.WARNING
self.stream_in.log.setLevel(level)
self.csr.log.setLevel(level)
self.mem.log.setLevel(level)
# self.stream_in_recovered.log.setLevel(level)
self.channel_model = SISOChannel()
@cocotb.coroutine
def append_channel(self):
yield ReadOnly()
while True:
if self.dut.dac_0_valid.value:
data = self.dut.dac_0_data.value.get_value()
else:
data = 0
# print("append_channel")
self.channel_model.push_packed_sample(data)
yield RisingEdge(self.dut.clock)
yield ReadOnly()
@cocotb.coroutine
def get_channel(self):
dataword = BinaryValue(n_bits=32)
# self.stream_in.bus.TVALID <= 1
while True:
# print("get_channel")
# dataword.assign(str(self.channel_model.pop_packed_sample()))
# self.stream_in.bus.TDATA <= dataword
data = self.channel_model.pop_packed_sample()
yield self.stream_in._driver_send(data=data, sync=False)
# yield RisingEdge(self.dut.clock)
@cocotb.coroutine
def dma_to_mm(self, *, base=0, size=None):
if size is None:
size = len(self.memory) // 4
# base
yield self.csr.write(self.csrBase + 4 * 4, base)
# length
yield self.csr.write(self.csrBase + 5 * 4, size - 1)
# cycles
yield self.csr.write(self.csrBase + 6 * 4, 0)
# fixed
yield self.csr.write(self.csrBase + 7 * 4, 0)
# go
yield self.csr.write(self.csrBase + 8 * 4, 1)
while True:
bytesLeft = yield self.csr.read(self.csrBase + 8 * 4)
if not bytesLeft:
break
@cocotb.coroutine
def dma_mm_to_dac(self, *, base=0, size=None):
if size is None:
size = len(self.memory) // 4
# enable Tx / disable DMA passthrough
yield self.csr.write(0x79040A00 + 0 * 4, 1)
# base
yield self.csr.write(self.csrBase + 0x9 * 4, base)
# length
yield self.csr.write(self.csrBase + 0xA * 4, size - 1)
# cycles
yield self.csr.write(self.csrBase + 0xB * 4, 100)
# fixed
yield self.csr.write(self.csrBase + 0xC * 4, 0)
# skid disable
yield self.csr.write(self.csrBase + 0x200, 0)
# skid drain upstream queue
yield self.csr.write(self.csrBase + 0x200 + 0x5 * 4, 1)
# skid clear overflow register
yield self.csr.write(self.csrBase + 0x200 + 0x3 * 4, 0)
# go
yield self.csr.write(self.csrBase + 0xD * 4, 0)
# enable
yield self.csr.write(self.csrBase + 0x0, 1)
# skid enable
yield self.csr.write(self.csrBase + 0x200, 1)
# wait for end
while True:
yield ClockCycles(self.dut.s_axi_aclk, 50)
out = yield self.csr.read(self.csrBase + 0xD * 4)
if out == 0:
break
print("Done with TX")
@cocotb.coroutine
def set_aligner(self, base=0x100, *, en=True, cnt=1, cntPassthrough=False):
if cntPassthrough:
cntPassthrough = 1
else:
cntPassthrough = 0
if en:
en = 1
else:
en = 0
if base < 0x70000000:
base = base + self.csrBase
yield self.csr.write(base + 0xC, cnt)
yield self.csr.write(base + 0x10, cntPassthrough)
yield self.csr.write(base, 1)
@cocotb.coroutine
def set_input_splitter_mux(self, base=0x900):
if base < 0x70000000:
base = base + self.csrBase
yield self.csr.write(base, 0)
@cocotb.coroutine
def set_input_stream_mux(self, base=0x300):
if base < 0x70000000:
base = base + self.csrBase
yield self.csr.write(base, 0)
# yield self.csr.write(base + 4, 0)
@cocotb.coroutine
def set_schedule(self, base=0x800, *, length, time):
if base < 0x70000000:
base = base + self.csrBase
yield self.csr.write(base, length)
yield self.csr.write(base + 0x4, time)
yield self.csr.write(base + 0xC, 1) # go!
@cocotb.coroutine
def set_timerx(self, base=0x400, **kwargs):
if base < 0x70000000:
base = base + self.csrBase
settings = {
'autocorrFF': 0.9,
'peakThreshold': 0.05,
'peakOffset': 0.0,
'freqMultiplier': 0.0,
'autocorrDepthApart': 65,
'autocorrDepthOverlap': 63,
'peakDetectNumPeaks': 16,
'peakDetectPeakDistance': 32,
'packetLength': 222 + 7,
'samplesToDrop': 0,
'inputDelay': 74,
}
representations = {
'autocorrFF': FixedPointRepresentation(bp=17),
'peakThreshold': FixedPointRepresentation(bp=17),
'peakOffset': FixedPointRepresentation(bp=17),
'freqMultiplier': FixedPointRepresentation(bp=17),
'autocorrDepthApart': IntRepresentation(),
'autocorrDepthOverlap': IntRepresentation(),
'peakDetectNumPeaks': IntRepresentation(),
'peakDetectPeakDistance': IntRepresentation(),
'packetLength': IntRepresentation(),
'samplesToDrop': IntRepresentation(),
'inputDelay': IntRepresentation()
}
settings = {**settings, **kwargs}
for key in settings.keys():
kwargs.pop(key, None)
if len(kwargs) != 0:
raise TypeError(f"Unexpected kwargs {kwargs}")
for idx, (key, val) in enumerate(settings.items()):
# print(f"Writing {representations[key](val)} ({val}) to {base + idx * 4}")
yield self.csr.write(base + idx * 4, representations[key](val))
# write globalCycleEn
yield self.csr.write(base + len(settings) * 4, 1)
@cocotb.coroutine
def transmit(self, data):
txdata = encode_tx(data, addPreamble=True)
# txdata = encode_linear_seq(222)
self.txdata.extend(data)
for i in range(len(txdata)):
self.memory[i] = txdata[i]
yield self.dma_mm_to_dac(base=0, size=len(txdata) // 4 - 1)
# self.dma_to_mm(base = 0 * 1024 * 4, size = len(txdata))
@cocotb.coroutine
def transmit_forever(self, data, wait_cycles=100):
txdata = encode_tx(data, addPreamble=True)
# txdata = encode_linear_seq(222)
self.txdata.extend(data)
for i in range(len(txdata)):
self.memory[i] = txdata[i]
while True:
yield ClockCycles(self.dut.clock, wait_cycles)
yield self.dma_mm_to_dac(base=0, size=len(txdata) // 4 - 1)
@cocotb.coroutine
def handle_packet_detect(self, *, base=0x400):
if base < 0x70000000:
base = base + self.csrBase
while True:
# check if an interrupt has fired
if not self.dut.skid_ints_0.value:
# if not, wait for one
yield RisingEdge(self.dut.skid_ints_0)
time = yield self.csr.read(base + 13 * 4)
print(f"Saw packet at time {time.signed_integer}")
@cocotb.coroutine
def reset(self, duration=5):
self.dut._log.debug("Resetting DUT")
self.dut.reset <= 1
self.dut.s_axi_aresetn <= 0
self.stream_in.bus.TVALID <= 0
yield ClockCycles(self.dut.clock, duration)
self.dut.reset <= 0
yield RisingEdge(self.dut.s_axi_aclk)
self.dut.s_axi_aresetn <= 1
self.dut.s_axi_awprot <= 0
self.dut.dac_0_ready <= 1
self.dut.dac_1_ready <= 1
self.dut._log.debug("Setting registers to drain input streams")
yield self.csr.write(self.csrBase + 0x200 + 0x5 * 4, 1)
yield self.csr.write(self.csrBase + 0x200, 0)
yield self.csr.write(self.csrBase + 0x100, 0)
self.dut._log.debug("Out of reset")
def write_to_controller(dut):
"""
Description:
Write a 16-bit valute to the controller
Test ID: 0
Expected Results:
A value is successfully written to the
the register of the controller.
This value should be readable from the test bench
"""
dut.rst <= 1
dut.i_fsync <= 1
dut.test_id <= 0
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
video_out = AXI4StreamMaster(dut, "AXIMS", dut.clk, width=24)
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
dut.log.info("Ready")
yield Timer(CLK_PERIOD * 10)
dut.rst <= 1
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
dut.log.info("Ready")
yield Timer(CLK_PERIOD * 10)
control = 0x00
control |= 1 << BIT_CONTROL_CHIP_SELECT
control |= 1 << BIT_CONTROL_RESET_DISPLAY
control |= 1 << BIT_CONTROL_ENABLE
control |= 1 << BIT_CONTROL_BACKLIGHT_ENABLE
control |= 1 << BIT_CONTROL_WRITE_OVERRIDE
#Reset the LCD
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
control &= ~(1 << BIT_CONTROL_RESET_DISPLAY)
control &= ~(1 << BIT_CONTROL_WRITE_OVERRIDE)
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
control &= ~(1 << BIT_CONTROL_CHIP_SELECT)
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
control |= 1 << BIT_CONTROL_CHIP_SELECT
##################################################
#Write a 0xAA55 to address 0xB8
#First set up the correct mode
control |= 1 << BIT_CONTROL_COMMAND_MODE
control &= ~ (1 << BIT_CONTROL_COMMAND_PARAMETER)
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
#Set The Address to write to
WRITE_ADDR = 0xB8
yield axim.write(REG_COMMAND_DATA, WRITE_ADDR)
yield Timer(CLK_PERIOD * 10)
#Write the command
control |= 1 << BIT_CONTROL_COMMAND_WRITE
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
#Write a parameter
WRITE_PARAMETER_1 = 0xAA # Arbitrary Data
WRITE_PARAMETER_2 = 0x55 # Arbitrary Data
# Write Parameter 1
yield axim.write(REG_COMMAND_DATA, WRITE_PARAMETER_1)
yield Timer(CLK_PERIOD * 10)
control |= 1 << BIT_CONTROL_COMMAND_PARAMETER
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
# Write Parameter 2
yield axim.write(REG_COMMAND_DATA, WRITE_PARAMETER_2)
yield Timer(CLK_PERIOD * 10)
control |= 1 << BIT_CONTROL_COMMAND_PARAMETER
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
#yield FallingEdge(dut.w_write_n)
#yield ReadOnly()
data = dut.r_write_parameter
value = (WRITE_PARAMETER_1 << 8) | WRITE_PARAMETER_2
if data != value:
raise TestFailure("Data written to register should have been: 0x02X, \
but is 0x%02X" % (data, value))
yield Timer(CLK_PERIOD * 100)
def first_test(dut):
"""
Description:
Very Basic Functionality
Startup Nysa
Test ID: 0
Expected Results:
Write to all registers
"""
WIDTH = 8
HEIGHT = 4
H_BLANK = 40
V_BLANK = 200
NUM_FRAMES = 2
video = []
for v in range (HEIGHT):
for h in range(WIDTH):
value = h << 16
value |= h << 8
value |= h
video.append(value)
dut.rst <= 1
dut.i_fsync <= 1
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
video_out = AXI4StreamMaster(dut, "AXIMS", dut.clk, width=24)
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
dut.log.info("Ready")
yield Timer(CLK_PERIOD * 10)
control = 0x00
control |= 1 << BIT_CONTROL_CHIP_SELECT
control |= 1 << BIT_CONTROL_RESET_DISPLAY
control |= 1 << BIT_CONTROL_ENABLE
control |= 1 << BIT_CONTROL_BACKLIGHT_ENABLE
control |= 1 << BIT_CONTROL_WRITE_OVERRIDE
#Reset the LCD
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
control &= ~(1 << BIT_CONTROL_RESET_DISPLAY)
control &= ~(1 << BIT_CONTROL_WRITE_OVERRIDE)
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
control &= ~(1 << BIT_CONTROL_CHIP_SELECT)
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
control |= 1 << BIT_CONTROL_CHIP_SELECT
##################################################
#Write a 0xAA55 to address 0xB8
#First set up the correct mode
control |= 1 << BIT_CONTROL_COMMAND_MODE
control &= ~ (1 << BIT_CONTROL_COMMAND_PARAMETER)
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
#Set The Address to write to
WRITE_ADDR = 0xB8
yield axim.write(REG_COMMAND_DATA, WRITE_ADDR)
yield Timer(CLK_PERIOD * 10)
#Write the command
control |= 1 << BIT_CONTROL_COMMAND_WRITE
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
#Write a parameter
WRITE_PARAMETER_1 = 0xAA # Arbitrary Address
WRITE_PARAMETER_2 = 0x55
# Write Parameter 1
yield axim.write(REG_COMMAND_DATA, WRITE_PARAMETER_1)
yield Timer(CLK_PERIOD * 10)
control |= 1 << BIT_CONTROL_COMMAND_PARAMETER
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
# Write Parameter 2
yield axim.write(REG_COMMAND_DATA, WRITE_PARAMETER_2)
yield Timer(CLK_PERIOD * 10)
control &= ~(1 << BIT_CONTROL_COMMAND_MODE)
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
##################################################
#Read two bytes from address 0xB8
# Set the address
READ_ADDR = 0xB8
control |= 1 << BIT_CONTROL_COMMAND_MODE
control &= ~ (1 << BIT_CONTROL_COMMAND_PARAMETER)
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
# Set address
yield axim.write(REG_COMMAND_DATA, READ_ADDR)
yield Timer(CLK_PERIOD * 10)
control |= 1 << BIT_CONTROL_COMMAND_WRITE
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
control &= ~(1 << BIT_CONTROL_COMMAND_WRITE)
control |= 1 << BIT_CONTROL_COMMAND_PARAMETER
control |= 1 << BIT_CONTROL_COMMAND_READ
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
data = yield axim.read(REG_COMMAND_DATA)
yield Timer(CLK_PERIOD * 10)
print "First Byte: 0x%02X" % data
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
data = yield axim.read(REG_COMMAND_DATA)
yield Timer(CLK_PERIOD * 10)
print "Second Byte: 0x%02X" % data
#Set the pixel count
yield axim.write(REG_IMAGE_WIDTH, WIDTH)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_IMAGE_HEIGHT, HEIGHT)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_IMAGE_SIZE, WIDTH * HEIGHT)
yield Timer(CLK_PERIOD * 10)
#Enable image write
control = 0x00
control |= 1 << BIT_CONTROL_ENABLE
control |= 1 << BIT_CONTROL_BACKLIGHT_ENABLE
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
#Stream the RGB Video (32 pixels), 4 rows of 8)
#Write Video to the memodry controller
yield video_out.write(video)
yield Timer(CLK_PERIOD * 1000)
yield video_out.write(video)
yield Timer(CLK_PERIOD * 100)
dut.log.info("Done")
def write_multiple_frames(dut):
"""
Description:
Send multiple images out of the controller
This test will verify that the full images
are successfully sent out and the process of restarting
the next image transfer does not lead to an error
Test ID: 3
Expected Results:
Should read images out of the controller
*** NEED SOMETHING TO VERIFY THE IMAGES ARE CORRECT!!!***
"""
dut.rst <= 1
dut.i_fsync <= 0;
dut.test_id <= 3
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
video_out = AXI4StreamMaster(dut, "AXIMS", dut.clk, width=24)
NUM_FRAMES = 4
HEIGHT = 4
WIDTH = 4
video = []
for y in range (HEIGHT):
line = []
for x in range (WIDTH):
if x == 0:
value = 0xFFFFFF
line.append(value)
elif x == (WIDTH) - 1:
value = 0xFFFFFF
line.append(value)
else:
value = x
line.append(value)
video.append(line)
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
dut.log.info("Ready")
yield Timer(CLK_PERIOD * 10)
control = 0x00
control |= 1 << BIT_CONTROL_CHIP_SELECT
control |= 1 << BIT_CONTROL_RESET_DISPLAY
control |= 1 << BIT_CONTROL_ENABLE
control |= 1 << BIT_CONTROL_BACKLIGHT_ENABLE
control |= 1 << BIT_CONTROL_WRITE_OVERRIDE
#Reset the LCD
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
control &= ~(1 << BIT_CONTROL_RESET_DISPLAY)
control &= ~(1 << BIT_CONTROL_WRITE_OVERRIDE)
dut.i_fsync <= 1
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
#Set the pixel count
yield axim.write(REG_IMAGE_WIDTH, WIDTH)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_IMAGE_HEIGHT, HEIGHT)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_IMAGE_SIZE, WIDTH * HEIGHT)
yield Timer(CLK_PERIOD * 10)
dut.i_fsync <= 0
yield Timer(CLK_PERIOD * 10)
dut.i_fsync <= 1
#Enable image write
control = 0x00
control |= 1 << BIT_CONTROL_ENABLE
control |= 1 << BIT_CONTROL_BACKLIGHT_ENABLE
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
dut.i_fsync <= 1
for line in video:
yield video_out.write(line)
yield Timer(CLK_PERIOD * 10)
dut.i_fsync <= 0
yield Timer(CLK_PERIOD * 10)
dut.i_fsync <= 1
for line in video:
yield video_out.write(line)
yield Timer(CLK_PERIOD * 10)
dut.i_fsync <= 0
yield Timer(CLK_PERIOD * 10)
dut.i_fsync <= 1
for line in video:
yield video_out.write(line)
yield Timer(CLK_PERIOD * 10)
dut.i_fsync <= 0
yield Timer(CLK_PERIOD * 10)
dut.i_fsync <= 1
for line in video:
yield video_out.write(line)
yield Timer(CLK_PERIOD * 10)
dut.i_fsync <= 0
yield Timer(CLK_PERIOD * 200)
def write_single_frame(dut):
"""
Description:
Send a single image to the controller
The signal format should be
Command: Set Memory Address
SEND Red, Blue, Green bytes
Repeat until full image is sent
It's important that the timing of the
sync strobes are good so that the FIFO doesn't
overfill
Test ID: 2
Expected Results:
Should read images out of the controller
*** NEED SOMETHING TO VERIFY THE IMAGES ARE CORRECT!!!***
"""
dut.rst <= 1
dut.i_fsync <= 0;
dut.test_id <= 2
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
video_out = AXI4StreamMaster(dut, "AXIMS", dut.clk, width=24)
NUM_FRAMES = 1
HEIGHT = 4
WIDTH = 4
video = []
for y in range (HEIGHT):
line = []
for x in range (WIDTH):
if x == 0:
value = 0xFFFFFF
line.append(value)
elif x == (WIDTH) - 1:
value = 0xFFFFFF
line.append(value)
else:
value = x
line.append(value)
video.append(line)
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
dut.log.info("Ready")
yield Timer(CLK_PERIOD * 10)
control = 0x00
control |= 1 << BIT_CONTROL_CHIP_SELECT
control |= 1 << BIT_CONTROL_RESET_DISPLAY
control |= 1 << BIT_CONTROL_ENABLE
control |= 1 << BIT_CONTROL_BACKLIGHT_ENABLE
control |= 1 << BIT_CONTROL_WRITE_OVERRIDE
#Reset the LCD
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
control &= ~(1 << BIT_CONTROL_RESET_DISPLAY)
control &= ~(1 << BIT_CONTROL_WRITE_OVERRIDE)
dut.i_fsync <= 1
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
#Set the pixel count
yield axim.write(REG_IMAGE_WIDTH, WIDTH)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_IMAGE_HEIGHT, HEIGHT)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_IMAGE_SIZE, WIDTH * HEIGHT)
yield Timer(CLK_PERIOD * 10)
dut.i_fsync <= 0
yield Timer(CLK_PERIOD * 10)
dut.i_fsync <= 1
#Enable image write
control = 0x00
control |= 1 << BIT_CONTROL_ENABLE
control |= 1 << BIT_CONTROL_BACKLIGHT_ENABLE
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
#Write Video to the video controller
for line in video:
yield video_out.write(line)
yield Timer(CLK_PERIOD * 400)
def read_from_controller(dut):
"""
Description:
Read a 16-bit value from the controller
Test ID: 1
Expected Results:
Receive a read request to address 0xB8
Should read back 0xAAAA
"""
dut.rst <= 1
dut.i_fsync <= 1
dut.test_id <= 1
axim = AXI4LiteMaster(dut, "AXIML", dut.clk)
video_out = AXI4StreamMaster(dut, "AXIMS", dut.clk, width=24)
setup_dut(dut)
yield Timer(CLK_PERIOD * 10)
dut.rst <= 0
dut.log.info("Ready")
yield Timer(CLK_PERIOD * 10)
control = 0x00
control |= 1 << BIT_CONTROL_CHIP_SELECT
control |= 1 << BIT_CONTROL_RESET_DISPLAY
control |= 1 << BIT_CONTROL_ENABLE
control |= 1 << BIT_CONTROL_BACKLIGHT_ENABLE
control |= 1 << BIT_CONTROL_WRITE_OVERRIDE
#Reset the LCD
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
control &= ~(1 << BIT_CONTROL_RESET_DISPLAY)
control &= ~(1 << BIT_CONTROL_WRITE_OVERRIDE)
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
control &= ~(1 << BIT_CONTROL_CHIP_SELECT)
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
control |= 1 << BIT_CONTROL_CHIP_SELECT
control |= 1 << BIT_CONTROL_COMMAND_MODE
# Set the address
READ_ADDR = 0xB8
control |= 1 << BIT_CONTROL_COMMAND_MODE
control &= ~ (1 << BIT_CONTROL_COMMAND_PARAMETER)
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
# Set address
yield axim.write(REG_COMMAND_DATA, READ_ADDR)
yield Timer(CLK_PERIOD * 10)
control |= 1 << BIT_CONTROL_COMMAND_WRITE
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
control &= ~(1 << BIT_CONTROL_COMMAND_WRITE)
control |= 1 << BIT_CONTROL_COMMAND_PARAMETER
control |= 1 << BIT_CONTROL_COMMAND_READ
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
d1 = yield axim.read(REG_COMMAND_DATA)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_CONTROL, control)
yield Timer(CLK_PERIOD * 10)
d2 = yield axim.read(REG_COMMAND_DATA)
d2 = int(d2)
d1 = int(d1 << 8)
data = d1 + d2
yield Timer(CLK_PERIOD * 10)
if data != 0xAAAA:
raise TestFailure("Data should have been 0x%04X but read: 0x%04X" % (0xAAAA, data))
#Set the pixel count
yield axim.write(REG_IMAGE_WIDTH, WIDTH)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_IMAGE_HEIGHT, HEIGHT)
yield Timer(CLK_PERIOD * 10)
yield axim.write(REG_IMAGE_SIZE, WIDTH * HEIGHT)
yield Timer(CLK_PERIOD * 10)