def __init__(self): """ Constructor for a driver instance """ # self._busy = Lock() self._pending = Event(name="Driver._pending") self._sendQ = deque() # Subclasses may already set up logging if not hasattr(self, "log"): self.log = SimLog("cocotb.driver.%s" % (self.__class__.__name__)) # Create an independent coroutine which can send stuff self._thread = cocotb.scheduler.add(self._send_thread())
def __init__(self, entity, name, clock, **kwargs): # emulate keyword-only arguments in python 2 index = kwargs.pop("array_idx", None) reject_remaining_kwargs('__init__', kwargs) self.log = SimLog("cocotb.%s.%s" % (entity._name, name)) Driver.__init__(self) self.entity = entity self.clock = clock self.bus = Bus(self.entity, name, self._signals, self._optional_signals, array_idx=index) # Give this instance a unique name self.name = name if index is None else "%s_%d" % (name, index)
def __init__(self, entity, name, clock, **kwargs): self.log = SimLog("cocotb.%s.%s" % (entity._name, name)) Driver.__init__(self) self.entity = entity self.clock = clock index = kwargs.get("array_idx") self.bus = Bus(self.entity, name, self._signals, self._optional_signals, array_idx=index) # Give this instance a unique name self.name = name if index is None else "%s_%d" % (name, index)
def __init__(self, entity: SimHandleBase, name: Optional[str], clock: SimHandleBase, **kwargs: Any): index = kwargs.get("array_idx", None) self.log = SimLog("cocotb.%s.%s" % (entity._name, name)) Driver.__init__(self) self.entity = entity self.clock = clock self.bus = Bus( self.entity, name, self._signals, optional_signals=self._optional_signals, **kwargs ) # Give this instance a unique name self.name = name if index is None else "%s_%d" % (name, index)
def __init__(self, inst, parent): self.error_messages = [] RunningCoroutine.__init__(self, inst, parent) self.log = SimLog("cocotb.test.%s" % self.__name__, id(self)) self.started = False self.start_time = 0 self.start_sim_time = 0 self.expect_fail = parent.expect_fail self.expect_error = parent.expect_error self.skip = parent.skip self.stage = parent.stage self.handler = RunningTest.ErrorLogHandler(self._handle_error_message) cocotb.log.addHandler(self.handler)
def __init__(self, dut): self.dut = dut self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.fork(Clock(dut.clk, 6.4, units="ns").start()) # Ethernet cocotb.fork(Clock(dut.qsfp0_rx_clk_1, 6.4, units="ns").start()) self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1) cocotb.fork(Clock(dut.qsfp0_tx_clk_1, 6.4, units="ns").start()) self.qsfp0_1_sink = XgmiiSink(dut.qsfp0_txd_1, dut.qsfp0_txc_1, dut.qsfp0_tx_clk_1, dut.qsfp0_tx_rst_1) cocotb.fork(Clock(dut.qsfp0_rx_clk_2, 6.4, units="ns").start()) self.qsfp0_2_source = XgmiiSource(dut.qsfp0_rxd_2, dut.qsfp0_rxc_2, dut.qsfp0_rx_clk_2, dut.qsfp0_rx_rst_2) cocotb.fork(Clock(dut.qsfp0_tx_clk_2, 6.4, units="ns").start()) self.qsfp0_2_sink = XgmiiSink(dut.qsfp0_txd_2, dut.qsfp0_txc_2, dut.qsfp0_tx_clk_2, dut.qsfp0_tx_rst_2) cocotb.fork(Clock(dut.qsfp0_rx_clk_3, 6.4, units="ns").start()) self.qsfp0_3_source = XgmiiSource(dut.qsfp0_rxd_3, dut.qsfp0_rxc_3, dut.qsfp0_rx_clk_3, dut.qsfp0_rx_rst_3) cocotb.fork(Clock(dut.qsfp0_tx_clk_3, 6.4, units="ns").start()) self.qsfp0_3_sink = XgmiiSink(dut.qsfp0_txd_3, dut.qsfp0_txc_3, dut.qsfp0_tx_clk_3, dut.qsfp0_tx_rst_3) cocotb.fork(Clock(dut.qsfp0_rx_clk_4, 6.4, units="ns").start()) self.qsfp0_4_source = XgmiiSource(dut.qsfp0_rxd_4, dut.qsfp0_rxc_4, dut.qsfp0_rx_clk_4, dut.qsfp0_rx_rst_4) cocotb.fork(Clock(dut.qsfp0_tx_clk_4, 6.4, units="ns").start()) self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4, dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4) cocotb.fork(Clock(dut.qsfp1_rx_clk_1, 6.4, units="ns").start()) self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1) cocotb.fork(Clock(dut.qsfp1_tx_clk_1, 6.4, units="ns").start()) self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1) cocotb.fork(Clock(dut.qsfp1_rx_clk_2, 6.4, units="ns").start()) self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2) cocotb.fork(Clock(dut.qsfp1_tx_clk_2, 6.4, units="ns").start()) self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2) cocotb.fork(Clock(dut.qsfp1_rx_clk_3, 6.4, units="ns").start()) self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3) cocotb.fork(Clock(dut.qsfp1_tx_clk_3, 6.4, units="ns").start()) self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3) cocotb.fork(Clock(dut.qsfp1_rx_clk_4, 6.4, units="ns").start()) self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4) cocotb.fork(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start()) self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4) dut.sw.setimmediatevalue(0)
def __init__(self, dut): self.dut = dut self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.fork(Clock(dut.clk, 2.56, units="ns").start()) # Ethernet cocotb.fork(Clock(dut.qsfp_0_rx_clk_0, 2.56, units="ns").start()) self.qsfp_0_0_source = XgmiiSource(dut.qsfp_0_rxd_0, dut.qsfp_0_rxc_0, dut.qsfp_0_rx_clk_0, dut.qsfp_0_rx_rst_0) cocotb.fork(Clock(dut.qsfp_0_tx_clk_0, 2.56, units="ns").start()) self.qsfp_0_0_sink = XgmiiSink(dut.qsfp_0_txd_0, dut.qsfp_0_txc_0, dut.qsfp_0_tx_clk_0, dut.qsfp_0_tx_rst_0) cocotb.fork(Clock(dut.qsfp_0_rx_clk_1, 2.56, units="ns").start()) self.qsfp_0_1_source = XgmiiSource(dut.qsfp_0_rxd_1, dut.qsfp_0_rxc_1, dut.qsfp_0_rx_clk_1, dut.qsfp_0_rx_rst_1) cocotb.fork(Clock(dut.qsfp_0_tx_clk_1, 2.56, units="ns").start()) self.qsfp_0_1_sink = XgmiiSink(dut.qsfp_0_txd_1, dut.qsfp_0_txc_1, dut.qsfp_0_tx_clk_1, dut.qsfp_0_tx_rst_1) cocotb.fork(Clock(dut.qsfp_0_rx_clk_2, 2.56, units="ns").start()) self.qsfp_0_2_source = XgmiiSource(dut.qsfp_0_rxd_2, dut.qsfp_0_rxc_2, dut.qsfp_0_rx_clk_2, dut.qsfp_0_rx_rst_2) cocotb.fork(Clock(dut.qsfp_0_tx_clk_2, 2.56, units="ns").start()) self.qsfp_0_2_sink = XgmiiSink(dut.qsfp_0_txd_2, dut.qsfp_0_txc_2, dut.qsfp_0_tx_clk_2, dut.qsfp_0_tx_rst_2) cocotb.fork(Clock(dut.qsfp_0_rx_clk_3, 2.56, units="ns").start()) self.qsfp_0_3_source = XgmiiSource(dut.qsfp_0_rxd_3, dut.qsfp_0_rxc_3, dut.qsfp_0_rx_clk_3, dut.qsfp_0_rx_rst_3) cocotb.fork(Clock(dut.qsfp_0_tx_clk_3, 2.56, units="ns").start()) self.qsfp_0_3_sink = XgmiiSink(dut.qsfp_0_txd_3, dut.qsfp_0_txc_3, dut.qsfp_0_tx_clk_3, dut.qsfp_0_tx_rst_3) cocotb.fork(Clock(dut.qsfp_1_rx_clk_0, 2.56, units="ns").start()) self.qsfp_1_0_source = XgmiiSource(dut.qsfp_1_rxd_0, dut.qsfp_1_rxc_0, dut.qsfp_1_rx_clk_0, dut.qsfp_1_rx_rst_0) cocotb.fork(Clock(dut.qsfp_1_tx_clk_0, 2.56, units="ns").start()) self.qsfp_1_0_sink = XgmiiSink(dut.qsfp_1_txd_0, dut.qsfp_1_txc_0, dut.qsfp_1_tx_clk_0, dut.qsfp_1_tx_rst_0) cocotb.fork(Clock(dut.qsfp_1_rx_clk_1, 2.56, units="ns").start()) self.qsfp_1_1_source = XgmiiSource(dut.qsfp_1_rxd_1, dut.qsfp_1_rxc_1, dut.qsfp_1_rx_clk_1, dut.qsfp_1_rx_rst_1) cocotb.fork(Clock(dut.qsfp_1_tx_clk_1, 2.56, units="ns").start()) self.qsfp_1_1_sink = XgmiiSink(dut.qsfp_1_txd_1, dut.qsfp_1_txc_1, dut.qsfp_1_tx_clk_1, dut.qsfp_1_tx_rst_1) cocotb.fork(Clock(dut.qsfp_1_rx_clk_2, 2.56, units="ns").start()) self.qsfp_1_2_source = XgmiiSource(dut.qsfp_1_rxd_2, dut.qsfp_1_rxc_2, dut.qsfp_1_rx_clk_2, dut.qsfp_1_rx_rst_2) cocotb.fork(Clock(dut.qsfp_1_tx_clk_2, 2.56, units="ns").start()) self.qsfp_1_2_sink = XgmiiSink(dut.qsfp_1_txd_2, dut.qsfp_1_txc_2, dut.qsfp_1_tx_clk_2, dut.qsfp_1_tx_rst_2) cocotb.fork(Clock(dut.qsfp_1_rx_clk_3, 2.56, units="ns").start()) self.qsfp_1_3_source = XgmiiSource(dut.qsfp_1_rxd_3, dut.qsfp_1_rxc_3, dut.qsfp_1_rx_clk_3, dut.qsfp_1_rx_rst_3) cocotb.fork(Clock(dut.qsfp_1_tx_clk_3, 2.56, units="ns").start()) self.qsfp_1_3_sink = XgmiiSink(dut.qsfp_1_txd_3, dut.qsfp_1_txc_3, dut.qsfp_1_tx_clk_3, dut.qsfp_1_tx_rst_3) dut.user_sw.setimmediatevalue(0)
async def get_adapter_test_bfms(dut): SimLog("bfm").setLevel(logging.DEBUG) wb_bfm = WishboneBfm(clock=dut.clock, reset=dut.reset, entity=dut, prefix="wb_") bus_bfm = CoppervBusSourceBfm(clock=dut.clock, reset=dut.reset, entity=dut, prefix="bus_") wb_bfm.sink_init() bus_bfm.init() wb_bfm.start_clock() await wb_bfm.reset() return wb_bfm, bus_bfm
def __init__(self, inst, parent): self.error_messages = [] RunningCoroutine.__init__(self, inst, parent) self.log = SimLog("cocotb.test.%s" % self.__name__, id(self)) self.started = False self.start_time = 0 self.start_sim_time = 0 self.expect_fail = parent.expect_fail self.expect_error = parent.expect_error self.skip = parent.skip self.stage = parent.stage self._id = parent._id # make sure not to create a circular reference here self.handler = RunningTest.ErrorLogHandler(self.error_messages.append)
def __init__(self, root_name, modules, tests=None): """ Args: modules (list): A list of python module names to run Kwargs """ self._queue = [] self._root_name = root_name self._dut = None self._modules = modules self._functions = tests self._running_test = None self._cov = None self.log = SimLog("cocotb.regression")
async def run_ready_valid_bfm_test(dut): """ ready/valid BFM test """ SimLog("bfm").setLevel(logging.DEBUG) reference = 123 signals = ReadyValidBfm.Signals(ready=dut.ready, valid=dut.valid) payload = dict(data=dut.data) bfm = ReadyValidBfm(dut.clock, signals, payload, reset=dut.reset) bfm.start_clock() await bfm.reset() await bfm.drive_ready(1) send_task = cocotb.start_soon(bfm.send_payload(data=reference)) received = await anext(bfm.recv_payload()) assert received['data'] == reference await Join(send_task) await RisingEdge(dut.clock)
def read_elf(test_elf, sections=['.text']): log = SimLog(__name__ + '.read_elf') with test_elf.open('rb') as file: elffile = ELFFile(file) elf = {} for spec in sections: section = elffile.get_section_by_name(spec) log.debug('read_elf %s spec: %s', test_elf, spec) if section is not None: elf[spec] = dict( addr=section['sh_addr'], data=section.data(), ) #log.debug(f"elf: {elf}") return elf
def __init__(self, handle): """ Args: handle (integer) : the GPI handle to the simulator object """ self._handle = handle self._len = None self._sub_handles = {} # Dictionary of children self._invalid_sub_handles = {} # Dictionary of invalid queries self._discovered = False self._name = simulator.get_name_string(self._handle) self._type = simulator.get_type_string(self._handle) self._fullname = self._name + "(%s)" % self._type self._log = SimLog("cocotb.%s" % self._name) self._log.debug("Created")
def __init__(self, handle): """ Args: _handle [integer] : vpi/vhpi handle to the simulator object """ self._handle = handle # handle used for future simulator transactions self._sub_handles = {} # Dict. of SimHandle objects created by getattr self._len = None self.name = simulator.get_name_string(self._handle) self.fullname = '%s(%s)' % (self.name, simulator.get_type_string(self._handle)) self.log = SimLog('cocotb.' + self.name) self.log.debug("Created!") self._r_edge = _RisingEdge(self) self._f_edge = _FallingEdge(self)
def __init__(self, callback=None, event=None): self._event = event self._wait_event = Event() self._recvQ = deque() self._callbacks = [] self.stats = MonitorStatistics() # Sub-classes may already set up logging if not hasattr(self, "log"): self.log = SimLog("cocotb.monitor.%s" % (type(self).__qualname__)) if callback is not None: self.add_callback(callback) # Create an independent coroutine which can receive stuff self._thread = cocotb.scheduler.add(self._monitor_recv())
def compile_riscv_test(asm_path): log = SimLog(__name__ + ".compile_riscv_test") test_s = asm_path crt0_s = sim_dir / 'tests/common/crt0.S' crt0_obj = Path(crt0_s.name).with_suffix('.o') test_obj = Path(test_s.name).with_suffix('.o') test_elf = Path(test_s.name).with_suffix('.elf') common_dir = sim_dir / 'tests/common' macros_dir = sim_dir / 'tests/isa/macros/scalar' cmd_crt0 = f"riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -I{common_dir} -I{macros_dir} -g -DENTRY_POINT={test_s.stem} -c {crt0_s} -o {crt0_obj}" cmd_test = f"riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -I{common_dir} -I{macros_dir} -g -DTEST_NAME={test_s.stem} -c {test_s} -o {test_obj}" cmd_link = f"riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -I{common_dir} -I{macros_dir} -Wl,-T,{linker_script},-Bstatic -nostartfiles -ffreestanding -g {crt0_obj} {test_obj} -o {test_elf}" run(cmd_crt0) run(cmd_test) run(cmd_link) return process_elf(test_elf)
def __init__(self, dut): self.dut = dut self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start()) # PCIe self.rc = RootComplex() self.dev = PcieIfDevice( clk=dut.clk, rst=dut.rst, rx_req_tlp_bus=PcieIfRxBus.from_prefix(dut, "rx_req_tlp"), tx_cpl_tlp_bus=PcieIfTxBus.from_prefix(dut, "tx_cpl_tlp"), tx_wr_req_tlp_bus=PcieIfTxBus.from_prefix(dut, "tx_wr_req_tlp"), wr_req_tx_seq_num=dut.s_axis_wr_req_tx_seq_num, wr_req_tx_seq_num_valid=dut.s_axis_wr_req_tx_seq_num_valid, tx_rd_req_tlp_bus=PcieIfTxBus.from_prefix(dut, "tx_rd_req_tlp"), rd_req_tx_seq_num=dut.s_axis_rd_req_tx_seq_num, rd_req_tx_seq_num_valid=dut.s_axis_rd_req_tx_seq_num_valid, rx_cpl_tlp_bus=PcieIfRxBus.from_prefix(dut, "rx_cpl_tlp"), cfg_max_payload=dut.max_payload_size, cfg_max_read_req=dut.max_read_request_size, cfg_ext_tag_enable=dut.ext_tag_enable, tx_fc_ph_av=dut.pcie_tx_fc_ph_av, tx_fc_pd_av=dut.pcie_tx_fc_pd_av, tx_fc_nph_av=dut.pcie_tx_fc_nph_av, ) self.dev.log.setLevel(logging.DEBUG) self.rc.make_port().connect(self.dev) self.dev.functions[0].msi_multiple_message_capable = 5 self.dev.functions[0].configure_bar(0, 2**len(dut.axil_ctrl_awaddr)) self.dev.functions[0].configure_bar(2, 2**len(dut.axi_ram_awaddr)) dut.bus_num.setimmediatevalue(0) # monitor error outputs self.status_error_cor_asserted = False self.status_error_uncor_asserted = False cocotb.start_soon(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def F_find_second_mk_test(dut): """ Resets and finds it again """ log = SimLog("cocotb.%s" % dut._name) log.setLevel(logging.DEBUG) cocotb.fork(Clock(dut.clk_i, 1000).start()) filename = '../test_data/wpa2-psk-linksys.hccap' start = '2000000000' end = '2000000300' #Comparison currently hardcoded as 1000000200 print_process_vars(dut) dut.cs_i <= 1 yield reset(dut) yield RisingEdge(dut.clk_i) print_process_vars(dut) yield load_file(dut, filename) print_process_vars(dut) yield load_mk(dut, start) print_process_vars(dut) yield load_mk(dut, end) #dut.main1.load_i <= 1 #yield RisingEdge(dut.clk_i) # dut.rst_i <= 1 # yield RisingEdge(dut.clk_i) # dut.rst_i <= 0 # yield RisingEdge(dut.clk_i) #dut.main1.load_i <= 0 #This clock isn't necessary while pipelining #yield RisingEdge(dut.clk_i) print_process_vars(dut) yield wait_process(dut) print_process_vars(dut) if int(str(dut.pmk_valid), 2) == 0: raise TestFailure("MK search failed") else: log.info("Master key found!")
def __init__(self, entity, name, clock, reset=None): self.log = SimLog("cocotb.%s.%s" % (entity._name, name)) self.log.info("AXI master model") self.log.info("cocotbext-axi version %s", __version__) self.log.info("Copyright (c) 2020 Alex Forencich") self.log.info("https://github.com/alexforencich/cocotbext-axi") self.reset = reset self.aw_channel = AxiAWSource(entity, name, clock, reset) self.w_channel = AxiWSource(entity, name, clock, reset) self.b_channel = AxiBSink(entity, name, clock, reset) self.active_tokens = set() self.write_command_queue = deque() self.write_command_sync = Event() self.write_resp_queue = deque() self.write_resp_sync = Event() self.write_resp_set = set() self.id_queue = deque(range(2**len(self.aw_channel.bus.awid))) self.id_sync = Event() self.int_write_resp_command_queue = deque() self.int_write_resp_command_sync = Event() self.int_write_resp_queue_list = {} self.in_flight_operations = 0 self.width = len(self.w_channel.bus.wdata) self.byte_size = 8 self.byte_width = self.width // self.byte_size self.strb_mask = 2**self.byte_width - 1 self.max_burst_len = 256 self.max_burst_size = (self.byte_width - 1).bit_length() assert self.byte_width == len(self.w_channel.bus.wstrb) assert self.byte_width * self.byte_size == self.width assert len(self.b_channel.bus.bid) == len(self.aw_channel.bus.awid) cocotb.fork(self._process_write()) cocotb.fork(self._process_write_resp())
def __init__(self, handle, path): """ .. Constructor. This RST comment works around sphinx-doc/sphinx#6885 Args: handle (int): The GPI handle to the simulator object. path (str): Path to this handle, ``None`` if root. """ self._handle = handle self._len = None # type: int """The "length" (the number of elements) of the underlying object. For vectors this is the number of bits.""" self._sub_handles = {} # type: dict """Dictionary of this handle's children.""" self._invalid_sub_handles = set() # type: set """Python :class:`set` of invalid queries, for caching purposes.""" self._name = self._handle.get_name_string() # type: str """The name of an object. :meta public: """ self._type = self._handle.get_type_string() # type: str """The type of an object as a string. :meta public: """ self._fullname = self._name + "(%s)" % self._type # type: str """The name of an object with its type appended in parentheses.""" self._path = self._name if path is None else path # type: str """The path to this handle, or its name if this is the root handle. :meta public: """ self._log = SimLog("cocotb.%s" % self._name) """The logging object.""" self._log.debug("Created") self._def_name = self._handle.get_definition_name() # type: str """The name of a GPI object's definition. This is the value of ``vpiDefName`` for VPI, ``vhpiNameP`` for VHPI, and ``mti_GetPrimaryName`` for FLI. Support for this depends on the specific object type and simulator used. :meta public: """ self._def_file = self._handle.get_definition_file() # type: str """The name of the file that sources the object's definition.
def __init__(self, entity, name, clock, reset=None, *args, **kwargs): self.log = SimLog("cocotb.%s.%s" % (entity._name, name)) self.entity = entity self.clock = clock self.reset = reset self.bus = Bus(self.entity, name, self._signals, optional_signals=self._optional_signals, **kwargs) self.log.info("AXI stream sink") self.log.info("cocotbext-axi version %s", __version__) self.log.info("Copyright (c) 2020 Alex Forencich") self.log.info("https://github.com/alexforencich/cocotbext-axi") super().__init__(*args, **kwargs) self.active = False self.queue = deque() self.sync = Event() self.read_queue = [] self.pause = False self._pause_generator = None self._pause_cr = None self.queue_occupancy_bytes = 0 self.queue_occupancy_frames = 0 self.queue_occupancy_limit_bytes = None self.queue_occupancy_limit_frames = None self.width = len(self.bus.tdata) self.byte_width = 1 self.reset = reset if hasattr(self.bus, "tready"): self.bus.tready.setimmediatevalue(0) if hasattr(self.bus, "tkeep"): self.byte_width = len(self.bus.tkeep) self.byte_size = self.width // self.byte_width self.byte_mask = 2**self.byte_size - 1 cocotb.fork(self._run())
def __init__(self, entity, name, clock): """ Args: entity (SimHandle) : a handle to the simulator entity name (str) : name of this bus. None for nameless bus, e.g. bus-signals in an interface or a modport (untested on struct/record, but could work here as well) clock (SimHandle) : A handle to the clock associated with this bus """ self.log = SimLog("cocotb.%s.%s" % (entity.name, name)) Driver.__init__(self) self.entity = entity self.name = name self.clock = clock self.bus = Bus(self.entity, self.name, self._signals, self._optional_signals)
def __init__(self, name, transaction_type, bfm_recv_req, bfm_recv_resp=None, callback=None, event=None, bus_name=None): self.bus_name = bus_name if self.bus_name is None: self.bus_name = name self.name = name self.log = SimLog(f"cocotb.{self.name}") self.bfm_recv_req = bfm_recv_req self.bfm_recv_resp = bfm_recv_resp self.transaction_type = transaction_type super().__init__(callback=callback, event=event)
def __init__(self, handle, path): """ Args: handle (integer) : the GPI handle to the simulator object path (string) : path to this handle, None if root """ self._handle = handle self._len = None self._sub_handles = {} # Dictionary of children self._invalid_sub_handles = {} # Dictionary of invalid queries self._name = simulator.get_name_string(self._handle) self._type = simulator.get_type_string(self._handle) self._fullname = self._name + "(%s)" % self._type self._path = self._name if path is None else path self._log = SimLog("cocotb.%s" % self._name) self._log.debug("Created")
def Z_wavedrom_test(dut): """ Generate a JSON wavedrom diagram of a trace """ log = SimLog("cocotb.%s" % dut._name) cocotb.fork(Clock(dut.clk_i, 100).start()) mockSha1 = wpa2slow.sha1.Sha1Model() mockObject = wpa2slow.hmac.HmacModel(mockSha1) shaObject = HmacDriver(dut, None, dut.clk_i) #yield load_random_data(dut, log, mockObject, 80) args = [ dut.rst_i, dut.dat_i, dut.i, dut.i_mux ] with cocotb.wavedrom.trace(*args, clk=dut.clk_i) as waves: yield RisingEdge(dut.clk_i) yield reset(dut) yield load_random_data(dut, log, mockObject, 16) mockObject.processInput() mockObject.processBuffer() if _debug == True: log.info(convert_hex(dut.pbuffer1.test_word_3).zfill(8)) yield load_random_data(dut, log, mockObject, 60) if _debug == True: log.info(convert_hex(dut.pbuffer1.test_word_3).zfill(8)) yield load_random_data(dut, log, mockObject, 90) if _debug == True: log.info(convert_hex(dut.pbuffer1.test_word_3).zfill(8)) log.info(convert_hex(dut.pbuffer1.test_word_4).zfill(8)) waves.write('wavedrom.json', header = {'text':'D_wavedrom_test', 'tick':-1}, config = {'hscale':5})
def __init__(self, dut): self.dut = dut self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.fork(Clock(dut.clk, 6.4, units="ns").start()) # Ethernet cocotb.fork(Clock(dut.sfp0_rx_clk, 6.4, units="ns").start()) self.sfp0_source = XgmiiSource(dut.sfp0_rxd, dut.sfp0_rxc, dut.sfp0_rx_clk, dut.sfp0_rx_rst) cocotb.fork(Clock(dut.sfp0_tx_clk, 6.4, units="ns").start()) self.sfp0_sink = XgmiiSink(dut.sfp0_txd, dut.sfp0_txc, dut.sfp0_tx_clk, dut.sfp0_tx_rst) cocotb.fork(Clock(dut.sfp1_rx_clk, 6.4, units="ns").start()) self.sfp1_source = XgmiiSource(dut.sfp1_rxd, dut.sfp1_rxc, dut.sfp1_rx_clk, dut.sfp1_rx_rst) cocotb.fork(Clock(dut.sfp1_tx_clk, 6.4, units="ns").start()) self.sfp1_sink = XgmiiSink(dut.sfp1_txd, dut.sfp1_txc, dut.sfp1_tx_clk, dut.sfp1_tx_rst) cocotb.fork(Clock(dut.sfp2_rx_clk, 6.4, units="ns").start()) self.sfp2_source = XgmiiSource(dut.sfp2_rxd, dut.sfp2_rxc, dut.sfp2_rx_clk, dut.sfp2_rx_rst) cocotb.fork(Clock(dut.sfp2_tx_clk, 6.4, units="ns").start()) self.sfp2_sink = XgmiiSink(dut.sfp2_txd, dut.sfp2_txc, dut.sfp2_tx_clk, dut.sfp2_tx_rst) cocotb.fork(Clock(dut.sfp3_rx_clk, 6.4, units="ns").start()) self.sfp3_source = XgmiiSource(dut.sfp3_rxd, dut.sfp3_rxc, dut.sfp3_rx_clk, dut.sfp3_rx_rst) cocotb.fork(Clock(dut.sfp3_tx_clk, 6.4, units="ns").start()) self.sfp3_sink = XgmiiSink(dut.sfp3_txd, dut.sfp3_txc, dut.sfp3_tx_clk, dut.sfp3_tx_rst) dut.btnu.setimmediatevalue(0) dut.btnl.setimmediatevalue(0) dut.btnd.setimmediatevalue(0) dut.btnr.setimmediatevalue(0) dut.btnc.setimmediatevalue(0) dut.sw.setimmediatevalue(0) dut.uart_rxd.setimmediatevalue(0) dut.uart_rts.setimmediatevalue(0)
def __init__(self, dut): self.dut = dut self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) # Ethernet cocotb.start_soon(Clock(dut.sfp_1_rx_clk, 6.4, units="ns").start()) self.sfp_1_source = XgmiiSource(dut.sfp_1_rxd, dut.sfp_1_rxc, dut.sfp_1_rx_clk, dut.sfp_1_rx_rst) cocotb.start_soon(Clock(dut.sfp_1_tx_clk, 6.4, units="ns").start()) self.sfp_1_sink = XgmiiSink(dut.sfp_1_txd, dut.sfp_1_txc, dut.sfp_1_tx_clk, dut.sfp_1_tx_rst) cocotb.start_soon(Clock(dut.sfp_2_rx_clk, 6.4, units="ns").start()) self.sfp_2_source = XgmiiSource(dut.sfp_2_rxd, dut.sfp_2_rxc, dut.sfp_2_rx_clk, dut.sfp_2_rx_rst) cocotb.start_soon(Clock(dut.sfp_2_tx_clk, 6.4, units="ns").start()) self.sfp_2_sink = XgmiiSink(dut.sfp_2_txd, dut.sfp_2_txc, dut.sfp_2_tx_clk, dut.sfp_2_tx_rst)
def __init__(self, dut, speed=1000e6): self.dut = dut self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.fork(Clock(dut.clk, 8, units="ns").start()) # Ethernet self.gmii_phy = GmiiPhy(dut.phy_txd, dut.phy_tx_er, dut.phy_tx_en, dut.phy_tx_clk, dut.phy_gtx_clk, dut.phy_rxd, dut.phy_rx_er, dut.phy_rx_dv, dut.phy_rx_clk, speed=speed) dut.btnu.setimmediatevalue(0) dut.btnl.setimmediatevalue(0) dut.btnd.setimmediatevalue(0) dut.btnr.setimmediatevalue(0) dut.btnc.setimmediatevalue(0) dut.sw.setimmediatevalue(0) dut.uart_rxd.setimmediatevalue(0)
async def unit_test(dut): """ Copperv unit tests """ test_name = os.environ['TEST_NAME'] params = TestParameters(test_name, **unit_tests[test_name]) SimLog("cocotb").setLevel(logging.DEBUG) instruction_memory = compile_instructions(params.instructions) data_memory = parse_data_memory(params.data_memory) tb = Testbench(dut, test_name, expected_data_read=params.expected_data_read, expected_data_write=params.expected_data_write, expected_regfile_read=params.expected_regfile_read, expected_regfile_write=params.expected_regfile_write, instruction_memory=instruction_memory, data_memory=data_memory) tb.bus_bfm.start_clock() await tb.bus_bfm.reset() await tb.finish()
def __init__(self, entity, name, clock, reset=None, reset_n=None, callback=None, event=None): self.log = SimLog("cocotb.%s.%s" % (entity._name, name)) self.entity = entity self.name = name self.clock = clock self.bus = Bus(self.entity, self.name, self._signals, optional_signals=self._optional_signals) self._reset = reset self._reset_n = reset_n Monitor.__init__(self, callback=callback, event=event)