def test_dff_vhdl_testcase(parameters):
run(
toplevel_lang="vhdl",
vhdl_sources=[os.path.join(tests_dir, "test_parameters.vhdl")],
toplevel="test_parameters",
module="test_parameters",
parameters=parameters,
extra_env=parameters,
sim_build="sim_build/" + "_".join(
("{}={}".format(*i) for i in parameters.items())),
)
def test_batch_normalization():
generics = {}
run(
vhdl_sources=get_files(
pathlib.Path(__file__).parent.absolute() / ".." / "src", "*.vhd"
),
toplevel="batch_normalization",
module="test_batch_normalization",
compile_args=["--work=bnn_lib", "--std=08"],
parameters=generics,
)
def test_cluster_packer(station, oneshot, deadtime):
tests_dir = os.path.abspath(os.path.dirname(__file__))
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', 'hdl'))
module = os.path.splitext(os.path.basename(__file__))[0]
vhdl_sources = [
os.path.join(rtl_dir, f"cluster_pkg.vhd"),
os.path.join(rtl_dir, f"fixed_delay.vhd"),
os.path.join(rtl_dir, f"sbit_oneshot.vhd"),
os.path.join(rtl_dir, f"../../oh_fe/utils/clock_strobe.vhd"),
os.path.join(rtl_dir, f"truncate_lsb.vhd"),
os.path.join(rtl_dir, f"bitonic_exchange.vhd"),
os.path.join(rtl_dir, f"bitonic_merge.vhd"),
os.path.join(rtl_dir, f"bitonic_sorter.vhd"),
os.path.join(rtl_dir, f"find_clusters.vhd"),
os.path.join(rtl_dir, f"top_cluster_packer.vhd")
]
verilog_sources = [
os.path.join(rtl_dir, f"find_cluster_primaries.v"),
os.path.join(rtl_dir, f"count.v"),
os.path.join(rtl_dir, f"consecutive_count.v"),
os.path.join(rtl_dir, f"priority.v")
]
parameters = {}
parameters['STATION'] = station
parameters['DEADTIME'] = deadtime
parameters['ONESHOT'] = oneshot
if station == 2:
parameters['NUM_VFATS'] = 12
else:
parameters['NUM_VFATS'] = 24
if station == 2:
parameters['NUM_PARTITIONS'] = 2
else:
parameters['NUM_PARTITIONS'] = 8
os.environ["SIM"] = "questa"
run(
verilog_sources=verilog_sources,
vhdl_sources=vhdl_sources,
module=module,
toplevel="cluster_packer",
toplevel_lang="vhdl",
parameters=parameters,
# sim_args = ["do cluster_packer_wave.do"],
# extra_env = {"SIM": "questa"},
gui=0)
def test_dff_verilog_testcase(parameters):
run(
verilog_sources=[os.path.join(tests_dir, "test_parameters.v")],
toplevel="test_parameters",
module="test_parameters",
parameters=parameters,
includes=[os.path.join(tests_dir, "includes")],
defines=["DEFINE=1"],
extra_env=parameters,
sim_build="sim_build/" + "_".join(
("{}={}".format(*i) for i in parameters.items())),
)
def test_adder_vhdl():
run(
vhdl_sources=[os.path.join(example_dir, "adder", "hdl", "adder.vhdl")],
toplevel="adder",
python_search=[
os.path.join(example_dir, "adder", "tests"),
os.path.join(example_dir, "adder", "model")
],
module="test_adder",
toplevel_lang="vhdl",
force_compile=True,
)
def test_ping_tun_tap():
if not (os.name == "posix" and os.geteuid() == 0):
pytest.skip("This test works only on a POSIX OS with admin rights")
run(
verilog_sources=[
os.path.join(example_dir, "ping_tun_tap", "hdl", "icmp_reply.sv")
],
toplevel="icmp_reply",
python_search=[os.path.join(example_dir, "ping_tun_tap", "tests")],
module="test_icmp_reply",
)
def test_adder_verilog():
run(
verilog_sources=[
os.path.join(example_dir, "adder", "hdl", "adder.sv")
],
toplevel="adder",
python_search=[
os.path.join(example_dir, "adder", "tests"),
os.path.join(example_dir, "adder", "model")
],
module="test_adder",
force_compile=True,
)
def test_maximum_pooling(kernel_size, channel):
generics = {
"C_KERNEL_SIZE": kernel_size,
"C_CHANNEL": channel,
}
run(
vhdl_sources=get_files(
pathlib.Path(__file__).parent.absolute() / ".." / "src", "*.vhd"),
toplevel="maximum_pooling",
module="test_maximum_pooling",
compile_args=["--work=bnn_lib", "--std=08"],
parameters=generics,
)
def test_inst(inst):
elf_dir = "/usr/riscv32-unknown-elf/share/riscv-tests/isa"
with prepare(elf_dir, inst) as top_v:
simulator.run(
verilog_sources=[
"build/ousia_0/src/ousia_0/Naive.v", "naive_soc.v", top_v
],
includes=includes,
toplevel="cocotb_top",
module="riscv_test",
sim_build="sim_build/" + inst,
# extra_args=["--trace", "--trace-structs"],
)
def test_mean():
run(
vhdl_sources=[
os.path.join(example_dir, "mean", "hdl", "mean_pkg.vhd"),
os.path.join(example_dir, "mean", "hdl", "mean.vhd")
],
verilog_sources=[
os.path.join(example_dir, "mean", "hdl", "mean_sv.sv")
],
toplevel="mean_sv",
python_search=[os.path.join(example_dir, "mean", "tests")],
module="test_mean",
force_compile=True,
)
def test_axi_lite_slave():
run(
verilog_sources=[
os.path.join(example_dir, "axi_lite_slave", "hdl",
"axi_lite_slave.v"),
os.path.join(example_dir, "axi_lite_slave", "hdl",
"axi_lite_demo.v"),
os.path.join(example_dir, "axi_lite_slave", "hdl",
"tb_axi_lite_slave.v"),
],
toplevel="tb_axi_lite_slave",
includes=[os.path.join(example_dir, "axi_lite_slave", "hdl")],
python_search=[os.path.join(example_dir, "axi_lite_slave", "tests")],
module="test_axi_lite_slave",
)
def run_simulator(self,
name=None,
parameters=None,
module=None,
values=None):
if name is None:
name = self.module_name
if module is None:
module = f'tests.test_{name}'
parameters = self.transform_params(parameters)
values = self.transform_params(values)
os.environ['SIM'] = 'icarus'
print(f'Testing {name} with parameters: {parameters}')
print(f'Testing {name} with values: {values}')
extra_env = {}
if parameters is not None:
for key, value in parameters.items():
extra_env[key] = value
if values is not None:
for key, value in values.items():
extra_env[key] = value
return simulator.run(
verilog_sources=self.list_verilog_files(),
toplevel=name,
module=module,
parameters=parameters,
extra_env=extra_env,
sim_build="sim_build/" + "_".join(
("{}={}".format(*i) for i in parameters.items())),
)
def test_average_pooling():
generics = {
"C_BITWIDTH": 8,
"C_CHANNEL": 6,
"C_IMG_WIDTH": 6,
"C_IMG_HEIGHT": 6,
}
run(
vhdl_sources=get_files(
pathlib.Path(__file__).parent.absolute() / ".." / "src", "*.vhd"
),
toplevel="average_pooling",
module="test_average_pooling",
compile_args=["--work=bnn_lib", "--std=08"],
parameters=generics,
)
def test_mixed_top_verilog():
run(
vhdl_sources=[
os.path.join(example_dir, "endian_swapper", "hdl",
"endian_swapper.vhdl")
],
verilog_sources=[
os.path.join(example_dir, "endian_swapper", "hdl",
"endian_swapper.sv"),
os.path.join(example_dir, "mixed_language", "hdl", "toplevel.sv"),
],
toplevel="endian_swapper_mixed",
python_search=[os.path.join(example_dir, "mixed_language", "tests")],
module="test_mixed_language",
force_compile=True,
)
def test_bnn_uart():
generics = {
"C_QUARTZ_FREQ": 115200 * 4
} # 4 cycles per bit for faster simulation
run(
vhdl_sources=get_files(
pathlib.Path(__file__).parent.absolute() / ".." / "src", "*.vhd") +
get_files(
pathlib.Path(__file__).parent.absolute() / ".." / "src" /
"interface",
"*.vhd",
),
toplevel="bnn_uart",
module="test_bnn_uart",
compile_args=["--work=bnn_lib", "--std=08"],
parameters=generics,
)
def test_ttc():
tests_dir = os.path.abspath(os.path.dirname(__file__))
rtl_dir = os.path.abspath(os.path.join(tests_dir))
module = os.path.splitext(os.path.basename(__file__))[0]
vhdl_sources = [
os.path.join(rtl_dir, f"ttc.vhd"),
]
os.environ["SIM"] = "ghdl"
run(
vhdl_sources=vhdl_sources,
module=module, # name of cocotb test module
toplevel="ttc", # top level HDL
toplevel_lang="vhdl",
gui=1)
def test_find_clusters(station, num_found_clusters):
""
tests_dir = os.path.abspath(os.path.dirname(__file__))
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', 'hdl'))
module = os.path.splitext(os.path.basename(__file__))[0]
vhdl_sources = [
os.path.join(rtl_dir, f"truncate_lsb.vhd"),
os.path.join(rtl_dir, f"cluster_pkg.vhd"),
os.path.join(rtl_dir, f"bitonic_exchange.vhd"),
os.path.join(rtl_dir, f"bitonic_merge.vhd"),
os.path.join(rtl_dir, f"bitonic_sorter.vhd"),
os.path.join(rtl_dir, f"find_clusters.vhd")
]
verilog_sources = [
os.path.join(rtl_dir, f"priority.v")
]
parameters = {}
parameters['STATION'] = station
parameters['NUM_FOUND_CLUSTERS'] = num_found_clusters
if station == 2:
parameters['NUM_VFATS'] = 12
else:
parameters['NUM_VFATS'] = 24
os.environ["SIM"] = "questa"
#os.environ["SIM"] = "ghdl"
run(
verilog_sources=verilog_sources,
vhdl_sources=vhdl_sources,
module=module, # name of cocotb test module
#compile_args=["-2008"],
toplevel="find_clusters", # top level HDL
toplevel_lang="vhdl",
parameters=parameters,
gui=0
)
def test_adder_tree(is_unsigned, input_bitwidth):
generics = {
"C_INPUT_COUNT": randint(1, 16),
"C_INPUT_BITWIDTH": input_bitwidth,
"C_UNSIGNED": is_unsigned,
}
generics["C_OUTPUT_BITWIDTH"] = generics["C_INPUT_BITWIDTH"] + ceil(
log2(generics["C_INPUT_COUNT"])
)
run(
vhdl_sources=[
pathlib.Path(__file__).parent.absolute()
/ ".."
/ "src"
/ "util"
/ "adder_tree.vhd"
],
toplevel="adder_tree",
module="test_adder_tree",
compile_args=["--work=util", "--std=08"],
parameters=generics,
)
def test_sbit_monitor():
""
tests_dir = os.path.abspath(os.path.dirname(__file__))
tests_top = os.path.join(tests_dir, "../../../")
module = os.path.splitext(os.path.basename(__file__))[0]
vhdl_sources = [
os.path.join(tests_top, "common/hdl/utils/shift_reg.vhd"),
# os.path.join(tests_dir, "xpm_cdc_sync_rst.vhd"),
# os.path.join(tests_dir, "xpm_reg_pipe_bit.vhd"),
# os.path.join(tests_dir, "xpm_counter_updn.vhd"),
# os.path.join(tests_dir, "xpm_fifo_reg_bit.vhd"),
# os.path.join(tests_dir, "xpm_fifo_reg_vec.vhd"),
# os.path.join(tests_dir, "xpm_fifo_rst.vhd"),
# os.path.join(tests_dir, "xpm_cdc_gray.vhd"),
# os.path.join(tests_dir, "xpm_fifo_base.vhd"),
# os.path.join(tests_dir, "xpm_memory_base.vhd"),
# os.path.join(tests_dir, "xpm_fifo_sync.vhd"),
os.path.join(tests_dir, "sbit_monitor.vhd"),
]
parameters = {}
parameters['g_NUM_OF_OHs'] = 1
parameters['g_USE_FIFO'] = True
os.environ["SIM"] = "questa"
run(
verilog_sources=[],
vhdl_sources=vhdl_sources,
module=module,
compile_args=["-2008"],
toplevel="sbit_monitor",
toplevel_lang="vhdl",
parameters=parameters,
# sim_args = ["do cluster_packer_wave.do"],
# extra_env = {"SIM": "questa"},
gui=0)
def test_verilog_access():
run(
verilog_sources=[
os.path.join(tests_dir, "designs", "uart2bus", "verilog", file)
for file in [
"baud_gen.v",
"uart_parser.v",
"uart_rx.v",
"uart_tx.v",
"uart_top.v",
"uart2bus_top.v",
]
] + [
os.path.join(tests_dir, "designs", "uart2bus", "top",
"verilog_toplevel.sv")
],
vhdl_sources=[
os.path.join(tests_dir, "designs", "uart2bus", "vhdl",
"uart2BusTop_pkg.vhd"),
os.path.join(tests_dir, "designs", "uart2bus", "vhdl",
"baudGen.vhd"),
os.path.join(tests_dir, "designs", "uart2bus", "vhdl",
"uartParser.vhd"),
os.path.join(tests_dir, "designs", "uart2bus", "vhdl",
"uartRx.vhd"),
os.path.join(tests_dir, "designs", "uart2bus", "vhdl",
"uartTx.vhd"),
os.path.join(tests_dir, "designs", "uart2bus", "vhdl",
"uartTop.vhd"),
os.path.join(tests_dir, "designs", "uart2bus", "vhdl",
"uart2BusTop.vhd"),
],
python_search=[
os.path.join(tests_dir, "test_cases", "test_verilog_access")
],
toplevel="verilog_toplevel",
module="test_verilog_access",
)
def test_fixed_delay(width, delay):
""
tests_dir = os.path.abspath(os.path.dirname(__file__))
module = os.path.splitext(os.path.basename(__file__))[0]
vhdl_sources = [os.path.join(tests_dir, "fixed_delay.vhd")]
parameters = {}
parameters['DELAY'] = delay
parameters['WIDTH'] = width
os.environ["SIM"] = "ghdl"
run(
verilog_sources=[],
vhdl_sources=vhdl_sources,
module=module,
toplevel="fixed_delay",
toplevel_lang="vhdl",
parameters=parameters,
gui=0
)
def test_window_convolution_activation(kernel_size, stride, input_channel,
output_channel,
output_channel_bitwidth):
# Input channel bitwidth > 1 is tested at convolution level.
input_channel_bitwidth = 1
generics = {
"C_KERNEL_SIZE": kernel_size,
"C_STRIDE": stride,
"C_INPUT_CHANNEL": input_channel,
"C_INPUT_CHANNEL_BITWIDTH": input_channel_bitwidth,
"C_OUTPUT_CHANNEL": output_channel,
"C_OUTPUT_CHANNEL_BITWIDTH": output_channel_bitwidth,
"C_IMG_WIDTH": 8,
"C_IMG_HEIGHT": 8,
}
run(
vhdl_sources=get_files(
pathlib.Path(__file__).parent.absolute() / ".." / "src", "*.vhd"),
toplevel="window_convolution_activation",
module="test_window_convolution_activation",
compile_args=["--work=bnn_lib", "--std=08"],
parameters=generics,
)
def test_wrong_ops(flavor):
"""
Checks if the AXI-S/NoC is capable of throwing an errors when illegal operations are executed
Test ID: 2
Description:
Different AXI-S txn are request on the routers to check if wrong/illegal txn are not allowed to move forward in the NoC. It's expected
the NoC/AXI slave interface to refuse the txn throwing an error on the slave interface due to not supported requests. Here's a list of
all txns that are sent over this test:
- Write: Invalid memory address - out of range or not mapped
- Write: Writing on read buffer region
- Write: Invalid burst type = FIXED
- Read: Reading from write buffer region
- Read: Reading from an invalid memory region - out of range or not mapped
- Read: Just after the reset, reading from empty buffer
We don't check if the write on full buffer will thrown an error because by uArch the NoC will generate back pressure on the master if the
buffers are full and more incoming txns are being requested at the w.address channel.
"""
module = os.path.splitext(os.path.basename(__file__))[0]
SIM_BUILD = os.path.join(
noc_const.TESTS_DIR,
f"../../run_dir/sim_build_{noc_const.SIMULATOR}_{module}_{flavor}")
noc_const.EXTRA_ENV['SIM_BUILD'] = SIM_BUILD
noc_const.EXTRA_ENV['FLAVOR'] = flavor
extra_args_sim = noc_const._get_cfg_args(flavor)
run(python_search=[noc_const.TESTS_DIR],
includes=noc_const.INC_DIR,
verilog_sources=noc_const.VERILOG_SOURCES,
toplevel=noc_const.TOPLEVEL,
module=module,
sim_build=SIM_BUILD,
extra_env=noc_const.EXTRA_ENV,
extra_args=extra_args_sim)
def test_priority_encoder(width, datbits, qlt_aspect):
tests_dir = os.path.abspath(os.path.dirname(__file__))
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', 'hdl'))
module = os.path.splitext(os.path.basename(__file__))[0]
vhdl_sources = [
os.path.join(rtl_dir, f"priority_encoder.vhd"),
os.path.join(rtl_dir, f"../tb/priority_encoder_inst.vhd")
]
parameters = {}
parameters['WIDTH'] = width
parameters['DAT_BITS'] = datbits
parameters['QLT_BITS'] = int(datbits / qlt_aspect)
run(
vhdl_sources=vhdl_sources,
module=module, # name of cocotb test module
compile_args=["-2008"],
toplevel="priority_encoder_inst", # top level HDL
toplevel_lang="vhdl",
parameters=parameters,
gui=0)
def test_plus_args_test_wrong():
run(
verilog_sources=[os.path.join(hdl_dir, "plus_args.sv")], toplevel="plus_args", plus_args=["+XUSER_MODE"]
)
def test_wishbone_adapter_write():
run(
**common_run_opts,
sim_build=f"work/sim/test_wishbone_adapter_write",
testcase="wishbone_adapter_write_test",
)
def test_wishbone_adapter_read():
run(
**common_run_opts,
sim_build=f"work/sim/test_wishbone_adapter_read",
testcase="wishbone_adapter_read_test",
)
def test_wishbone_adapter_verify():
run(
**common_run_opts,
sim_build=f"work/sim/test_wishbone_adapter_verify",
testcase="verify_wishbone_adapter_test",
)
def test_dff_verilog():
run(verilog_sources=[os.path.join(tests_dir, "dff.sv")],
toplevel="dff_test",
module="dff_cocotb"
) # sources # top level HDL # name of cocotb test module
def test_dff_vhdl():
run(vhdl_sources=[os.path.join(tests_dir, "dff.vhdl")],
toplevel="dff_test_vhdl",
module="dff_cocotb",
toplevel_lang="vhdl")
