def __init__(self, dut): self.dut = dut s_count = len(dut.axi_crossbar_inst.s_axi_awvalid) m_count = len(dut.axi_crossbar_inst.m_axi_awvalid) self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.start_soon(Clock(dut.clk, 10, units="ns").start()) self.axi_master = [ AxiMaster(AxiBus.from_prefix(dut, f"s{k:02d}_axi"), dut.clk, dut.rst) for k in range(s_count) ] self.axi_ram = [ AxiRam(AxiBus.from_prefix(dut, f"m{k:02d}_axi"), dut.clk, dut.rst, size=2**16) for k in range(m_count) ] for ram in self.axi_ram: # prevent X propagation from screwing things up - "anything but X!" # (X on bid and rid can propagate X to ready/valid) ram.write_if.b_channel.bus.bid.setimmediatevalue(0) ram.read_if.r_channel.bus.rid.setimmediatevalue(0)
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.fork(Clock(dut.clk, 10, units="ns").start()) self.axi_master = AxiMaster(AxiBus.from_prefix(dut, "s_axi"), dut.clk, dut.rst) self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16)
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.fork(Clock(dut.a_clk, 8, units="ns").start()) cocotb.fork(Clock(dut.b_clk, 10, units="ns").start()) self.axi_master = [] self.axi_master.append(AxiMaster(AxiBus.from_prefix(dut, "s_axi_a"), dut.a_clk, dut.a_rst)) self.axi_master.append(AxiMaster(AxiBus.from_prefix(dut, "s_axi_b"), dut.b_clk, dut.b_rst))
def __init__(self, dut, log_name, cfg): self.dut = dut self.cfg = cfg timenow_wstamp = self._gen_log(log_name) self.log.info("------------[LOG - %s]------------",timenow_wstamp) self.log.info("SEED: %s",str(cocotb.RANDOM_SEED)) self.log.info("Log file: %s",log_name) self._print_noc_cfg() # Create the AXI Master I/Fs and connect it to the two main AXI Slave I/Fs in the top wrappers self.noc_axi_in = AxiMaster(AxiBus.from_prefix(self.dut, "noc_in"), self.dut.clk_axi, self.dut.arst_axi) self.noc_axi_out = AxiMaster(AxiBus.from_prefix(self.dut, "noc_out"), self.dut.clk_axi, self.dut.arst_axi) # Tied to zero the inputs self.dut.act_in.setimmediatevalue(0) self.dut.act_out.setimmediatevalue(0) self.dut.axi_sel_in.setimmediatevalue(0) self.dut.axi_sel_out.setimmediatevalue(0)
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.start_soon(Clock(dut.clk, 10, units="ns").start()) # AXI RAM self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16) # DMA RAM self.dma_ram = PsdpRam(PsdpRamBus.from_prefix(dut, "ram"), dut.clk, dut.rst, size=2**16) # Control self.read_desc_source = DescSource( DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst) self.read_desc_status_sink = DescStatusSink( DescStatusBus.from_prefix(dut, "m_axis_read_desc_status"), dut.clk, dut.rst) self.write_desc_source = DescSource( DescBus.from_prefix(dut, "s_axis_write_desc"), dut.clk, dut.rst) self.write_desc_status_sink = DescStatusSink( DescStatusBus.from_prefix(dut, "m_axis_write_desc_status"), dut.clk, dut.rst) dut.read_enable.setimmediatevalue(0) dut.write_enable.setimmediatevalue(0)
async def test(dut): rank2ip = BlkMemGen(AxiBus.from_prefix(dut, "m_axi"), dut.aclk, dut.areset, size=2**16) rank2ip.portb.en = 1 rank2ip.portb.addr = 4 cocotb.log.info("*** rank2ip.dout = %s" % rank2ip.portb.dout.hex()) rank2ip.write_dword(4, 0xc0caff01, byteorder='little') rank2ip.portb.addr = 4 cocotb.log.info("*** rank2ip.dout = %s" % rank2ip.portb.dout.hex()) cocotb.log.info("*** port disabled") rank2ip.portb.en = 0 rank2ip.write_dword(8, 0xcfffbbaa, byteorder='little') rank2ip.portb.addr = 8 cocotb.log.info("*** rank2ip.dout = %s" % rank2ip.portb.dout.hex()) rank2ip.portb.addr = 4 cocotb.log.info("*** rank2ip.dout = %s" % rank2ip.portb.dout.hex()) cocotb.log.info("*** port enabled") rank2ip.portb.en = 1 rank2ip.portb.addr = 8 cocotb.log.info("*** rank2ip.dout = %s" % rank2ip.portb.dout.hex()) rank2ip.portb.addr = 4 cocotb.log.info("*** rank2ip.dout = %s" % rank2ip.portb.dout.hex())
def __init__(self, dut): self.dut = dut self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.start_soon(Clock(dut.clk_250mhz, 4, units="ns").start()) # AXI self.address_space = AddressSpace() self.pool = self.address_space.create_pool(0, 0x8000_0000) self.axil_master = AxiLiteMaster( AxiLiteBus.from_prefix(dut, "s_axil_ctrl"), dut.clk_250mhz, dut.rst_250mhz) self.address_space.register_region(self.axil_master, 0x10_0000_0000) self.hw_regs = self.address_space.create_window( 0x10_0000_0000, self.axil_master.size) self.axi_slave = AxiSlave(AxiBus.from_prefix(dut, "m_axi"), dut.clk_250mhz, dut.rst_250mhz, self.address_space) self.driver = mqnic.Driver() # Ethernet cocotb.start_soon(Clock(dut.sfp0_rx_clk, 6.4, units="ns").start()) self.sfp0_source = XgmiiSource(dut.sfp0_rxd, dut.sfp0_rxc, dut.sfp0_rx_clk, dut.sfp0_rx_rst) cocotb.start_soon(Clock(dut.sfp0_tx_clk, 6.4, units="ns").start()) self.sfp0_sink = XgmiiSink(dut.sfp0_txd, dut.sfp0_txc, dut.sfp0_tx_clk, dut.sfp0_tx_rst) cocotb.start_soon(Clock(dut.sfp1_rx_clk, 6.4, units="ns").start()) self.sfp1_source = XgmiiSource(dut.sfp1_rxd, dut.sfp1_rxc, dut.sfp1_rx_clk, dut.sfp1_rx_rst) cocotb.start_soon(Clock(dut.sfp1_tx_clk, 6.4, units="ns").start()) self.sfp1_sink = XgmiiSink(dut.sfp1_txd, dut.sfp1_txc, dut.sfp1_tx_clk, dut.sfp1_tx_rst) cocotb.start_soon(Clock(dut.sfp_drp_clk, 8, units="ns").start()) dut.sfp_drp_rst.setimmediatevalue(0) dut.sfp_drp_do.setimmediatevalue(0) dut.sfp_drp_rdy.setimmediatevalue(0) dut.sfp0_rx_error_count.setimmediatevalue(0) dut.sfp1_rx_error_count.setimmediatevalue(0) dut.btnu.setimmediatevalue(0) dut.btnl.setimmediatevalue(0) dut.btnd.setimmediatevalue(0) dut.btnr.setimmediatevalue(0) dut.btnc.setimmediatevalue(0) dut.sw.setimmediatevalue(0) dut.i2c_scl_i.setimmediatevalue(1) dut.i2c_sda_i.setimmediatevalue(1) self.loopback_enable = False cocotb.start_soon(self._run_loopback())
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) # PCIe self.rc = RootComplex() self.dev = UltraScalePlusPcieDevice( # configuration options pcie_generation=3, # pcie_link_width=2, # user_clk_frequency=250e6, alignment="dword", cq_cc_straddle=False, rq_rc_straddle=False, rc_4tlp_straddle=False, enable_pf1=False, enable_client_tag=True, enable_extended_tag=False, enable_parity=False, enable_rx_msg_interface=False, enable_sriov=False, enable_extended_configuration=False, enable_pf0_msi=True, enable_pf1_msi=False, # signals user_clk=dut.clk, user_reset=dut.rst, cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), cfg_max_payload=dut.max_payload_size, ) self.dev.log.setLevel(logging.DEBUG) self.dev.functions[0].configure_bar(0, 16*1024*1024) self.dev.functions[0].configure_bar(1, 16*1024, io=True) self.rc.make_port().connect(self.dev) # AXI self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16) dut.completer_id.setimmediatevalue(0) dut.completer_id_enable.setimmediatevalue(0) # monitor error outputs self.status_error_cor_asserted = False self.status_error_uncor_asserted = False cocotb.fork(self._run_monitor_status_error_cor()) cocotb.fork(self._run_monitor_status_error_uncor())
def __init__(self, dut): self.dut = dut s_count = len(dut.axi_interconnect_inst.s_axi_awvalid) m_count = len(dut.axi_interconnect_inst.m_axi_awvalid) self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.fork(Clock(dut.clk, 10, units="ns").start()) self.axi_master = [ AxiMaster(AxiBus.from_prefix(dut, f"s{k:02d}_axi"), dut.clk, dut.rst) for k in range(s_count) ] self.axi_ram = [ AxiRam(AxiBus.from_prefix(dut, f"m{k:02d}_axi"), dut.clk, dut.rst, size=2**16) for k in range(m_count) ]
def __init__(self, dut): self.dut = dut s_count = int(os.getenv("PARAM_S_COUNT")) m_count = int(os.getenv("PARAM_M_COUNT")) self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.fork(Clock(dut.clk, 10, units="ns").start()) self.axi_master = [ AxiMaster(AxiBus.from_prefix(dut, f"s{k:02d}_axi"), dut.clk, dut.rst) for k in range(s_count) ] self.axi_ram = [ AxiRam(AxiBus.from_prefix(dut, f"m{k:02d}_axi"), dut.clk, dut.rst, size=2**16) for k in range(m_count) ]
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.fork(Clock(dut.clk, 10, units="ns").start()) # control interface self.desc_source = DescSource(DescBus.from_prefix(dut, "s_axis_desc"), dut.clk, dut.rst) self.desc_status_sink = DescStatusSink(DescStatusBus.from_prefix(dut, "m_axis_desc_status"), dut.clk, dut.rst) # AXI interface self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16) dut.enable.setimmediatevalue(0)
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.fork(Clock(dut.clk, 10, units="ns").start()) # read interface self.read_desc_source = DescSource( DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst) self.read_desc_status_sink = DescStatusSink( DescStatusBus.from_prefix(dut, "m_axis_read_desc_status"), dut.clk, dut.rst) self.read_data_sink = AxiStreamSink( AxiStreamBus.from_prefix(dut, "m_axis_read_data"), dut.clk, dut.rst) # write interface self.write_desc_source = DescSource( DescBus.from_prefix(dut, "s_axis_write_desc"), dut.clk, dut.rst) self.write_desc_status_sink = DescStatusSink( DescStatusBus.from_prefix(dut, "m_axis_write_desc_status"), dut.clk, dut.rst) self.write_data_source = AxiStreamSource( AxiStreamBus.from_prefix(dut, "s_axis_write_data"), dut.clk, dut.rst) # AXI interface self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16) dut.read_enable.setimmediatevalue(0) dut.write_enable.setimmediatevalue(0) dut.write_abort.setimmediatevalue(0)
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start()) # PCIe self.rc = RootComplex() self.dev = PcieIfDevice( clk=dut.clk, rst=dut.rst, rx_req_tlp_bus=PcieIfRxBus.from_prefix(dut, "rx_req_tlp"), tx_cpl_tlp_bus=PcieIfTxBus.from_prefix(dut, "tx_cpl_tlp"), cfg_max_payload=dut.max_payload_size, ) self.dev.log.setLevel(logging.DEBUG) self.dev.functions[0].configure_bar(0, 16*1024*1024) self.dev.functions[0].configure_bar(1, 16*1024, io=True) self.rc.make_port().connect(self.dev) # AXI self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16) # monitor error outputs self.status_error_cor_asserted = False self.status_error_uncor_asserted = False cocotb.start_soon(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) # PCIe self.rc = RootComplex() self.dev = UltraScalePlusPcieDevice( # configuration options pcie_generation=3, # pcie_link_width=2, # user_clk_frequency=250e6, alignment="dword", cq_cc_straddle=False, rq_rc_straddle=False, rc_4tlp_straddle=False, enable_pf1=False, enable_client_tag=True, enable_extended_tag=False, enable_parity=False, enable_rx_msg_interface=False, enable_sriov=False, enable_extended_configuration=False, enable_pf0_msi=True, enable_pf1_msi=False, # signals user_clk=dut.clk, user_reset=dut.rst, rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), cfg_max_payload=dut.max_payload_size, cfg_max_read_req=dut.max_read_request_size, cfg_fc_sel=0b100, cfg_fc_ph=dut.pcie_tx_fc_ph_av, cfg_fc_pd=dut.pcie_tx_fc_pd_av, cfg_fc_nph=dut.pcie_tx_fc_nph_av, ) self.dev.log.setLevel(logging.DEBUG) self.rc.make_port().connect(self.dev) # AXI self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16) # Control self.read_desc_source = DescSource( DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst) self.read_desc_status_sink = DescStatusSink( DescStatusBus.from_prefix(dut, "m_axis_read_desc_status"), dut.clk, dut.rst) self.write_desc_source = DescSource( DescBus.from_prefix(dut, "s_axis_write_desc"), dut.clk, dut.rst) self.write_desc_status_sink = DescStatusSink( DescStatusBus.from_prefix(dut, "m_axis_write_desc_status"), dut.clk, dut.rst) dut.requester_id.setimmediatevalue(0) dut.requester_id_enable.setimmediatevalue(0) dut.ext_tag_enable.setimmediatevalue(0) dut.read_enable.setimmediatevalue(0) dut.write_enable.setimmediatevalue(0) # monitor error outputs self.status_error_cor_asserted = False self.status_error_uncor_asserted = False cocotb.start_soon(self._run_monitor_status_error_cor()) cocotb.start_soon(self._run_monitor_status_error_uncor())
def __init__(self, dut): self.dut = dut self.log = SimLog("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.start_soon(Clock(dut.clk, 4, units="ns").start()) # AXI self.address_space = AddressSpace() self.pool = self.address_space.create_pool(0, 0x8000_0000) self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil_ctrl"), dut.clk, dut.rst) self.address_space.register_region(self.axil_master, 0x10_0000_0000) self.hw_regs = self.address_space.create_window(0x10_0000_0000, self.axil_master.size) self.axi_slave = AxiSlave(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, self.address_space) self.driver = mqnic.Driver() # Ethernet self.port_mac = [] eth_int_if_width = len(dut.core_inst.iface[0].port[0].rx_async_fifo_inst.m_axis_tdata) eth_clock_period = 6.4 eth_speed = 10e9 if eth_int_if_width == 64: # 10G eth_clock_period = 6.4 eth_speed = 10e9 elif eth_int_if_width == 128: # 25G eth_clock_period = 2.56 eth_speed = 25e9 elif eth_int_if_width == 512: # 100G eth_clock_period = 3.102 eth_speed = 100e9 for iface in dut.core_inst.iface: for port in iface.port: cocotb.start_soon(Clock(port.port_rx_clk, eth_clock_period, units="ns").start()) cocotb.start_soon(Clock(port.port_tx_clk, eth_clock_period, units="ns").start()) port.port_rx_rst.setimmediatevalue(0) port.port_tx_rst.setimmediatevalue(0) mac = EthMac( tx_clk=port.port_tx_clk, tx_rst=port.port_tx_rst, tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"), tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts, tx_ptp_ts=port.ptp.axis_tx_ptp_ts, tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag, tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid, rx_clk=port.port_rx_clk, rx_rst=port.port_rx_rst, rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"), rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts, ifg=12, speed=eth_speed ) self.port_mac.append(mac) dut.ctrl_reg_wr_wait.setimmediatevalue(0) dut.ctrl_reg_wr_ack.setimmediatevalue(0) dut.ctrl_reg_rd_data.setimmediatevalue(0) dut.ctrl_reg_rd_wait.setimmediatevalue(0) dut.ctrl_reg_rd_ack.setimmediatevalue(0) dut.ptp_sample_clk.setimmediatevalue(0) dut.s_axis_stat_tdata.setimmediatevalue(0) dut.s_axis_stat_tid.setimmediatevalue(0) dut.s_axis_stat_tvalid.setimmediatevalue(0) self.loopback_enable = False cocotb.start_soon(self._run_loopback())