def genCmd(self): if self.closeIt or not self.cmdRandomizer.get(): return None trans = Transaction() if not self.burstRandomizer.get(): trans.address = randBits(9+2+2) else: trans.address = self.lastAddr + 1 trans.address = trans.address & ((1 << 13)-1) trans.write = self.writeRandomizer.get() and self.writeRandomizer.get() trans.mask = randBits(2) trans.data = randBits(16) trans.context = randBits(8) self.lastAddr = trans.address if trans.write == 0: rsp = Transaction() rsp.data = self.ram[trans.address*2] + (self.ram[trans.address*2+1] << 8) rsp.context = trans.context self.scorboard.refPush(rsp) if rsp.data != 0: self.nonZeroRspCounter += 1 if self.nonZeroRspCounter % 50 == 0: print("self.nonZeroRspCounter=" + str(self.nonZeroRspCounter)) else: for i in xrange(2): if (trans.mask >> i) & 1 == 1: self.ram[trans.address * 2 + i] = (trans.data >> (i*8)) & 0xFF return trans
def genCmdB(self): if self.getPhase() != PHASE_SIM: return None if self.memInitDone and random.random() < 0.5: trans = Transaction() trans.itself = randBits(32) return trans
def test1(dut): random.seed(0) for i in range(100): randValue = randBits(5) dut.io_value <= randValue yield Timer(1000) assertEquals( dut.io_isPrime, is_prime(randValue), "fail with " + str(randValue) + " which should have produce a isPrime=" + str(is_prime(randValue)))
def genReadCmd(self): if self.closeIt: return None if not self.readCmdIdleRand.get(): return None idOffset = randBits(2) trans = Transaction() trans.addr = self.genRandomReadAddress() trans.hid = self.idBase * 4 + idOffset #Each master can use 4 id trans.region = randBits(4) trans.len = randBits(4) trans.size = randBits(3) trans.burst = randBits(2) trans.lock = randBits(1) trans.cache = randBits(4) trans.qos = randBits(4) trans.prot = randBits(3) return trans
def genReadCmd(self): if self.closeIt: return None if not self.readCmdIdleRand.get(): return None idOffset = randBits(2) trans = Transaction() trans.addr = self.genRandomReadAddress() trans.hid = self.idBase*4 + idOffset #Each master can use 4 id trans.region = randBits(4) trans.len = randBits(4) trans.size = randBits(3) trans.burst = randBits(2) trans.lock = randBits(1) trans.cache = randBits(4) trans.qos = randBits(4) trans.prot = randBits(3) return trans
def genCmd(self): if self.closeIt or not self.cmdRandomizer.get(): return None trans = Transaction() if not self.burstRandomizer.get(): trans.address = randBits(9 + 2 + 2) else: trans.address = self.lastAddr + 1 trans.address = trans.address & ((1 << 13) - 1) trans.write = self.writeRandomizer.get() and self.writeRandomizer.get() trans.mask = randBits(2) trans.data = randBits(16) trans.context = randBits(8) self.lastAddr = trans.address if trans.write == 0: rsp = Transaction() rsp.data = self.ram[trans.address * 2] + (self.ram[trans.address * 2 + 1] << 8) rsp.context = trans.context self.scorboard.refPush(rsp) if rsp.data != 0: self.nonZeroRspCounter += 1 if self.nonZeroRspCounter % 50 == 0: print(("self.nonZeroRspCounter=" + str(self.nonZeroRspCounter))) else: for i in range(2): if (trans.mask >> i) & 1 == 1: self.ram[trans.address * 2 + i] = (trans.data >> (i * 8)) & 0xFF return trans
def test1(dut): random.seed(0) outputs = [Bundle(dut, "io_outputs_" + str(i)) for i in range(4)] mappings = [[0x0000, 0x1000], [0x1000, 0x1000], [0x4000, 0x2000], [0x6000, 0x3000]] for i in range(100): dut.io_input_PADDR <= randBits(16) dut.io_input_PSEL <= randBits(1) dut.io_input_PENABLE <= randBits(1) dut.io_input_PWRITE <= randBits(1) dut.io_input_PWDATA <= randBits(32) for output in outputs: output.PREADY <= randBits(1) output.PRDATA <= randBits(32) output.PSLVERROR <= randBits(1) yield Timer(1000) select = None for index, mapping in enumerate(mappings): if (int(dut.io_input_PADDR) >= mapping[0] and int(dut.io_input_PADDR) < mapping[0] + mapping[1]): select = index for index, output in enumerate(outputs): assertEquals(output.PADDR, dut.io_input_PADDR, "fail on output PADDR " + str(index)) assertEquals(output.PWRITE, dut.io_input_PWRITE, "fail on output PWRITE " + str(index)) if select == index: assertEquals(output.PENABLE, dut.io_input_PENABLE, "fail on output PENABLE " + str(index)) assertEquals(output.PSEL, dut.io_input_PSEL, "fail on output PSEL " + str(index)) else: assertEquals(output.PSEL, 0, "fail on output PSEL " + str(index)) if select == index: assertEquals(output.PREADY, dut.io_input_PREADY, "fail on input PREADY") assertEquals(output.PRDATA, dut.io_input_PRDATA, "fail on input PRDATA") assertEquals(output.PSLVERROR, dut.io_input_PSLVERROR, "fail on input PSLVERROR")
def genWrite(self): idOffset = randBits(2) writeCmd = Transaction() writeCmd.addr = self.genRandomWriteAddress() writeCmd.hid = self.idBase + idOffset #Each master can use 4 id writeCmd.region = randBits(4) writeCmd.len = randBits(4) writeCmd.size = randBits(3) writeCmd.burst = randBits(2) writeCmd.lock = randBits(1) writeCmd.cache = randBits(4) writeCmd.qos = randBits(4) writeCmd.prot = randBits(3) self.writeCmdQueue.put(writeCmd) for i in xrange(writeCmd.len + 1): writeData = Transaction() writeData.data = writeCmd.addr + i writeData.strb = (writeCmd.addr + i) & 0xF writeData.last = 1 if i == writeCmd.len else 0 self.writeDataQueue.put(writeData)
def genWrite(self): idOffset = randBits(2) writeCmd = Transaction() writeCmd.addr = self.genRandomWriteAddress() writeCmd.hid = self.idBase + idOffset #Each master can use 4 id writeCmd.region = randBits(4) writeCmd.len = randBits(4) writeCmd.size = randBits(3) writeCmd.burst = randBits(2) writeCmd.lock = randBits(1) writeCmd.cache = randBits(4) writeCmd.qos = randBits(4) writeCmd.prot = randBits(3) self.writeCmdQueue.put(writeCmd) for i in range(writeCmd.len + 1): writeData = Transaction() writeData.data = writeCmd.addr + i writeData.strb = (writeCmd.addr + i) & 0xF writeData.last = 1 if i == writeCmd.len else 0 self.writeDataQueue.put(writeData)
def genReadCmd(self): if self.doFinish: return None if not self.readCmdIdleRand.get(): return None idOffset = randBits(2) trans = Transaction() trans.addr = self.genRandomAddress() if random.random() < 0.1: # Random assertion of decoding error trans.addr = 1 << 12 trans.hid = self.hid * 4 + idOffset #Each master can use 4 id trans.region = randBits(4) trans.len = randBits(4) trans.size = randBits(3) trans.burst = randBits(2) trans.lock = randBits(1) trans.cache = randBits(4) trans.qos = randBits(4) trans.prot = randBits(3) trans.progress = 0 self.readMonitorQueues[idOffset].put(trans) # print("Master START %d %x" % (trans.hid, trans.addr)) return trans
def test1(dut): random.seed(0) cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset)) cocotb.fork(simulationSpeedPrinter(dut.clk)) cocotb.fork(SimulationTimeout(1000 * 8000)) phaseManager = PhaseManager() phaseManager.setWaitTasksEndTime(1000 * 200) driver = DriverAgent("driver", phaseManager, dut) monitor = MonitorAgent("monitor", phaseManager, dut) for i in range(1 << 8): dut.io_memWrite_valid <= 1 dut.io_memWrite_payload_address <= i dut.io_memWrite_payload_data <= randBits(32) yield RisingEdge(dut.clk) dut.io_memWrite_valid <= 0 driver.memInitDone = True yield phaseManager.run()
def genRandomWriteAddress(self): if random.random() < 0.1: # Random assertion of decoding error return 1 << 14 return randBits(12) + random.choice([0,1,3])*0x1000
def genNewCmd(): length = random.randint(1, (lengthMax // lengthMin)) * lengthMin if self.doWriteInit: address = self.writeInitAddress self.writeInitAddress += length else: address = (random.randint( 0, addressRange // lengthMaxAll // len(self.bmbs) - 1) * len(self.bmbs) + bmbId) * lengthMaxAll write = random.random() < 0.5 or self.doWriteInit beatCount = (length + bytePerBeat - 1) // bytePerBeat context = randBits(len(bmb.cmd.payload.fragment_context)) print("* " + str(context) + " " + str(length) + " " + str(bytePerBeat) + " " + str(beatCount)) source = 0 if not write: cmd = Transaction() cmd.last = True cmd.fragment_source = source cmd.fragment_opcode = 0 cmd.fragment_address = address cmd.fragment_length = length - 1 cmd.fragment_data = randBits(len( bmb.cmd.payload.fragment_data)) cmd.fragment_mask = randBits(len( bmb.cmd.payload.fragment_mask)) cmd.fragment_context = context cmdTasks.put(cmd) # print("*** R" + str(bmbId) + " " + hex(cmd.fragment_context)) for beat in range(beatCount): rsp = Transaction() rsp.last = beat == beatCount - 1 rsp.fragment_source = source rsp.fragment_context = context rsp.fragment_opcode = 0 rsp.fragment_data = self.ram.read( address + beat * bytePerBeat, bytePerBeat) # print("*** " + str(bmbId) + " " + hex(rsp.fragment_context)) rspTasks.put(rsp) else: rsp = Transaction() rsp.last = True rsp.fragment_source = source rsp.fragment_context = context rsp.fragment_opcode = 0 rsp.fragment_data = None rspTasks.put(rsp) # print("*** " + str(bmbId) + " " + hex(rsp.fragment_context)) for beat in range(beatCount): cmd = Transaction() cmd.last = beat == beatCount - 1 cmd.fragment_opcode = 1 cmd.fragment_address = address cmd.fragment_length = length - 1 cmd.fragment_source = source cmd.fragment_context = context cmd.fragment_data = randBits( len(bmb.cmd.payload.fragment_data)) if self.doWriteInit: cmd.fragment_mask = ( 1 << len(bmb.cmd.payload.fragment_mask)) - 1 else: cmd.fragment_mask = randBits( len(bmb.cmd.payload.fragment_mask)) cmdTasks.put(cmd) # print("*** W " + str(bmbId) + " " + hex(cmd.fragment_context) + " " + str(length)) self.ram.write(address + beat * bytePerBeat, bytePerBeat, cmd.fragment_data, cmd.fragment_mask) if self.writeInitAddress >= addressRange: self.writeInitAddress = False
def genRandomeAddress(self): return randBits(self.addressWidth)
import random from Queue import Queue import cocotb from cocotb import fork, log from cocotb.decorators import coroutine from cocotb.triggers import RisingEdge, FallingEdge, Event, Timer from cocotblib.Flow import Flow from cocotblib.Stream import Stream, StreamDriverMaster, Transaction from cocotblib.misc import assertEquals, randInt, ClockDomainAsyncReset, simulationSpeedPrinter, clockedWaitTrue, Bundle, randBits, randBool from spinal.I2CTester2.lib.misc import OpenDrainInterconnect, I2cSoftMaster cmdToData = [randBits(8) for x in xrange(256)] crapyConflictCounter = 0 normalConflictCounter = 0 normalTransactionCounter = 0 @coroutine def clockedFuncWaitTrue(clk, that): while True: yield RisingEdge(clk) if that() == True: break @coroutine def SlaveThread(scl, sda, clk, baudPeriod): global crapyConflictCounter
def testDESCore(dut): dut.log.info("Cocotb test DES Core") from cocotblib.misc import cocotbXHack cocotbXHack() helperDES = DESCoreStdHelper(dut) clockDomain = ClockDomain(helperDES.io.clk, 200, helperDES.io.resetn, RESET_ACTIVE_LEVEL.LOW) # Start clock cocotb.fork(clockDomain.start()) # Init IO and wait the end of the reset helperDES.io.init() yield clockDomain.event_endReset.wait() # start monitoring the Valid signal helperDES.io.rsp.startMonitoringValid(helperDES.io.clk) for _ in range(0, 5): # Vector test ... #key = 0xAABB09182736CCDD #data = 0x123456ABCD132536 #data = 0xC0B7A8D05F3A829C # Gen random value key = randBits(64) data = randBits(64) # Encrpytion helperDES.io.cmd.valid <= 1 helperDES.io.cmd.payload.key <= key helperDES.io.cmd.payload.block <= data helperDES.io.cmd.payload.enc <= 1 # do an encryption # Wait the end of the process and read the result yield helperDES.io.rsp.event_valid.wait() rtlEncryptedBlock = int(helperDES.io.rsp.event_valid.data.block) #print("RTL encrypted", hex(rtlEncryptedBlock)) helperDES.io.cmd.valid <= 0 yield RisingEdge(helperDES.io.clk) # Encrpytion helperDES.io.cmd.valid <= 1 helperDES.io.cmd.payload.key <= key helperDES.io.cmd.payload.block <= rtlEncryptedBlock helperDES.io.cmd.payload.enc <= 0 # do a decryption # Wait the end of the process and read the result yield helperDES.io.rsp.event_valid.wait() rtlDecryptedBlock = int(helperDES.io.rsp.event_valid.data.block) #print("RTL decrypted", hex(rtlDecryptedBlock)) helperDES.io.cmd.valid <= 0 yield RisingEdge(helperDES.io.clk) # Encrypted data with the model k = des(int_2_String(key), CBC, "\0\0\0\0\0\0\0\0", pad=None, padmode=PAD_PKCS5) refEncryptedOutput = (k.encrypt(int_2_String(data))).encode('hex')[:16] # print("Ref encrypted ", refEncryptedOutput) # compare result assertEquals(int(refEncryptedOutput, 16), rtlEncryptedBlock, "Encryption data wrong ") assertEquals(rtlDecryptedBlock, data, "Decryption data wrong ") dut.log.info("Cocotb end test DES Core")
def run(self): global crapyConflictCounter global normalConflictCounter global normalTransactionCounter yield Timer(self.baudPeriod * 10) while crapyConflictCounter < 2 or normalConflictCounter < 3 or normalTransactionCounter < 40: while True: colision = False cmd = Transaction() cmd.mode = 0 cmd.data = randBool() self.cmdQueue.append(cmd) address = randBits(8) | 2 for bitId in range(8): cmd = Transaction() cmd.mode = 1 cmd.data = (address >> (7 - bitId)) & 1 self.cmdQueue.append(cmd) yield clockedWaitTrue(self.clk,self.rsp.valid) if self.rsp.payload.data != cmd.data: assert bitId == 6 colision = True cmd = Transaction() cmd.mode = 3 #DROP cmd.data = randBool() self.cmdQueue.append(cmd) break if colision: continue for bitId in range(8): cmd = Transaction() cmd.mode = 1 cmd.data = True self.cmdQueue.append(cmd) yield clockedWaitTrue(self.clk,self.rsp.valid) assert self.rsp.payload.data == ((cmdToData[address] >> (7-bitId)) & 1) if random.random() < 0.75: cmd = Transaction() cmd.mode = 2 cmd.data = randBool() self.cmdQueue.append(cmd) if random.random() < 0.75: #no other master frame if random.random() < 0.5: # With inter frame delay yield Timer(randInt(0,self.baudPeriod*20)) else: @coroutine def anotherFrameEmiter(): yield self.softMaster.sendStart() for i in range(5): yield self.softMaster.sendBit(randBool()) yield self.softMaster.sendStop() yield Timer(randInt(self.baudPeriod * 4, self.baudPeriod * 10)) fork(anotherFrameEmiter()) yield Timer(randInt(self.baudPeriod * 1, self.baudPeriod * 14)) normalTransactionCounter += 1 break while self.cmdQueue: yield Timer(self.baudPeriod * 10)
import random from Queue import Queue import cocotb from cocotb import fork, log from cocotb.decorators import coroutine from cocotb.triggers import RisingEdge, FallingEdge, Event, Timer from cocotblib.Flow import Flow from cocotblib.Stream import Stream, StreamDriverMaster, Transaction from cocotblib.misc import assertEquals, randInt, ClockDomainAsyncReset, simulationSpeedPrinter, clockedWaitTrue, Bundle, randBits, randBool from spinal.I2CTester2.lib.misc import OpenDrainInterconnect, I2cSoftMaster cmdToData = [randBits(8) for x in xrange(256)] crapyConflictCounter = 0 normalConflictCounter = 0 normalTransactionCounter = 0 @coroutine def clockedFuncWaitTrue(clk,that): while True: yield RisingEdge(clk) if that() == True: break @coroutine def SlaveThread(scl,sda,clk,baudPeriod): global crapyConflictCounter global normalConflictCounter
def bundleAGen(): trans = Transaction() trans.a = randBits(8) trans.b = randBits(1) return trans
def genNewCmd(self): cmd = Transaction() cmd.hid = randBits(self.idWidth) # Each master can use 4 id cmd.region = randBits(4) cmd.len = randBits(4) cmd.size = random.randint(0, self.maxDataBytes) cmd.burst = random.randint(0, 2) if cmd.burst == 2: cmd.len = random.choice([2, 4, 8, 16]) - 1 else: cmd.len = randBits(4) + (16 if random.random() < 0.1 else 0) + (32 if random.random() < 0.02 else 0) cmd.lock = randBits(1) cmd.cache = randBits(4) cmd.qos = randBits(4) cmd.prot = randBits(3) byteCount = (1 << cmd.size) * (cmd.len + 1) while (True): cmd.addr = self.genRandomeAddress() & ~((1 << cmd.size) - 1) if cmd.burst == 1: if cmd.addr + byteCount >= (1 << self.addressWidth): continue if cmd.burst == 0: start = cmd.addr end = start + cmd.size if cmd.burst == 1: start = cmd.addr end = start + byteCount if cmd.burst == 2: start = cmd.addr & ~(byteCount - 1) end = start + byteCount if self.isAddressRangeBusy(start, end): continue break if self.readWriteRand.get(): cmd.write = 1 beatAddr = cmd.addr for i in range(cmd.len + 1): dataTrans = Transaction() dataTrans.data = randBits(self.dataWidth) dataTrans.strb = randBits(self.maxDataBytes) dataTrans.last = 1 if cmd.len == i else 0 self.writeTasks.put(dataTrans) for s in range(self.maxDataBytes): if (dataTrans.strb >> s) & 1 == 1: self.ram[(beatAddr & ~(self.maxDataBytes - 1)) + s] = (dataTrans.data >> (s * 8)) & 0xFF beatAddr = Axi4AddrIncr(beatAddr, cmd.burst, cmd.len, cmd.size) writeRsp = Transaction() writeRsp.resp = 0 writeRsp.hid = cmd.hid self.reservedAddresses[writeRsp] = [start, end] self.writeRspScoreboard.refPush(writeRsp, writeRsp.hid) else: cmd.write = 0 beatAddr = cmd.addr for s in range(cmd.len + 1): readRsp = Transaction() addrBase = beatAddr & ~(self.maxDataBytes - 1) readRsp.data = 0 for i in range(self.maxDataBytes): readRsp.data |= self.ram[addrBase + i] << (i * 8) readRsp.resp = 0 readRsp.last = 1 if cmd.len == s else 0 readRsp.hid = cmd.hid if readRsp.last == 1: self.reservedAddresses[readRsp] = [start, end] self.readRspScoreboard.refPush(readRsp, readRsp.hid) beatAddr = Axi4AddrIncr(beatAddr, cmd.burst, cmd.len, cmd.size) self.cmdTasks.put(cmd)
def genRandomAddress(self): while True: value = randBits(12) if (value >> 10) != self.hid and ((value >> 8) & 0x3) == self.hid: return value
def genRandomWriteAddress(self): if random.random() < 0.1: # Random assertion of decoding error return 1 << 14 return randBits(12) + random.choice([0, 1, 3]) * 0x1000
def run(self): global crapyConflictCounter global normalConflictCounter global normalTransactionCounter yield Timer(self.baudPeriod * 10) while crapyConflictCounter < 2 or normalConflictCounter < 3 or normalTransactionCounter < 40: while True: colision = False cmd = Transaction() cmd.mode = 0 cmd.data = randBool() self.cmdQueue.append(cmd) address = randBits(8) | 2 for bitId in range(8): cmd = Transaction() cmd.mode = 1 cmd.data = (address >> (7 - bitId)) & 1 self.cmdQueue.append(cmd) yield clockedWaitTrue(self.clk, self.rsp.valid) if self.rsp.payload.data != cmd.data: assert bitId == 6 colision = True cmd = Transaction() cmd.mode = 3 #DROP cmd.data = randBool() self.cmdQueue.append(cmd) break if colision: continue for bitId in range(8): cmd = Transaction() cmd.mode = 1 cmd.data = True self.cmdQueue.append(cmd) yield clockedWaitTrue(self.clk, self.rsp.valid) assert self.rsp.payload.data == ((cmdToData[address] >> (7 - bitId)) & 1) if random.random() < 0.75: cmd = Transaction() cmd.mode = 2 cmd.data = randBool() self.cmdQueue.append(cmd) if random.random() < 0.75: #no other master frame if random.random() < 0.5: # With inter frame delay yield Timer(randInt(0, self.baudPeriod * 20)) else: @coroutine def anotherFrameEmiter(): yield self.softMaster.sendStart() for i in range(5): yield self.softMaster.sendBit(randBool()) yield self.softMaster.sendStop() yield Timer( randInt(self.baudPeriod * 4, self.baudPeriod * 10)) fork(anotherFrameEmiter()) yield Timer( randInt(self.baudPeriod * 1, self.baudPeriod * 14)) normalTransactionCounter += 1 break while self.cmdQueue: yield Timer(self.baudPeriod * 10)
def genWrite(self): idOffset = randBits(2) writeCmd = Transaction() writeCmd.addr = self.genRandomAddress() if random.random() < 0.1: # Random assertion of decoding error writeCmd.addr = 1 << 12 writeCmd.hid = self.hid * 4 + idOffset #Each master can use 4 id writeCmd.region = randBits(4) writeCmd.len = randBits(4) writeCmd.size = randBits(3) writeCmd.burst = randBits(2) writeCmd.lock = randBits(1) writeCmd.cache = randBits(4) writeCmd.qos = randBits(4) writeCmd.prot = randBits(3) self.writeCmdQueue.put(writeCmd) writeCmd.linkedDatas = [] for i in range(writeCmd.len + 1): writeData = Transaction() writeData.data = randBits(32) writeData.strb = randBits(4) writeData.last = 1 if i == writeCmd.len else 0 self.writeDataQueue.put(writeData) writeCmd.linkedDatas.append(writeData) self.idToWrites[writeCmd.hid].append(writeCmd)