def test1(dut):
dut.log.info("Cocotb test boot")
def assertGpio(value):
assert (str(dut.cmd_read).lower() == value)
assert (str(dut.bus_gpio).lower() == value)
assert (str(dut.bus_cmd_read).lower() == value)
assert (str(dut.buscpy_gpio_readed).lower() == value)
@cocotb.coroutine
def stim(drivers):
for i in xrange(100):
for toidle in drivers:
randSignal(toidle.write)
toidle.writeenable <= 0
driver = random.choice(drivers)
randSignal(driver.writeenable)
yield Timer(10)
if driver.writeenable == False:
assertGpio("z")
elif driver.write == False:
assertGpio("0")
else:
assertGpio("1")
drivers = [
Bundle(dut, "bus_cmd"),
Bundle(dut, "cmd"),
Bundle(dut, "cmdbb")
]
yield stim(drivers)
dut.log.info("Cocotb test done")
def __init__(self, dut, name):
self.valid = dut.__getattr__(name + "_valid")
self.ready = dut.__getattr__(name + "_ready")
self.payload = Bundle(dut, name + "_payload")
# Event
self.event_ready = Event()
self.event_valid = Event()
def jtagTest(dut):
dut.log.info("Cocotb test boot")
random.seed(0)
cocotb.fork(simulationSpeedPrinter(dut.io_axiClk))
yield loadIHex(dut,"e:/vm/share/pinsec_test.hex",dut.io_axiClk,dut.io_asyncReset)
cocotb.fork(ClockDomainAsyncReset(dut.io_axiClk, dut.io_asyncReset))
jtag = JtagMaster(Bundle(dut,"io_jtag"),4000,4)
yield Timer(1000*50)
yield jtag.goToIdle()
yield Timer(1000*8)
# Check rom write/read via jtag
yield jtagBridgeWrite(jtag,0x3000,0x11223344,4)
yield jtagBridgeWrite(jtag,0x3002,0x00550000,1)
yield jtagBridgeReadAssert(jtag,0x3000,4,0x11553344)
yield jtagBridgeReadAssert(jtag,0x3002,2,0x1155)
# Check RISCV APB debug module via jtag
yield jtagBridgeWrite(jtag,0xF00F0200,1 << 17,4) #halt CPU
yield jtagBridgeReadAssert(jtag,0xF00F0200,4,(1 << 1),0x0F)
yield jtagBridgeWrite(jtag,0xF00F0008,0x99887766,4) #write R2
yield jtagBridgeReadAssert(jtag,0xF00F0008,4,0x99887766)
yield Timer(1000*500)
dut.log.info("Cocotb test done")
def __init__(self, dut, name):
# interface
self.valid = dut.__getattr__(name + "_valid")
self.payload = Bundle(dut, name + "_payload")
# Event
self.event_valid = Event()
def test1(dut):
dut.log.info("Cocotb test boot")
random.seed(0)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
cocotb.fork(simulationSpeedPrinter(dut.clk))
drivers = []
checkers = []
for i in range(3):
readQueue = Queue()
ahb = Bundle(dut, "ahbMasters_" + str(i))
drivers.append(
AhbLite3MasterDriver(
ahb, AhbLite3TraficGeneratorWithMemory(12, 32, readQueue, i),
dut.clk, dut.reset))
checkers.append(
AhbLite3MasterReadChecker(ahb, readQueue, dut.clk, dut.reset))
# AhbLite3MasterIdle(Bundle(dut, "ahbMasters_1"))
# AhbLite3MasterIdle(Bundle(dut, "ahbMasters_2"))
AhbLite3SlaveMemory(Bundle(dut, "ahbSlaves_0"), 0x000, 0x400, dut.clk,
dut.reset)
AhbLite3SlaveMemory(Bundle(dut, "ahbSlaves_1"), 0x400, 0x400, dut.clk,
dut.reset)
AhbLite3SlaveMemory(Bundle(dut, "ahbSlaves_2"), 0x800, 0x400, dut.clk,
dut.reset)
AhbLite3SlaveMemory(Bundle(dut, "ahbSlaves_3"), 0xC00, 0x400, dut.clk,
dut.reset)
while True:
yield RisingEdge(dut.clk)
done = True
for checker in checkers:
if checker.counter < 1000:
done = False
if done:
break
dut.log.info("Cocotb test done")
def test1(dut):
random.seed(0)
outputs = [Bundle(dut, "io_outputs_" + str(i)) for i in range(4)]
mappings = [[0x0000, 0x1000], [0x1000, 0x1000], [0x4000, 0x2000],
[0x6000, 0x3000]]
for i in range(100):
dut.io_input_PADDR <= randBits(16)
dut.io_input_PSEL <= randBits(1)
dut.io_input_PENABLE <= randBits(1)
dut.io_input_PWRITE <= randBits(1)
dut.io_input_PWDATA <= randBits(32)
for output in outputs:
output.PREADY <= randBits(1)
output.PRDATA <= randBits(32)
output.PSLVERROR <= randBits(1)
yield Timer(1000)
select = None
for index, mapping in enumerate(mappings):
if (int(dut.io_input_PADDR) >= mapping[0]
and int(dut.io_input_PADDR) < mapping[0] + mapping[1]):
select = index
for index, output in enumerate(outputs):
assertEquals(output.PADDR, dut.io_input_PADDR,
"fail on output PADDR " + str(index))
assertEquals(output.PWRITE, dut.io_input_PWRITE,
"fail on output PWRITE " + str(index))
if select == index:
assertEquals(output.PENABLE, dut.io_input_PENABLE,
"fail on output PENABLE " + str(index))
assertEquals(output.PSEL, dut.io_input_PSEL,
"fail on output PSEL " + str(index))
else:
assertEquals(output.PSEL, 0,
"fail on output PSEL " + str(index))
if select == index:
assertEquals(output.PREADY, dut.io_input_PREADY,
"fail on input PREADY")
assertEquals(output.PRDATA, dut.io_input_PRDATA,
"fail on input PRDATA")
assertEquals(output.PSLVERROR, dut.io_input_PSLVERROR,
"fail on input PSLVERROR")
def test1(dut):
dut.log.info("Cocotb test boot")
from cocotblib.misc import cocotbXHack
cocotbXHack()
random.seed(0)
cocotb.fork(simulationSpeedPrinter(dut.clk))
# elements = [a for a in dut.AhbRam if a._name.startswith("")]
# for e in elements:
# print(str(e._name))
# while True:
# dut.AhbRam.ram_port1_enable <= 1
# dut.AhbRam.ram_port1_mask <= 0xF
# dut.AhbRam.ram_port1_address <= 0X90
# dut.AhbRam.ram_port1_data <= 0xCAFEF00D
#
# dut.AhbRam.reset <= 1
# dut.AhbRam.ram_port1_enable <= 1
# yield Timer(1000)
# dut.AhbRam.ram_port1_enable <= 1
# dut.AhbRam.clk <= 0
# yield Timer(1000)
# dut.AhbRam.ram_port1_enable <= 1
# dut.AhbRam.clk <= 1
# yield Timer(1000)
# dut.AhbRam.ram_port1_enable <= 0
# yield Timer(1000)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset))
readQueue = Queue()
ahb = Bundle(dut, "ahb")
driver = AhbLite3MasterDriver(
ahb, AhbLite3TraficGeneratorWithMemory(10, 32, readQueue), dut.clk,
dut.reset)
checker = AhbLite3MasterReadChecker(ahb, readQueue, dut.clk, dut.reset)
terminaison = AhbLite3Terminaison(ahb, dut.clk, dut.reset)
while True:
yield RisingEdge(dut.clk)
if checker.counter > 4000:
break
dut.log.info("Cocotb test done")
def jtagTest(dut):
from cocotblib.misc import cocotbXHack
cocotbXHack()
uut = dut.uut
log = open('uartTx.log', 'w')
cocotb.fork(simulationSpeedPrinter(uut.io_axiClk))
yield loadIHex(dut, "../hex/dummy.hex", uut.io_axiClk, uut.io_asyncReset)
pinsecClockGen(dut)
yield Timer(1000 * 10)
jtag = JtagMaster(Bundle(uut, "io_jtag"), 20000 * 4, 4)
yield Timer(1000 * 50)
yield jtag.goToIdle()
yield Timer(1000 * 8)
#yield jtagBridgeWrite(jtag,0xF00F0200,0x00030000,4)
#yield Timer(1000*80)
# Check rom write/read via jtag
yield jtagBridgeWrite(jtag, 8, 0x11223344, 4)
yield jtagBridgeWrite(jtag, 10, 0x00550000, 1)
yield jtagBridgeReadAssert(jtag, 8, 4, 0x11553344)
yield jtagBridgeReadAssert(jtag, 10, 2, 0x1155)
yield jtagBridgeWrite(jtag, 0x40004FF0, 0x77665544, 4)
yield Timer(1000 * 50)
yield jtagBridgeReadAssert(jtag, 0x40004FF0, 4, 0x77665544)
yield jtagBridgeWrite(jtag, 0x40004FF2, 0x00FF0000, 1)
yield Timer(1000 * 50)
yield jtagBridgeReadAssert(jtag, 0x40004FF0, 4, 0x77FF5544)
# Check RISCV APB debug module via jtag
yield jtagBridgeWrite(jtag, 0xF00F0200, 1 << 17, 4) #halt CPU
yield jtagBridgeReadAssert(jtag, 0xF00F0200, 4, (1 << 1), 0x0F)
yield jtagBridgeWrite(jtag, 0xF00F0008, 0x99887766, 4) #write R2
yield jtagBridgeReadAssert(jtag, 0xF00F0008, 4, 0x99887766)
yield jtagBridgeReadAssert(jtag, 0xF00F0000 + 10 * 4, 4,
0x55) #Written by dummy.hex
yield Timer(1000 * 500)
def test1(dut):
# random.seed(13)
cocotb.fork(ClockDomainAsyncReset(dut.clk, dut.reset,100000))
cocotb.fork(simulationSpeedPrinter(dut.clk))
sclInterconnect = OpenDrainInterconnect()
sclInterconnect.addHardDriver(dut.io_i2c_scl_write)
sclInterconnect.addHardReader(dut.io_i2c_scl_read)
sdaInterconnect = OpenDrainInterconnect()
sdaInterconnect.addHardDriver(dut.io_i2c_sda_write)
sdaInterconnect.addHardReader(dut.io_i2c_sda_read)
dut.io_config_samplingClockDivider <= 3
dut.io_config_timeout <= 25*10-1
dut.io_config_tsuDat <= 4
softMaster = I2cSoftMaster(sclInterconnect.newSoftConnection(), sdaInterconnect.newSoftConnection(), 2500000,dut.clk)
masterCmds = []
slaveCmds = []
slaveRsps = []
masterRsps = []
masterCmds.append(10)
for frameId in range(50):
masterCmds.append("start")
slaveCmds.append("start")
while True:
for bitId in range(randInt(1,10)):
masterValue = random.uniform(0,1) > 0.5
slaveValue = random.uniform(0,1) > 0.5
slaveEnable = random.uniform(0,1) > 0.5
value = masterValue and (slaveValue or not slaveEnable)
masterCmds.append(masterValue)
slaveRsps.append(slaveValue if slaveEnable else "Z")
slaveCmds.append("drive")
slaveCmds.append(value)
masterRsps.append(value)
if random.uniform(0,1) < 0.1:
slaveCmds.append("drive")
slaveRsps.append(random.uniform(0,1) > 0.5)
masterCmds.append(20)
masterCmds.append("drop")
masterCmds.append(randInt(1,10))
slaveCmds.append("drop")
break
slaveRsps.append("Z")
if random.uniform(0,1) < 0.5:
masterCmds.append("stop")
slaveCmds.append("drive")
slaveCmds.append(False)
slaveCmds.append("stop")
masterCmds.append(randInt(1,10))
break
masterCmds.append("restart")
slaveCmds.append("drive")
slaveCmds.append(True)
slaveCmds.append("restart")
masterThread = fork(i2cMasterThread(softMaster, masterCmds,masterRsps))
slaveThread = fork(i2cSlaveThread(Bundle(dut,"io_bus_cmd"), Bundle(dut,"io_bus_rsp"),slaveCmds,slaveRsps, dut.clk))
yield masterThread.join()
cocotb.fork(SimulationTimeout(100 * 2500000))
while True:
if not slaveCmds and not slaveRsps and not masterRsps:
break
yield Timer(10000)