binary = options.binary
ite = options.ite;
thread = options.thread;
args = []
args.append(thread)
args.append(ite)
# Create a process for a simple "multi-threaded" application
process = Process()
# Set the command
# cmd is a list which begins with the executable (like argv)
process.cmd = [binary] + args
# Set the cpu to use the process as its workload and create thread contexts
for cpu in system.cpu:
cpu.workload = process
cpu.createThreads()
# Set up the pseudo file system for the threads function above
config_filesystem(system)
# set up the root SimObject and start the simulation
root = Root(full_system = False, system = system)
# instantiate all of the objects we've created above
m5.instantiate()
print("Beginning simulation!")
exit_event = m5.simulate()
print('Exiting @ tick {} because {}'.format(
m5.curTick(), exit_event.getCause())
)
system.system_port = system.membus.slave
# system.mmap_using_noreserve = True
if 'dpi' in nf_core_mapping or 'spmc' in nf_core_mapping or 'dpi-queue' in nf_core_mapping:
temp_core_set = []
if 'dpi' in nf_core_mapping:
temp_core_set.extend(nf_core_mapping['dpi'][1:])
if 'dpi-queue' in nf_core_mapping:
temp_core_set.extend(nf_core_mapping['dpi-queue'][1:])
if 'spmc' in nf_core_mapping:
temp_core_set.extend(nf_core_mapping['spmc'][1:])
CacheConfig.config_cache(options, system, temp_core_set)
else:
CacheConfig.config_cache(options, system)
MemConfig.config_mem(options, system)
config_filesystem(system, options)
# reconfig the dpi hardware thread l1 dcache to make it connect to the memory bus directly;
if 'dpi' in nf_core_mapping:
core_set = nf_core_mapping['dpi']
for i, core_id in enumerate(core_set):
if i == 0:
continue
system.cpu[core_id].icache.mem_side = system.membus.slave
system.cpu[core_id].dcache.mem_side = system.membus.slave
system.cpu[core_id].itb.walker.port = system.membus.slave
system.cpu[core_id].dtb.walker.port = system.membus.slave
# print(system.cpu[core_id].icache.mem_side, system.cpu[core_id].dcache.mem_side)
system.cpu[core_id].dcache.size = "8kB"
system.cpu[core_id].dcache.assoc = 1
if options.checker:
system.cpu[i].addCheckerCpu()
if options.bp_type:
bpClass = BPConfig.get(options.bp_type)
system.cpu[i].branchPred = bpClass()
if options.indirect_bp_type:
indirectBPClass = BPConfig.get_indirect(options.indirect_bp_type)
system.cpu[i].branchPred.indirectBranchPred = indirectBPClass()
system.cpu[i].createThreads()
system.redirect_paths = redirect_paths(os.path.expanduser(options.chroot))
config_filesystem(options)
if options.ruby:
Ruby.create_system(options, False, system)
assert(options.num_cpus == len(system.ruby._cpu_ports))
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
for i in range(np):
ruby_port = system.ruby._cpu_ports[i]
# Create the interrupt controller and connect its ports to Ruby
# Note that the interrupt controller is always present but only
# in x86 does it have message ports that need to be connected
system.cpu[i].createInterruptController()
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
for i in range(np):
ruby_port = system.ruby._cpu_ports[i]
# Create the interrupt controller and connect its ports to Ruby
# Note that the interrupt controller is always present but only
# in x86 does it have message ports that need to be connected
system.cpu[i].createInterruptController()
# Connect the cpu's cache ports to Ruby
system.cpu[i].icache_port = ruby_port.slave
system.cpu[i].dcache_port = ruby_port.slave
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].interrupts[0].pio = ruby_port.master
system.cpu[i].interrupts[0].int_master = ruby_port.slave
system.cpu[i].interrupts[0].int_slave = ruby_port.master
system.cpu[i].itb.walker.port = ruby_port.slave
system.cpu[i].dtb.walker.port = ruby_port.slave
else:
MemClass = Simulation.setMemClass(options)
system.membus = SystemXBar()
system.system_port = system.membus.slave
CacheConfig.config_cache(options, system)
MemConfig.config_mem(options, system)
config_filesystem(system, options)
root = Root(full_system = False, system = system)
Simulation.run(options, root, system, FutureClass)
else:
fatal("KvmCPU can only be used in SE mode with x86")
# Sanity check
if options.simpoint_profile:
if not CpuConfig.is_noncaching_cpu(CPUClass):
fatal("SimPoint/BPProbe should be done with an atomic cpu")
if np > 1:
fatal("SimPoint generation not supported with more than one CPUs")
for i in range(np):
system.cpu[i].workload = process
print(process.cmd)
system.redirect_paths = redirect_paths(os.path.expanduser(options.chroot))
config_filesystem(options)
if options.ruby:
Ruby.create_system(options, False, system)
assert(options.num_cpus == len(system.ruby._cpu_ports))
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
for i in range(np):
ruby_port = system.ruby._cpu_ports[i]
# Create the interrupt controller and connect its ports to Ruby
# Note that the interrupt controller is always present but only
# in x86 does it have message ports that need to be connected
system.cpu[i].createInterruptController()
Ruby.create_system(args, False, system)
assert (args.num_cpus == len(system.ruby._cpu_ports))
system.ruby.clk_domain = SrcClockDomain(
clock=args.ruby_clock, voltage_domain=system.voltage_domain)
for i in range(np):
ruby_port = system.ruby._cpu_ports[i]
# Create the interrupt controller and connect its ports to Ruby
# Note that the interrupt controller is always present but only
# in x86 does it have message ports that need to be connected
system.cpu[i].createInterruptController()
# Connect the cpu's cache ports to Ruby
ruby_port.connectCpuPorts(system.cpu[i])
else:
MemClass = Simulation.setMemClass(args)
system.membus = SystemXBar()
system.system_port = system.membus.cpu_side_ports
CacheConfig.config_cache(args, system)
MemConfig.config_mem(args, system)
config_filesystem(system, args)
system.workload = SEWorkload.init_compatible(mp0_path)
if args.wait_gdb:
system.workload.wait_for_remote_gdb = True
root = Root(full_system=False, system=system)
Simulation.run(args, root, system, FutureClass)
# Run application and use the compiled ISA to find the binary
# grab the specific path to the binary
thispath = os.path.dirname(os.path.realpath(__file__))
binary = os.path.join(thispath, '../../../', 'tests/test-progs/threads/bin/',
isa, 'linux/threads')
# Create a process for a simple "multi-threaded" application
process = Process()
# Set the command
# cmd is a list which begins with the executable (like argv)
process.cmd = [binary]
# Set the cpu to use the process as its workload and create thread contexts
for cpu in system.cpu:
cpu.workload = process
cpu.createThreads()
# Set up the pseudo file system for the threads function above
config_filesystem(system)
# set up the root SimObject and start the simulation
root = Root(full_system = False, system = system)
# instantiate all of the objects we've created above
m5.instantiate()
print("Beginning simulation!")
exit_event = m5.simulate()
print('Exiting @ tick {} because {}'.format(
m5.curTick(), exit_event.getCause())
)
