def parse_pracc(self):
control_in = bin2int(self.last_data['in']['data'][0])
control_out = bin2int(self.last_data['out']['data'][0])
# Check if JTAG master acknowledges a pending PrAcc.
if not ((not (control_in & ControlReg.PRACC)) and \
(control_out & ControlReg.PRACC)):
return
ss, es = self.pracc_state.ss, self.pracc_state.es
pracc_write = (control_out & ControlReg.PRNW) != 0
s = 'PrAcc: '
s += 'Store' if pracc_write else 'Load/Fetch'
if pracc_write:
if self.pracc_state.address_out is not None:
s += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out)
if self.pracc_state.data_out is not None:
s += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_out)
else:
if self.pracc_state.address_out is not None:
s += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out)
if self.pracc_state.data_in is not None:
s += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_in)
self.pracc_state.reset()
self.put_at(ss, es, [Ann.PRACC, [s]])
def handle_fastdata(self, val, ann):
spracc_write_desc = {
0: ['0', 'SPrAcc: 0', 'Request completion of Fastdata access'],
1: ['1', 'SPrAcc: 1', 'No effect'],
}
spracc_read_desc = {
0: ['0', 'SPrAcc: 0', 'Fastdata access failure'],
1: ['1', 'SPrAcc: 1', 'Successful completion of Fastdata access'],
}
bitstring = val[0]
bit_sample_pos = val[1]
fastdata_state = bitstring[32]
data = bin2int(bitstring[0:32])
fastdata_bit_pos = bit_sample_pos[32]
data_pos = [bit_sample_pos[31][0], bit_sample_pos[0][1]]
ss_fastdata, es_fastdata = fastdata_bit_pos
ss_data, es_data = data_pos
display_data = [ann, ['0x{:08X}'.format(data)]]
spracc_display_data = []
if ann == Ann.CONTROL_FIELD_IN:
spracc_display_data = [ann, spracc_write_desc[int(fastdata_state)]]
elif ann == Ann.CONTROL_FIELD_OUT:
spracc_display_data = [ann, spracc_read_desc[int(fastdata_state)]]
self.put_at(ss_fastdata, es_fastdata, spracc_display_data)
self.put_at(ss_data, es_data, display_data)
def parse_control_reg(self, ann):
reg_write = ann == Ann.CONTROL_FIELD_IN
control_bit_positions = []
data_select = 'in' if (reg_write) else 'out'
control_bit_positions = self.last_data[data_select]['data'][1]
control_data = self.last_data[data_select]['data'][0]
# Annotate control register fields.
for field in ejtag_control_reg:
start_bit = 31 - field[1]
end_bit = 31 - field[0]
comment = field[2]
value_descriptions = []
if reg_write:
if len(field[3]) < 2:
continue
value_descriptions = field[3][1]
else:
value_descriptions = field[3][0]
ss = control_bit_positions[start_bit][0]
es = control_bit_positions[end_bit][1]
value_str = control_data[end_bit : start_bit + 1]
value_index = bin2int(value_str)
short_desc = comment + ': ' + value_str
long_desc = value_descriptions[value_index] if len(value_descriptions) > value_index else '?'
self.put_at(ss, es, [ann, [long_desc, short_desc]])
def handle_dr_tdo(self, val):
value = bin2int(val[0])
self.check_last_data()
self.last_data['out'] = {'ss': self.ss, 'es': self.es, 'data': val}
if self.state == State.ADDRESS:
self.pracc_state.address_out = value
elif self.state == State.DATA:
self.pracc_state.data_out = value
elif self.state == State.FASTDATA:
self.handle_fastdata(val, Ann.CONTROL_FIELD_OUT)
def handle_ir_tdi(self, val):
code = bin2int(val[0])
hexval = '0x{:02X}'.format(code)
if code in ejtag_insn:
# Format instruction name.
insn = ejtag_insn[code]
s_short = insn[0]
s_long = insn[0] + ': ' + insn[1] + ' (' + hexval + ')'
# Display it and select data register.
self.put_current([Ann.INSTRUCTION, [s_long, s_short]])
else:
self.put_current([Ann.INSTRUCTION, [hexval, 'IR TDI ({})'.format(hexval)]])
self.select_reg(code)
def handle_dr_tdi(self, val):
value = bin2int(val[0])
self.check_last_data()
self.last_data['in'] = {'ss': self.ss, 'es': self.es, 'data': val}
self.pracc_state.ss, self.pracc_state.es = self.ss, self.es
if self.state == State.ADDRESS:
self.pracc_state.address_in = value
elif self.state == State.DATA:
self.pracc_state.data_in = value
elif self.state == State.FASTDATA:
self.handle_fastdata(val, Ann.CONTROL_FIELD_IN)
