def create(args): # System CpuClass, mem_mode, _ = Simulation.setCPUClass(args) sys_cfg = Benchmarks.SysConfig(args.script, args.mem_size) system = FSConfig.makeArmSystem(mem_mode, "VExpress_GEM5_V2", args.num_cpus, sys_cfg, bare_metal=True, security=True) system.voltage_domain = VoltageDomain(voltage=args.sys_voltage) system.clk_domain = SrcClockDomain(clock=args.sys_clock, voltage_domain=system.voltage_domain) system.highest_el_is_64 = True system.have_virtualization = True system.workload.object_file = args.kernel # CPU cluster system.cpu_voltage_domain = VoltageDomain() system.cpu_clk_domain = SrcClockDomain( clock=args.cpu_clock, voltage_domain=system.cpu_voltage_domain) system.cpu = [ CpuClass(clk_domain=system.cpu_clk_domain, cpu_id=i) for i in range(args.num_cpus) ] for cpu in system.cpu: cpu.createThreads() # (gem5 v20.1) Disable FEAT_VHE, prevents booting features = cpu.isa[0].id_aa64mmfr1_el1.getValue() cpu.isa[0].id_aa64mmfr1_el1 = features & ~0xf00 CacheConfig.config_cache(args, system) # Devices system.realview.atp_adapter = ProfileGen(config_files=args.atp_file, exit_when_done=False, init_only=True, disable_watchdog=True, disable_mem_check=True) system.realview.atp_device = ATPDevice(pio_addr=0x2b500000, interrupt=ArmSPI(num=104), atp_id="STREAM") system.realview.attachSmmu([system.realview.atp_device], system.membus) # (gem5 v20.1) Ensure 128 CMDQ entries for compatibility from Linux v5.4 system.realview.smmu.smmu_idr1 = 0x00E00000 # (gem5 v20.2+) Enable SMMUv3 interrupt interface to boot Linux if hasattr(system.realview.smmu, "irq_interface_enable"): system.realview.smmu.irq_interface_enable = True connect_adapter(system.realview.atp_adapter, system.realview.smmu) if args.disk_image: system.disk = [ PciVirtIO(vio=VirtIOBlock(image=create_cow_image(disk))) for disk in args.disk_image ] for disk in system.disk: system.realview.attachPciDevice(disk, system.iobus) # Memory MemConfig.config_mem(args, system) return system
assert(options.num_cpus == len(system.ruby._cpu_ports)) system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, voltage_domain = system.voltage_domain) for i in xrange(np): ruby_port = system.ruby._cpu_ports[i] # Create the interrupt controller and connect its ports to Ruby # Note that the interrupt controller is always present but only # in x86 does it have message ports that need to be connected system.cpu[i].createInterruptController() # Connect the cpu's cache ports to Ruby system.cpu[i].icache_port = ruby_port.slave system.cpu[i].dcache_port = ruby_port.slave if buildEnv['TARGET_ISA'] == 'x86': system.cpu[i].interrupts[0].pio = ruby_port.master system.cpu[i].interrupts[0].int_master = ruby_port.slave system.cpu[i].interrupts[0].int_slave = ruby_port.master system.cpu[i].itb.walker.port = ruby_port.slave system.cpu[i].dtb.walker.port = ruby_port.slave else: MemClass = Simulation.setMemClass(options) system.membus = SystemXBar() system.system_port = system.membus.slave CacheConfig.config_cache(options, system) MemConfig.config_mem(options, system) root = Root(full_system = False, system = system) Simulation.run(options, root, system, FutureClass)
def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "alpha": test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], options.ruby, cmdline=cmdline, cossim_enabled=options.cossim, nodeNum=options.nodeNum) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem( test_mem_mode, options.machine_type, options.num_cpus, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, external_memory=options.external_memory_system, ruby=options.ruby, security=options.enable_security_extensions, cossim_enabled=options.cossim, nodeNum=options.nodeNum, system_clock=options.sys_clock, dev_clk=options.device_clock) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = options.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain( clock=options.sys_clock, voltage_domain=test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain( clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain) if options.kernel is not None: test_sys.kernel = binary(options.kernel) if options.script is not None: test_sys.readfile = options.script if options.lpae: test_sys.have_lpae = True if options.virtualisation: test_sys.have_virtualization = True test_sys.init_param = options.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [ TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in xrange(np) ] if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): test_sys.kvm_vm = KvmVM() if options.ruby: # Check for timing mode because ruby does not support atomic accesses if not (options.cpu_type == "DerivO3CPU" or options.cpu_type == "TimingSimpleCPU"): print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" sys.exit(1) Ruby.create_system(options, True, test_sys, test_sys.iobus, test_sys._dma_ports) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain( clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[ i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[ i].master else: if options.caches or options.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave elif not options.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges=test_sys.mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if options.fastmem: if TestCPUClass != AtomicSimpleCPU: fatal("Fastmem can only be used with atomic CPU!") if (options.caches or options.l2cache): fatal("You cannot use fastmem in combination with caches!") if options.simpoint_profile: if not options.fastmem: # Atomic CPU checked with fastmem option already fatal( "SimPoint generation should be done with atomic cpu and fastmem" ) if np > 1: fatal( "SimPoint generation not supported with more than one CPUs" ) for i in xrange(np): if options.fastmem: test_sys.cpu[i].fastmem = True if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: test_sys.cpu[i].addCheckerCpu() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if options.elastic_trace_en and options.checkpoint_restore == None and \ not options.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) CacheConfig.config_cache(options, test_sys) MemConfig.config_mem(options, test_sys) return test_sys
# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock # is actually used only by the caches connected to the CPU. system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, voltage_domain = system.cpu_voltage_domain) # All cpus belong to a common cpu_clk_domain, therefore running at a common # frequency. for cpu in system.cpu: cpu.clk_domain = system.cpu_clk_domain # BaseCPU no longer has default values for the BaseCPU.isa # createThreads() is needed to fill in the cpu.isa for cpu in system.cpu: cpu.createThreads() # Assign input trace files to the Trace CPU system.cpu.instTraceFile=options.inst_trace_file system.cpu.dataTraceFile=options.data_trace_file # Configure the classic memory system options MemClass = Simulation.setMemClass(options) system.membus = SystemXBar() system.system_port = system.membus.slave CacheConfig.config_cache(options, system) MemConfig.config_mem(options, system) root = Root(full_system = False, system = system) Simulation.run(options, root, system, FutureClass)
def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "alpha": test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem(test_mem_mode, options.machine_type, np, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, external_memory= options.external_memory_system, ruby=options.ruby, security=options.enable_security_extensions) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = options.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, voltage_domain = test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, voltage_domain = test_sys.cpu_voltage_domain) if options.kernel is not None: test_sys.kernel = binary(options.kernel) else: print("Error: a kernel must be provided to run in full system mode") sys.exit(1) if options.script is not None: test_sys.readfile = options.script if options.lpae: test_sys.have_lpae = True if options.virtualisation: test_sys.have_virtualization = True test_sys.init_param = options.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in range(np)] if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass): test_sys.kvm_vm = KvmVM() if options.ruby: bootmem = getattr(test_sys, 'bootmem', None) Ruby.create_system(options, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, voltage_domain = test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master else: if options.caches or options.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave elif not options.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if options.simpoint_profile: if not CpuConfig.is_noncaching_cpu(TestCPUClass): fatal("SimPoint generation should be done with atomic cpu") if np > 1: fatal("SimPoint generation not supported with more than one CPUs") for i in range(np): if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: test_sys.cpu[i].addCheckerCpu() if options.bp_type: bpClass = BPConfig.get(options.bp_type) test_sys.cpu[i].branchPred = bpClass() if options.indirect_bp_type: IndirectBPClass = \ BPConfig.get_indirect(options.indirect_bp_type) test_sys.cpu[i].branchPred.indirectBranchPred = \ IndirectBPClass() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if options.elastic_trace_en and options.checkpoint_restore == None and \ not options.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) CacheConfig.config_cache(options, test_sys) MemConfig.config_mem(options, test_sys) return test_sys
def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "riscv": test_sys = makeBareMetalRiscvSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], args.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem( test_mem_mode, args.machine_type, np, bm[0], args.dtb_filename, bare_metal=args.bare_metal, cmdline=cmdline, external_memory=args.external_memory_system, ruby=args.ruby, vio_9p=args.vio_9p, bootloader=args.bootloader, ) if args.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = args.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage=args.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain( clock=args.sys_clock, voltage_domain=test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain( clock=args.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain) if buildEnv['TARGET_ISA'] == 'riscv': test_sys.workload.bootloader = args.kernel elif args.kernel is not None: test_sys.workload.object_file = binary(args.kernel) if args.script is not None: test_sys.readfile = args.script test_sys.init_param = args.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [ TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in range(np) ] if args.ruby: bootmem = getattr(test_sys, '_bootmem', None) Ruby.create_system(args, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain( clock=args.ruby_clock, voltage_domain=test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.mem_side_ports = test_sys.ruby._io_port.in_ports for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() test_sys.ruby._cpu_ports[i].connectCpuPorts(cpu) else: if args.caches or args.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.mem_side_ports test_sys.iocache.mem_side = test_sys.membus.cpu_side_ports elif not args.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges=test_sys.mem_ranges) test_sys.iobridge.cpu_side_port = test_sys.iobus.mem_side_ports test_sys.iobridge.mem_side_port = test_sys.membus.cpu_side_ports # Sanity check if args.simpoint_profile: if not ObjectList.is_noncaching_cpu(TestCPUClass): fatal("SimPoint generation should be done with atomic cpu") if np > 1: fatal( "SimPoint generation not supported with more than one CPUs" ) for i in range(np): if args.simpoint_profile: test_sys.cpu[i].addSimPointProbe(args.simpoint_interval) if args.checker: test_sys.cpu[i].addCheckerCpu() if not ObjectList.is_kvm_cpu(TestCPUClass): if args.bp_type: bpClass = ObjectList.bp_list.get(args.bp_type) test_sys.cpu[i].branchPred = bpClass() if args.indirect_bp_type: IndirectBPClass = ObjectList.indirect_bp_list.get( args.indirect_bp_type) test_sys.cpu[i].branchPred.indirectBranchPred = \ IndirectBPClass() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if args.elastic_trace_en and args.checkpoint_restore == None and \ not args.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, args) CacheConfig.config_cache(args, test_sys) MemConfig.config_mem(args, test_sys) if ObjectList.is_kvm_cpu(TestCPUClass) or \ ObjectList.is_kvm_cpu(FutureClass): # Assign KVM CPUs to their own event queues / threads. This # has to be done after creating caches and other child objects # since these mustn't inherit the CPU event queue. for i, cpu in enumerate(test_sys.cpu): # Child objects usually inherit the parent's event # queue. Override that and use the same event queue for # all devices. for obj in cpu.descendants(): obj.eventq_index = 0 cpu.eventq_index = i + 1 test_sys.kvm_vm = KvmVM() return test_sys
# use classic memory model. MemClass = Simulation.setMemClass(options) system.membus = SystemXBar() system.system_port = system.membus.slave # system.mmap_using_noreserve = True if 'dpi' in nf_core_mapping or 'spmc' in nf_core_mapping or 'dpi-queue' in nf_core_mapping: temp_core_set = [] if 'dpi' in nf_core_mapping: temp_core_set.extend(nf_core_mapping['dpi'][1:]) if 'dpi-queue' in nf_core_mapping: temp_core_set.extend(nf_core_mapping['dpi-queue'][1:]) if 'spmc' in nf_core_mapping: temp_core_set.extend(nf_core_mapping['spmc'][1:]) CacheConfig.config_cache(options, system, temp_core_set) else: CacheConfig.config_cache(options, system) MemConfig.config_mem(options, system) config_filesystem(system, options) # reconfig the dpi hardware thread l1 dcache to make it connect to the memory bus directly; if 'dpi' in nf_core_mapping: core_set = nf_core_mapping['dpi'] for i, core_id in enumerate(core_set): if i == 0: continue system.cpu[core_id].icache.mem_side = system.membus.slave system.cpu[core_id].dcache.mem_side = system.membus.slave system.cpu[core_id].itb.walker.port = system.membus.slave system.cpu[core_id].dtb.walker.port = system.membus.slave
system.workload.dtb_filename = args.dtb_filename else: generateDtb(system) system.workload.dtb_filename = path.join(m5.options.outdir, 'device.dtb') # Default DTB address if bbl is bulit with --with-dts option system.workload.dtb_addr = 0x87e00000 # Linux boot command flags if args.command_line: system.workload.command_line = args.command_line else: kernel_cmd = ["console=ttyS0", "root=/dev/vda", "ro"] system.workload.command_line = " ".join(kernel_cmd) # ---------------------------- Default Setup --------------------------- # if args.elastic_trace_en and args.checkpoint_restore == None and \ not args.fast_forward: CpuConfig.config_etrace(CPUClass, system.cpu, args) CacheConfig.config_cache(args, system) MemConfig.config_mem(args, system) root = Root(full_system=True, system=system) Simulation.setWorkCountOptions(system, args) Simulation.run(args, root, system, FutureClass)
def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "riscv": test_sys = makeBareMetalRiscvSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem( test_mem_mode, options.machine_type, np, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, external_memory=options.external_memory_system, ruby=options.ruby, security=options.enable_security_extensions, vio_9p=options.vio_9p, bootloader=options.bootloader, ) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = options.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain( clock=options.sys_clock, voltage_domain=test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain( clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain) if buildEnv['TARGET_ISA'] == 'riscv': test_sys.workload.bootloader = options.kernel elif options.kernel is not None: test_sys.workload.object_file = binary(options.kernel) if options.script is not None: test_sys.readfile = options.script if options.lpae: test_sys.have_lpae = True if options.virtualisation: test_sys.have_virtualization = True test_sys.init_param = options.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [ TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in range(np) ] if ObjectList.is_kvm_cpu(TestCPUClass) or \ ObjectList.is_kvm_cpu(FutureClass): test_sys.kvm_vm = KvmVM() if options.ruby: bootmem = getattr(test_sys, '_bootmem', None) Ruby.create_system(options, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain( clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[ i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[ i].master else: if options.caches or options.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave elif not options.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges=test_sys.mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if options.simpoint_profile: if not ObjectList.is_noncaching_cpu(TestCPUClass): fatal("SimPoint generation should be done with atomic cpu") if np > 1: fatal( "SimPoint generation not supported with more than one CPUs" ) for i in range(np): if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: test_sys.cpu[i].addCheckerCpu() if not ObjectList.is_kvm_cpu(TestCPUClass): if options.bp_type: bpClass = ObjectList.bp_list.get(options.bp_type) test_sys.cpu[i].branchPred = bpClass() if options.indirect_bp_type: IndirectBPClass = ObjectList.indirect_bp_list.get( options.indirect_bp_type) test_sys.cpu[i].branchPred.indirectBranchPred = \ IndirectBPClass() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if options.elastic_trace_en and options.checkpoint_restore == None and \ not options.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) CacheConfig.config_cache(options, test_sys) MemConfig.config_mem(options, test_sys) ''' pmu_listeners = [] for cpu in test_sys.cpu: if buildEnv['TARGET_ISA'] in "arm": for isa in cpu.isa: isa.pmu = ArmPMU(interrupt=ArmPPI(num=20)) isa.pmu.addArchEvents( cpu=cpu, dtb=cpu.dtb, itb=cpu.itb, icache=getattr(cpu, "icache", None), dcache=getattr(cpu, "dcache", None), l2cache=getattr(test_sys, "l2", None)) pmu_listeners.append(PmuListener( cpu=cpu, dtb=cpu.dtb, itb=cpu.itb, icache=getattr(cpu, "icache", None), dcache=getattr(cpu, "dcache", None), l2cache=getattr(test_sys, "l2", None), bpred=getattr(cpu, "branchPred", None), )) test_sys.pmu_listeners = pmu_listeners ''' for cpu in test_sys.cpu: if buildEnv['TARGET_ISA'] in "arm": for isa in cpu.isa: isa.pmu = ArmPMU(interrupt=ArmPPI(num=20)) isa.pmu.addArchEvents(cpu=cpu, dtb=cpu.dtb, itb=cpu.itb, icache=getattr(cpu, "icache", None), dcache=getattr(cpu, "dcache", None), l2cache=getattr(test_sys, "l2", None)) return test_sys
def build_test_system(np, simplessd): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "alpha": test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, simplessd, options.num_cpus, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem( test_mem_mode, options.machine_type, simplessd, options.num_cpus, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, external_memory=options.external_memory_system, ruby=options.ruby, security=options.enable_security_extensions) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = options.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain( clock=options.sys_clock, voltage_domain=test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain( clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain) if options.kernel is not None: test_sys.kernel = binary(options.kernel) if options.script is not None: test_sys.readfile = options.script if options.lpae: test_sys.have_lpae = True if options.virtualisation: test_sys.have_virtualization = True test_sys.init_param = options.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [ TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in range(np) ] if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass): test_sys.kvm_vm = KvmVM() if buildEnv['TARGET_ISA'] in "x86": test_sys.eventq_index = np if options.ruby: bootmem = getattr(test_sys, 'bootmem', None) Ruby.create_system(options, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain( clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[ i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[ i].master else: gicv2m_range = AddrRange(0x2c1c0000, 0x2c1d0000 - 1) if options.caches or options.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave if buildEnv['TARGET_ISA'] in "arm": if options.machine_type == "VExpress_GEM5_V1": test_sys.iobridge = Bridge(delay='50ns', ranges=[gicv2m_range]) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave elif not options.external_memory_system: mem_ranges = list(test_sys.mem_ranges) # Copy list not reference # Bypass MSI/MSI-X if buildEnv['TARGET_ISA'] in "arm": if options.machine_type == "VExpress_GEM5_V1": mem_ranges.append(gicv2m_range) test_sys.iobridge = Bridge(delay='50ns', ranges=mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if options.simpoint_profile: if not CpuConfig.is_noncaching_cpu(TestCPUClass): fatal("SimPoint generation should be done with atomic cpu") if np > 1: fatal( "SimPoint generation not supported with more than one CPUs" ) for i in range(np): if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: test_sys.cpu[i].addCheckerCpu() if options.bp_type: bpClass = BPConfig.get(options.bp_type) test_sys.cpu[i].branchPred = bpClass() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if options.elastic_trace_en and options.checkpoint_restore == None and \ not options.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) CacheConfig.config_cache(options, test_sys) MemConfig.config_mem(options, test_sys) if buildEnv['TARGET_ISA'] in "x86": lapics = [] for i in range(np): lapics.append(test_sys.cpu[i].interrupts[0]) test_sys.msi_handler.lapics = lapics if buildEnv['TARGET_ISA'] in "x86" and test_sys.eventq_index == np: test_sys.eventq_index = 0 for idx, cpu in enumerate(test_sys.cpu): for obj in cpu.descendants(): obj.eventq_index = test_sys.eventq_index cpu.eventq_index = idx + 1 return test_sys
# in x86 does it have message ports that need to be connected system.cpu[i].createInterruptController() # Connect the cpu's cache ports to Ruby system.cpu[i].icache_port = ruby_port.slave system.cpu[i].dcache_port = ruby_port.slave if buildEnv['TARGET_ISA'] == 'x86': system.cpu[i].interrupts[0].pio = ruby_port.master system.cpu[i].interrupts[0].int_master = ruby_port.slave system.cpu[i].interrupts[0].int_slave = ruby_port.master system.cpu[i].itb.walker.port = ruby_port.slave system.cpu[i].dtb.walker.port = ruby_port.slave else: print("we are doing this building here") MemClass = Simulation.setMemClass(options) system.membus = SystemXBar() system.system_port = system.membus.slave CacheConfig.config_cache(options, system, encoder) MemConfig.config_mem(options, system) root = Root(full_system=False, system=system) #root.encrypter = EncodeObject() print('--------------') print(FutureClass) print(options) print(root) print(system) print(options.test_Flag) print('-----------') Simulation.run(options, root, system, FutureClass)
def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "alpha": test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem( test_mem_mode, options.machine_type, options.membus_width, options, options.num_cpus, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, ignore_dtb=options.generate_dtb, external_memory=options.external_memory_system, ruby=options.ruby, security=options.enable_security_extensions) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = options.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain( clock=options.sys_clock, voltage_domain=test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain( clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain) if options.kernel is not None: test_sys.kernel = binary(options.kernel) if options.script is not None: test_sys.readfile = options.script if options.lpae: test_sys.have_lpae = True if options.virtualisation: test_sys.have_virtualization = True test_sys.init_param = options.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [ TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in xrange(np) ] if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): test_sys.kvm_vm = KvmVM() if options.ruby: bootmem = getattr(test_sys, 'bootmem', None) Ruby.create_system(options, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain( clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[ i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[ i].master else: if options.caches or options.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave elif not options.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges=test_sys.mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if options.fastmem: if TestCPUClass != AtomicSimpleCPU: fatal("Fastmem can only be used with atomic CPU!") if (options.caches or options.l2cache): fatal("You cannot use fastmem in combination with caches!") if options.simpoint_profile: if not options.fastmem: # Atomic CPU checked with fastmem option already fatal( "SimPoint generation should be done with atomic cpu and fastmem" ) if np > 1: fatal( "SimPoint generation not supported with more than one CPUs" ) for i in xrange(np): if options.fastmem: test_sys.cpu[i].fastmem = True if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: test_sys.cpu[i].addCheckerCpu() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if options.elastic_trace_en and options.checkpoint_restore == None and \ not options.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) if buildEnv['TARGET_ISA'] != "arm" and options.workload_automation_vio: warn("Ignoring --workload-automation-vio. It is unsupported on " "non-ARM systems.") elif options.workload_automation_vio: from m5.objects import PciVirtIO, VirtIO9PDiod viopci = PciVirtIO( pci_bus=0, pci_dev=test_sys.realview._num_pci_dev, pci_func=0, InterruptPin=1, InterruptLine=test_sys.realview._num_pci_int_line) test_sys.realview._num_pci_dev = test_sys.realview._num_pci_dev + 1 test_sys.realview._num_pci_int_line = test_sys.realview._num_pci_int_line + 1 viopci.vio = VirtIO9PDiod() viopci.vio.root = options.workload_automation_vio viopci.vio.socketPath = "/home/yqureshi/shares/local/scrap/temp" test_sys.realview.viopci = viopci test_sys.realview.viopci.dma = test_sys.iobus.slave test_sys.realview.viopci.pio = test_sys.iobus.master CacheConfig.config_cache(options, test_sys) MemConfig.config_mem(options, test_sys) return test_sys