def main(): dut = Refresher(13, 2, tRP=3, tREFI=100, tRFC=5) logger = CommandLogger(dut.cmd) granter = Granter(dut.req, dut.ack) fragment = dut.get_fragment() + logger.get_fragment() + granter.get_fragment() sim = Simulator(fragment) sim.run(400)
def __init__(self):
self.req = Interface(32, 32, 1, sdram_timing.req_queue_size,
sdram_phy.read_latency, sdram_phy.write_latency)
self.submodules.dut = BankMachine(sdram_geom, sdram_timing, 2, 0,
self.req)
self.submodules.logger = CommandLogger(self.dut.cmd, True)
self.generator = my_generator()
self.dat_ack_cnt = 0
def main():
hub = Hub(12, 128, 2)
initiator = Initiator(hub.get_port(), my_generator())
hub.finalize()
dut = BankMachine(sdram_geom, sdram_timing, 2, 0, hub.get_slots())
logger = CommandLogger(dut.cmd, True)
completer = Completer(hub, dut.cmd)
def end_simulation(s):
s.interrupt = initiator.done
fragment = hub.get_fragment() + initiator.get_fragment() + \
dut.get_fragment() + logger.get_fragment() + completer.get_fragment() + \
Fragment(sim=[end_simulation])
sim = Simulator(fragment, TopLevel("my.vcd"))
sim.run()
def __init__(self):
self.submodules.dut = Refresher(13, 2, tRP=3, tREFI=100, tRFC=5)
self.submodules.logger = CommandLogger(self.dut.cmd)
self.submodules.granter = Granter(self.dut.req, self.dut.ack)
